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* Write patterns for the various shl and srl patterns that don't involveNate Begeman2005-10-193-50/+71
| | | | | | doing something clever. llvm-svn: 23824
* Push processor descriptions to the top of target and add command line info.Jim Laskey2005-10-197-23/+80
| | | | llvm-svn: 23820
* now that tblgen is smarter, use integers directly. This should help Andrew tooChris Lattner2005-10-191-4/+1
| | | | llvm-svn: 23818
* teach ppc backend these are copiesChris Lattner2005-10-191-1/+2
| | | | llvm-svn: 23813
* Convert these cases to patternsChris Lattner2005-10-192-37/+11
| | | | llvm-svn: 23811
* Woo, it kinda works. We now generate this atrociously bad, but correct,Nate Begeman2005-10-192-23/+54
| | | | | | | | | | | | | | | | | | | | | | | code for long long foo(long long a, long long b) { return a + b; } _foo: or r2, r3, r3 or r3, r4, r4 or r4, r5, r5 or r5, r6, r6 rldicr r2, r2, 32, 31 rldicl r3, r3, 0, 32 rldicr r4, r4, 32, 31 rldicl r5, r5, 0, 32 or r2, r3, r2 or r3, r5, r4 add r4, r3, r2 rldicl r2, r4, 32, 32 or r4, r4, r4 or r3, r2, r2 blr llvm-svn: 23809
* apply some tblgen majik to simplify the X register definitionsChris Lattner2005-10-191-19/+19
| | | | llvm-svn: 23805
* Teach Legalize how to do something with EXTRACT_ELEMENT when the type ofNate Begeman2005-10-191-7/+30
| | | | | | the pair of elements is a legal type. llvm-svn: 23804
* Make a new reg class for 64 bit regs that aliases the 32 bit regs. ThisNate Begeman2005-10-193-9/+50
| | | | | | | | | | | will have to tide us over until we get real subreg support, but it prevents the PrologEpilogInserter from spilling 8 byte GPRs on a G4 processor. Add some initial support for TRUNCATE and ANY_EXTEND, but they don't currently work due to issues with ScheduleDAG. Something wll have to be figured out. llvm-svn: 23803
* Add the ability to lower return instructions to TargetLowering. ThisNate Begeman2005-10-184-7/+39
| | | | | | | allows us to lower legal return types to something else, to meet ABI requirements (such as that i64 be returned in two i32 regs on Darwin/ppc). llvm-svn: 23802
* Fix Generic/2005-10-18-ZeroSizeStackObject.ll by not requesting a zeroChris Lattner2005-10-181-0/+1
| | | | | | sized stack object if either the array size or the type size is zero. llvm-svn: 23801
* remove hackChris Lattner2005-10-181-3/+1
| | | | llvm-svn: 23797
* Simple edits; remove unimplimented cases and clarify long haul SLU cases.Jim Laskey2005-10-184-61/+3
| | | | llvm-svn: 23788
* Fix the JIT encoding of LWA, LD, STD, and STDU.Chris Lattner2005-10-183-4/+20
| | | | llvm-svn: 23787
* Checking in first round of scheduling tablegen files. Not tied in as yet.Jim Laskey2005-10-186-0/+947
| | | | llvm-svn: 23786
* add a caseChris Lattner2005-10-181-0/+3
| | | | llvm-svn: 23785
* Add an option to this pass. If it is set, we are allowed to internalizeChris Lattner2005-10-181-4/+10
| | | | | | | all but main. If it's not set, we can still internalize, but only if an explicit symbol list is provided. llvm-svn: 23783
* Fold (select C, load A, load B) -> load (select C, A, B). This happens quiteChris Lattner2005-10-181-7/+82
| | | | | | | | | | | | | | | | | | | | | | a lot throughout many programs. In particular, specfp triggers it a bunch for constant FP nodes when you have code like cond ? 1.0 : -1.0. If the PPC ISel exposed the loads implicit in pic references to external globals, we would be able to eliminate a load in cases like this as well: %X = external global int %Y = external global int int* %test4(bool %C) { %G = select bool %C, int* %X, int* %Y ret int* %G } Note that this breaks things that use SrcValue's (see the fixme), but since nothing uses them yet, this is ok. Also, simplify some code to use hasOneUse() on an SDOperand instead of hasNUsesOfValue directly. llvm-svn: 23781
* Do the right thing and enable 64 bit regs under the control of a subtargetNate Begeman2005-10-183-8/+10
| | | | | | | option. Currently the only way to enable this is to specify the 64bitregs mattr flag. It is never enabled by default on any config yet. llvm-svn: 23779
* First bits of 64 bit PowerPC stuff, currently disabled. A lot of this isNate Begeman2005-10-189-88/+154
| | | | | | purely mechanical. llvm-svn: 23778
* Implement some feedback from Chris re: constant canonicalizationNate Begeman2005-10-181-39/+27
| | | | llvm-svn: 23777
* Legalize BUILD_PAIR appropriately for upcoming 64 bit PowerPC work.Nate Begeman2005-10-181-0/+25
| | | | llvm-svn: 23776
* fold fmul X, +2.0 -> fadd X, X;Nate Begeman2005-10-171-14/+17
| | | | llvm-svn: 23774
* Make this work for FP constantexprsChris Lattner2005-10-171-2/+3
| | | | llvm-svn: 23773
* Oops, X+0.0 isn't foldable, but X+-0.0 is.Chris Lattner2005-10-171-4/+5
| | | | llvm-svn: 23772
* relax this a bit, as we only support the default rounding modeChris Lattner2005-10-171-2/+4
| | | | llvm-svn: 23771
* add a trivial foldChris Lattner2005-10-171-0/+4
| | | | llvm-svn: 23764
* More PPC32 -> PPC changes, as well as merging some classes that wereNate Begeman2005-10-1620-170/+152
| | | | | | redundant after the change. llvm-svn: 23759
* Fix this logic.Chris Lattner2005-10-151-1/+1
| | | | llvm-svn: 23756
* Add a case we were missing that was causing us to fail ↵Chris Lattner2005-10-151-0/+14
| | | | | | CodeGen/PowerPC/rlwinm.ll:test3 llvm-svn: 23755
* Remove some dead code now that the dag combiner exists.Nate Begeman2005-10-151-15/+0
| | | | llvm-svn: 23754
* Remove some dead code: the ORI/ORIS cases are autogen'd. This makesChris Lattner2005-10-151-42/+1
| | | | | | SelectIntImmediateExpr dead. llvm-svn: 23753
* prune #includesChris Lattner2005-10-152-3/+2
| | | | llvm-svn: 23752
* These instructions are now autogeneratedChris Lattner2005-10-151-34/+0
| | | | llvm-svn: 23751
* Add a pattern for FSQRTSChris Lattner2005-10-151-1/+1
| | | | llvm-svn: 23750
* remove dead codeChris Lattner2005-10-151-8/+3
| | | | llvm-svn: 23749
* Use getExtLoad here instead of getNode, as extloads produce two values. ThisChris Lattner2005-10-151-2/+3
| | | | | | fixes a legalize failure on SPASS for itanium. llvm-svn: 23747
* remove broken SRA/rlwimi caseChris Lattner2005-10-151-11/+2
| | | | llvm-svn: 23746
* Rename PPC32*.h to PPC*.hChris Lattner2005-10-1414-17/+16
| | | | | | This completes the grand PPC file renaming llvm-svn: 23745
* Merge PPCJITInfo.h and PPC32JITInfo.h. Note that the PowerPCJITInfoChris Lattner2005-10-145-45/+22
| | | | | | and PPC32JITInfo classes should be merged. llvm-svn: 23744
* Rename PowerPC*.h to PPC*.hChris Lattner2005-10-1417-19/+19
| | | | llvm-svn: 23743
* Rename PowerPCInstrBuilder.h -> PPC*Chris Lattner2005-10-144-3/+3
| | | | llvm-svn: 23742
* Nuke the PowerPCTargetMachine.h header. Note that the PowerPCTargetMachineChris Lattner2005-10-144-49/+24
| | | | | | still should be merged into the PPC32TargetMachine class llvm-svn: 23741
* Rename PowerPC*.td -> PPC*.tdChris Lattner2005-10-144-4/+4
| | | | llvm-svn: 23740
* These are deadChris Lattner2005-10-142-74/+0
| | | | llvm-svn: 23739
* Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.tdChris Lattner2005-10-149-32/+70
| | | | llvm-svn: 23738
* Like the comment says...Chris Lattner2005-10-141-6/+0
| | | | llvm-svn: 23737
* Nuke PowerPCInstrFormats.h, its contents are dead. Remove the definitionsChris Lattner2005-10-146-87/+11
| | | | | | from the .td file that correspond to it llvm-svn: 23736
* Properly split f32 and f64 into separate register classes for scalar sse fpNate Begeman2005-10-145-79/+78
| | | | | | fixing a bunch of nasty hackery llvm-svn: 23735
* Remove an unnecsesary file. PPC32 and PPC64 share architected registers.Nate Begeman2005-10-144-52/+38
| | | | | | | We will decide with subtarget support whether we ever use an i64 register class. llvm-svn: 23734
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