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* [AArch64] Implement the isLegalAddressingMode and getScalingFactorCost APIs.Chad Rosier2014-04-122-0/+77
| | | | llvm-svn: 206089
* blockfreq: Rename BlockFrequencyImpl to BlockFrequencyInfoImplDuncan P. N. Exon Smith2014-04-112-4/+4
| | | | | | | | | | | | This is a shared implementation class for BlockFrequencyInfo and MachineBlockFrequencyInfo, not for BlockFrequency, a related (but distinct) class. No functionality change. <rdar://problem/14292693> llvm-svn: 206083
* blockfreq: Use getSuccessorIndex()Duncan P. N. Exon Smith2014-04-111-5/+3
| | | | | | | | No functionality change. <rdar://problem/14292693> llvm-svn: 206082
* Pull out a named variable for the cached section names to aid readability.David Blaikie2014-04-111-6/+8
| | | | | | Based on a code review suggestion from Eric Christopher in r205990 llvm-svn: 206080
* Add ARM64 CLS patternsLouis Gerbarg2014-04-111-0/+6
| | | | | | | | | This patch adds patterns to generate the cls instruction ARM64. Includes tests for 64 bit and 32 bit operands. rdar://15611957 llvm-svn: 206079
* Format fixes for r205990David Blaikie2014-04-111-5/+12
| | | | llvm-svn: 206078
* [RegAllocGreedy][Last Chance Recoloring] Change the name of the exhaustive ↵Quentin Colombet2014-04-111-1/+1
| | | | | | | | | | | search option. fexhaustive-register-search => exhaustive-register-search 'f' is a Clang thing! This is related to PR18747. llvm-svn: 206075
* [RegAllocGreedy][Last Chance Recoloring] Addition ofQuentin Colombet2014-04-111-6/+14
| | | | | | | | | | | -fexhaustive-register-search option to allow an exhaustive search during last chance recoloring. This is related to PR18747 Patch by MAYUR PANDEY <mayur.p@samsung.com>. llvm-svn: 206072
* R600: Check if a sextload should be used for parameter loads.Matt Arsenault2014-04-113-14/+20
| | | | | | | | | | Through some oddity where truncate (sextload x) isn't folded into an anyextload for vectors, the sextload remains if the vector isn't immediately scalarized. This keeps the expected zextload instructions in the kernel-args test when small type vectors aren't scalarized. llvm-svn: 206070
* Remove redundant symbolization support from MCDisassembler interface.Lang Hames2014-04-117-235/+285
| | | | | | | | | | | | | | | | | MCDisassembler has an MCSymbolizer member that is meant to take care of symbolizing during disassembly, but it also has several methods that enable the disassembler to do symbolization internally (i.e. without an attached symbolizer object). There is no need for this duplication, but ARM64 had been making use of it. This patch moves the ARM64 symbolization logic out of ARM64Disassembler and into an ARM64ExternalSymbolizer class, and removes the duplicated MCSymbolizer functionality from the MCDisassembler interface. Symbolization will now be done exclusively through MCSymbolizers. There should be no impact on disassembly for any platform, but this allows us to tidy up the MCDisassembler interface and simplify the process of (and invariants related to) disassembler setup. llvm-svn: 206063
* [Register Coalescer] Fix wrong live-range information with rematerialization.Quentin Colombet2014-04-111-0/+21
| | | | | | | | | | | | | | | When rematerializing an instruction that defines a super register that would be used by a physical subregisters we use the related physical super register for the definition. To keep the live-range information accurate, all the defined subregisters must be marked as dead def, otherwise the register allocation may miss some interferences. Working on a reduced test-case! <rdar://problem/16582185> llvm-svn: 206060
* R600/SI: Refactor SOPC classes slightly.Matt Arsenault2014-04-113-20/+28
| | | | | | | Better match what is done for VOPC to eventually prefer selecting these. llvm-svn: 206048
* Don't lose the thumb bit by using relocations with sections.Rafael Espindola2014-04-111-0/+7
| | | | | | This fixes a regression from r205076. llvm-svn: 206047
* Fix shift by constants for vector.Matt Arsenault2014-04-112-13/+23
| | | | | | ashr <N x iM>, <N x iM> M -> undef llvm-svn: 206045
* Debug info: Store the DIVariable in DebugLocEntry also for constants,Adrian Prantl2014-04-112-9/+11
| | | | | | | | so DwarfDebug::emitDebugLocEntry can emit them with the correct signedness. rdar://problem/15928306 llvm-svn: 206042
* Move ExtractVectorElements to SelectionDAG.Matt Arsenault2014-04-113-23/+22
| | | | | | | This seems generally useful, and makes sense to go along with SplitVector. llvm-svn: 206041
* SelectionDAG: Use helper function to improve legalization of ISD::MULTom Stellard2014-04-111-0/+17
| | | | | | | | The TargetLowering::expandMUL() helper contains lowering code extracted from the DAGTypeLegalizer and allows the SelectionDAGLegalizer to expand more ISD::MUL patterns without having to use a library call. llvm-svn: 206037
* SelectionDAG: Factor ISD::MUL lowering code out of DAGTypeLegalizerTom Stellard2014-04-112-67/+113
| | | | | | | | | | | This code has been moved to a new function in the TargetLowering class called expandMUL(). The purpose of this is to be able to share lowering code between the SelectionDAGLegalize and DAGTypeLegalizer classes. No functionality changed intended. llvm-svn: 206036
* Fix use-after-free bug caught by address sanitizer:Diego Novillo2014-04-111-1/+1
| | | | | | | | http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/2959 The location string is returned as a std::string, not a StringRef. llvm-svn: 206032
* [yaml2obj][ELF] ELF Relocations Support.Simon Atanasyan2014-04-111-3/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch implements support for both relocation record formats: Elf_Rel and Elf_Rela. It is possible to define relocation against symbol only. Relocations against sections will be implemented later. Now yaml2obj recognizes X86_64, MIPS and Hexagon relocation types. Example of relocation section specification: Sections: - Name: .text Type: SHT_PROGBITS Content: "0000000000000000" AddressAlign: 16 Flags: [SHF_ALLOC] - Name: .rel.text Type: SHT_REL Info: .text AddressAlign: 4 Relocations: - Offset: 0x1 Symbol: glob1 Type: R_MIPS_32 - Offset: 0x2 Symbol: glob2 Type: R_MIPS_CALL16 The patch reviewed by Michael Spencer, Sean Silva, Shankar Easwaran. llvm-svn: 206017
* Implement depth_first and inverse_depth_first range factory functions.David Blaikie2014-04-118-40/+28
| | | | | | | | | | | | | | Also updated as many loops as I could find using df_begin/idf_begin - strangely I found no uses of idf_begin. Is that just used out of tree? Also a few places couldn't use df_begin because either they used the member functions of the depth first iterators or had specific ordering constraints (I added a comment in the latter case). Based on a patch by Jim Grosbach. (Jim - you just had iterator_range<T> where you needed iterator_range<idf_iterator<T>>) llvm-svn: 206016
* [c++11] Range'ify use list loops in InstrEmitter.Jim Grosbach2014-04-111-9/+3
| | | | llvm-svn: 206015
* [c++11] Range'ify use list loops in DAGCombiner.Jim Grosbach2014-04-111-18/+7
| | | | llvm-svn: 206014
* [ARM64,C++11] Range'ify use-lists iterators in address type promotion.Jim Grosbach2014-04-111-8/+4
| | | | llvm-svn: 206013
* Use value types instead of 'new'd objects to store dwarf labels for asm filesDavid Blaikie2014-04-111-22/+9
| | | | llvm-svn: 206009
* [ARM64,C++11]: Range'ify use-list iterators in DAGToDAG.Jim Grosbach2014-04-111-6/+3
| | | | llvm-svn: 206007
* [ARM64,C++11]: More range-based loop simplification.Jim Grosbach2014-04-111-3/+2
| | | | llvm-svn: 206006
* Remove lazy-initialization of section caches in MCContextDavid Blaikie2014-04-101-52/+18
| | | | | | | | This seems to have been a cargo-culted habit from the very first such cache which didn't have any specific justification (but might've been a layering constraint at the time). llvm-svn: 206003
* Move the segmented stack switch to a function attributeReid Kleckner2014-04-105-20/+53
| | | | | | | | | This removes the -segmented-stacks command line flag in favor of a per-function "split-stack" attribute. Patch by Luqman Aden and Alex Crichton! llvm-svn: 205997
* [ARM64,C++11]: Range'ify loops in InstrInfo.Jim Grosbach2014-04-101-10/+5
| | | | llvm-svn: 205992
* Reimplement debug info compression by compressing the whole section, rather ↵David Blaikie2014-04-102-0/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | than a fragment. To support compressing the debug_line section that contains multiple fragments (due, I believe, to variation in choices of line table encoding depending on the size of instruction ranges in the actual program code) we needed to support compressing multiple MCFragments in a single pass. This patch implements that behavior by mutating the post-relaxed and relocated section to be the compressed form of its former self, including renaming the section. This is a more flexible (and less invasive, to a degree) implementation that will allow for other features such as "use compression only if it's smaller than the uncompressed data". Compressing debug_frame would be a possible further extension to this work, but I've left it for now. The hurdle there is alignment sections - which might require going as far as to refactor MCAssembler.cpp:writeFragment to handle writing to a byte buffer or an MCObjectWriter (there's already a virtual call there, so it shouldn't add substantial compile-time cost) which could in turn involve refactoring MCAsmBackend::writeNopData to use that same abstraction... which involves touching all the backends. This would remove the limited handling of fragment writing seen in ELFObjectWriter.cpp:getUncompressedData which would be nice - but it's more invasive. I did discover that I (perhaps obviously) don't need to handle relocations when I rewrite the fragments - since the relocations have already been applied and computed (and stored into ELFObjectWriter::Relocations) by this stage (necessarily, because we need to have written any immediate values or assembly-time relocations into the data already before we compress it, which we have). The test case doesn't necessarily cover that in detail - I can add more test coverage if that's preferred. llvm-svn: 205990
* Revert debug info compression support.David Blaikie2014-04-103-58/+1
| | | | | | | | | | To support compression for debug_line and debug_frame a different approach is required. To simplify review, revert the old implementation and XFAIL the test case. New implementation to follow shortly. Reverts r205059 and r204958. llvm-svn: 205989
* [ARM64,C++11]: Range'ify loops in the conditional-compare pass.Jim Grosbach2014-04-101-27/+25
| | | | llvm-svn: 205988
* For the ARM integrated assembler add checking of theKevin Enderby2014-04-103-433/+894
| | | | | | | | | | | | | | | | | | | alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
* Debug info: Factor the retrieving of the DIVariable from a MachineInstrAdrian Prantl2014-04-101-3/+2
| | | | | | into a function. llvm-svn: 205973
* [mips] NotMips64 predicate is really a test for 32-bit GPR's.Daniel Sanders2014-04-102-4/+6
| | | | | | | | | | | | | | | | Summary: Similarly, the HasMips64 on the 64-bit move InstAlias is a test for 64-bit GPR's. No functional change. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3263 llvm-svn: 205968
* Reapply "SLPVectorizer: Ignore users that are insertelements we can ↵Arnold Schwaighofer2014-04-101-30/+65
| | | | | | | | | reschedule them" This commit reapplies 205018. After 205855 we should correctly vectorize intrinsics. llvm-svn: 205965
* [mips] Switch the MIPS-III and MIPS-IV assembler tests to use -mcpu=mips4.Daniel Sanders2014-04-101-2/+2
| | | | | | | | | | | | | | | | | | Summary: It is now the smallest superset for these ISA's. FeatureMips4 now contains FeatureFPIdx since [ls][dw]xc1 were added in MIPS-IV. Made the FPIdx feature bit lowercase so that it can be used in the -mattr option. Depends on D3274 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3275 llvm-svn: 205964
* ARM64/*/LLVMBuild.txt: Prune redundant deps.NAKAMURA Takumi2014-04-103-3/+3
| | | | llvm-svn: 205963
* LLVMBuild.txt: Add missing dependencies.NAKAMURA Takumi2014-04-107-7/+7
| | | | llvm-svn: 205962
* LLVMBuild.txt: Reformat.NAKAMURA Takumi2014-04-1014-16/+12
| | | | llvm-svn: 205961
* YAMLIO: Allow scalars to dictate quotation rulesDavid Majnemer2014-04-102-10/+6
| | | | | | | Introduce ScalarTraits::mustQuote which determines whether or not a StringRef needs quoting before it is acceptable to output. llvm-svn: 205955
* Use range-based for loops. No functionality change.Simon Atanasyan2014-04-101-25/+16
| | | | llvm-svn: 205953
* Fix abuse of StringRef on ARM64SysReg::MRSMapper::toString(Val, Valid).NAKAMURA Takumi2014-04-101-4/+4
| | | | | FIXME: Could we use SmallString here? llvm-svn: 205950
* ARM64: add an explicit cast to silence a silly warningSaleem Abdulrasool2014-04-101-2/+4
| | | | | | | | | | GCC 4.8 complains with: warning: enumeral and non-enumeral type in conditional expression Although this is silly and harmless in this case, add an explicit cast to silence the warning. llvm-svn: 205949
* [ARM64] Fix immediate cost calculation for types larger than i64.Juergen Ributzka2014-04-101-1/+1
| | | | | | | | | | The immediate cost calculation code was hitting an assertion in the included test case, because APInt was still internally 128-bits. Truncating it to 64-bits fixed the issue. Fixes <rdar://problem/16572521>. llvm-svn: 205947
* Revert "For the ARM integrated assembler add checking of the alignments on ↵Reid Kleckner2014-04-103-894/+432
| | | | | | | | | | | | | vld/vst instructions. And report errors for alignments that are not supported." It doesn't build with MSVC 2012, because MSVC doesn't allow union members that have non-trivial default constructors. This change added 'SMLoc AlignmentLoc' to MemoryOp, which made MemoryOp's default ctor non-trivial. This reverts commit r205930. llvm-svn: 205944
* Fix to support properly cleaning up failed address sinking against constantsJim Grosbach2014-04-101-2/+3
| | | | | | | | | | | As it turns out the source of the sunkaddr can be a constant, in which case there is not an instruction to delete, causing the cleanup code introduced in r204833 to crash. This patch adds a dynamic check to ensure the deleted value is in fact an instruction and not a constant. Patch by Louis Gerbarg <lgg@apple.com> llvm-svn: 205941
* Add support for load folding of avx1 logical instructionsJim Grosbach2014-04-091-0/+13
| | | | | | | | | | | | | | | | | | AVX supports logical operations using an operand from memory. Unfortunately because integer operations were not added until AVX2 the AVX1 logical operation's types were preventing the isel from folding the loads. In a limited number of cases the peephole optimizer would fold the loads, but most were missed. This patch adds explicit patterns with appropriate casts in order for these loads to be folded. The included test cases run on reduced examples and disable the peephole optimizer to ensure the folds are being pattern matched. Patch by Louis Gerbarg <lgg@apple.com> rdar://16355124 llvm-svn: 205938
* SelectionDAG: Don't constant fold target-specific nodes.Jim Grosbach2014-04-091-0/+6
| | | | | | | | | | | | | | FoldConstantArithmetic() only knows how to deal with a few target independent ISD opcodes. Bail early if it sees a target-specific ISD node. These node do funny things with operand types which may break the assumptions of the code that follows, and there's no actual folding that can be done anyway. For example, non-constant 256 bit vector shifts on X86 have a shift-amount operand that's a 128-bit v4i32 vector regardless of what the first operand type is and that breaks the assumption that the operand types must match. rdar://16530923 llvm-svn: 205937
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