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* [llvm-mca] Improve debugging (NFC)Evandro Menezes2019-01-082-0/+4
| | | | llvm-svn: 350661
* [llvm-undname] Add support for demangling msvc's noexcept types.Zachary Turner2019-01-082-3/+9
| | | | | | | | | | | Starting in C++17, MSVC introduced a new mangling for function parameters that are themselves noexcept functions. This patch makes llvm-undname properly demangle them. Patch by Zachary Henkel Differential Revision: https://reviews.llvm.org/D55769 llvm-svn: 350656
* Don't write #include "Windows/WindowsSupport.h" from the Windows dir.Zachary Turner2019-01-081-1/+1
| | | | | | | This generates -Wnonportable-include-dir warnings, and doesn't need to be there. It seems this was just checked in on accident. llvm-svn: 350655
* Revert "Revert "Revert "Resubmit rL345008 "Split MachinePipeliner code into ↵Adrian Prantl2019-01-081-5/+595
| | | | | | | | header and cpp files"""" This reverts commit D56084. llvm-svn: 350654
* [NewPM] Port tsanPhilip Pfaffe2019-01-084-41/+60
| | | | | | | | | A straightforward port of tsan to the new PM, following the same path as D55647. Differential Revision: https://reviews.llvm.org/D56433 llvm-svn: 350647
* Rename DIFlagFixedEnum to DIFlagEnumClass. NFCPaul Robinson2019-01-082-3/+3
| | | | llvm-svn: 350641
* [UnrollRuntime] Fix domTree failures in multiexit unrollingAnna Thomas2019-01-081-24/+24
| | | | | | | | | | | | | | | | | | | | Summary: This fixes the IDom for exit blocks and all blocks reachable from the exit blocks, when runtime unrolling under multiexit/exiting case. We initially had a restrictive check that the IDom is only updated when it is the header of the loop. However, we also need to update the IDom to the correct one when the IDom is any block within the original loop. See added test cases (which fail dom tree verification without the patch). Reviewers: reames, mzolotukhin, mkazantsev, hfinkel Reviewed by: brzycki, kuhar Subscribers: zzheng, dmgreen, llvm-commits Differential Revision: https://reviews.llvm.org/D56284 llvm-svn: 350640
* [BPF] Fix .BTF.ext reloc type assigment issueYonghong Song2019-01-081-2/+10
| | | | | | | | | | | | | | | | | | | | Commit f1db33c5c1a9 ("[BPF] Disable relocation for .BTF.ext section") assigned relocation type R_BPF_NONE if the fixup type is FK_Data_4 and the symbol is temporary. The reason is we use FK_Data_4 as a fixup type for insn offsets in .BTF.ext section. Just checking whether the symbol is temporary is not enough. For example, .debug_info may reference some strings whose fixup is FK_Data_4 with a temporary symbol as well. To truely reflect the case for .BTF.ext section, this patch further checks that the section associateed with the symbol must be SHF_ALLOC and SHF_EXECINSTR, i.e., in the text section. This fixed the above-mentioned problem. Signed-off-by: Yonghong Song <yhs@fb.com> llvm-svn: 350637
* [MachineVerifier] Include offending register in allocatable live-in error msg.Florian Hahn2019-01-081-0/+6
| | | | | | | | | | | | | | This patch adds a convenience report() method for physical registers and uses it to print the offending register with the 'MBB has allocatable live-in' error. Reviewers: MatzeB, rtereshin, dsanders Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D55946 llvm-svn: 350630
* [GlobalISel] Fix choice of instruction selector for AArch64 at -O0 with ↵Petr Pavlu2019-01-081-12/+23
| | | | | | | | | | | | | | | | | -global-isel=0 Commit rL347861 introduced an unintentional change in the behaviour when compiling for AArch64 at -O0 with -global-isel=0. Previously, explicitly disabling GlobalISel resulted in using FastISel but an updated condition in the commit changed it to using SelectionDAG. The patch fixes this condition and slightly better organizes the code that chooses the instruction selector. Fixes PR40131. Differential Revision: https://reviews.llvm.org/D56266 llvm-svn: 350626
* [DA][NewPM] Add a printerpass and port the testsuitePhilip Pfaffe2019-01-082-0/+8
| | | | | | | | | The new-pm version of DA is untested. Testing requires a printer, so add that and use it in the existing DA tests. Differential Revision: https://reviews.llvm.org/D56386 llvm-svn: 350624
* [X86][Darwin] Emit compact-unwind for register-sized stack adjustmentsFrancis Visoiu Mistrih2019-01-081-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For stack frames on the size of a register in x86, a code size optimization emits "push rax/eax" instead of "sub" for stack allocation. For example: foo: .cfi_startproc BB#0: pushq %rax Ltmp0: .cfi_def_cfa_offset 16 ... .cfi_endproc However, we are falling back to DWARF in this case because we cannot encode %rax as a saved register. This requirement is wrong, since we don't care about the contents of %rax, it is the equivalent of a sub. In order to specify that we care about the contents of %rax, we would need a .cfi_offset %rax, <offset>. It's also overzealous in the case where there are pushes for callee saved registers followed by a "push rax/eax" instead of "sub", in which case we should also be able to encode the callee saved regs and everything else using compact unwind. Patch authored by Bruno Cardoso Lopes. Differential Revision: https://reviews.llvm.org/D13793 llvm-svn: 350623
* Revert "Revert "Resubmit rL345008 "Split MachinePipeliner code into header ↵Lama Saba2019-01-081-595/+5
| | | | | | | | | | and cpp files""" This reverts commit rL350497 reported remaining issues seem to be unrelated to modules or this change. more info: https://reviews.llvm.org/D56084 llvm-svn: 350621
* AArch64: avoid splitting vector truncating stores.Tim Northover2019-01-081-0/+11
| | | | | | | | | | | | We have code to split vector splats (of zero and non-zero) for performance reasons, but it ignores the fact that a store might be truncating. Actually, truncating stores are formed for vNi8 and vNi16 types. Since the truncation is from a legal type, the size of the store is always <= 64-bits and so they don't actually benefit from being split up anyway, so this patch just disables that transformation. llvm-svn: 350620
* [GlobalISel] Fix unused variable warning in Release builds.Benjamin Kramer2019-01-081-3/+3
| | | | llvm-svn: 350618
* [ARM] Add missing patterns for DSP mulsSam Parker2019-01-082-80/+60
| | | | | | | | | | | Using a PatLeaf for sext_16_node allowed matching smulbb and smlabb instructions once the operands had been sign extended. But we also need to use sext_inreg operands along with sext_16_node to catch a few more cases that enable use to remove the unnecessary sxth. Differential Revision: https://reviews.llvm.org/D55992 llvm-svn: 350613
* AMDGPU/GlobalISel: Introduce vcc reg bankMatt Arsenault2019-01-083-42/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | I'm not entirely sure this is the correct thing to do with the global isel philosophy, but I think this is necessary to handle how differently SGPRs are used normally vs. from a condition. For example, it makes sense to allow a copy from a VGPR to an SGPR, but it makes no sense to allow a copy from VGPRs to SGPRs used as select mask. This avoids regbankselecting strange code with a truncate feeding directly into a condition field. Now a copy is forced from sgpr(s1) to vcc, which is more sensible to handle. Some of these issues could probably avoided with making enough operations resulting in i1 illegal. I think we can't avoid this register bank for legality. For example, an i1 and where one source is from a truncate, and one source is a compare needs some kind of copy inserted to make sure both are in condition registers. llvm-svn: 350611
* [WebAssembly] Massive instruction renamingThomas Lively2019-01-0817-177/+177
| | | | | | | | | | | | | | | Summary: An automated renaming of all the instructions listed at https://github.com/WebAssembly/spec/issues/884#issuecomment-426433329 as well as some similarly-named identifiers. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, eraman, sunfish, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D56338 llvm-svn: 350609
* [LLVM-C] Allow For Creating a BasicBlock without a Parent FunctionRobert Widmann2019-01-081-0/+6
| | | | | | | | | | | | | | Summary: Add a utility function for creating a basic block without a parent function. A useful operation for compilers that need to synthesize and conditionally insert code without having to bother with appending and immediately unlinking a block. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D56279 llvm-svn: 350608
* [LLVM-C] Allow Specifying Signedness in Int CastRobert Widmann2019-01-081-0/+7
| | | | | | | | | | | | | | Summary: Fix an old outstanding problem with the int cast builder binding always assuming the cast is signed by introducing a new LLVMBuildIntCast2 operation and deprecating the old prototype. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D56280 llvm-svn: 350607
* [MC] [AArch64] Support resolving signed fixups for :abs_g0_s: etc.Mandeep Singh Grang2019-01-081-27/+69
| | | | | | | | | | | | | | Summary: This patch is a follow-up to D55896. Reviewers: efriedma, mstorsjo Reviewed By: efriedma Subscribers: javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D56029 llvm-svn: 350606
* [NFC] Remove empty line as a test commit.Chris Kennelly2019-01-081-1/+0
| | | | llvm-svn: 350605
* AMDGPU/GlobalISel: Legalize concat_vectorsMatt Arsenault2019-01-081-0/+12
| | | | llvm-svn: 350598
* Fix typosMatt Arsenault2019-01-081-2/+2
| | | | llvm-svn: 350597
* [WebAssembly] Move CFG-changing passes before RegStackifyHeejin Ahn2019-01-081-8/+6
| | | | | | | | | | | | | | | | | | | Summary: FixIrreducibleControlFlow and LateEHPrepare both possibly modify CFG and create new registers. There seems to be no reason these passes go after register-related optimization passes (PrepareForLiveIntervals, OptimizeLiveIntervals, StoreResults, RegStackify, and RegColoring), and this also possibly create new optimization opportunities. I think we should put all current and future optimization passes before RegStackify (and related passes) unless there's a reason not to. Reviewers: kripken Subscribers: dschuff, sbc100, sunfish, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D56356 llvm-svn: 350596
* RegBankSelect: Fix copy insertion point for terminatorsMatt Arsenault2019-01-083-9/+43
| | | | | | | | | | | | | | | If a copy was needed to handle the condition of brcond, it was being inserted before the defining instruction. Add tests for iterator edge cases. I find the existing code here suspect for the case where it's looking for terminators that modify the register. It's going to insert a copy in the middle of the terminators, which isn't allowed (it might be necessary to have a COPY_terminator if anybody actually needs this). Also legalize brcond for AMDGPU. llvm-svn: 350595
* [WebAssembly] Use 'I' multiclass template for br_table (NFC)Heejin Ahn2019-01-081-22/+12
| | | | | | | | | | | | | | Summary: We don't need to explicitly use `NI` anymore because we now don't use `let` statements within the definitions. Reviewers: aardappel Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D56376 llvm-svn: 350594
* AMDGPU/GlobalISel: Disallow VGPR->SCC copiesMatt Arsenault2019-01-081-2/+8
| | | | | | | This fixes using scalar adds when only the carry in is a VGPR using greedy regbankselect. llvm-svn: 350593
* AMDGPU/GlobalISel: RegBankSelect for carry-inMatt Arsenault2019-01-082-2/+33
| | | | | | | | I'm not sure we should be allowing the truncate to s1 for the inputs. It may be necessary to create a new VCC reg bank. llvm-svn: 350592
* AMDGPU/GlobalISel: RegBankSelect for add/sub with carry outMatt Arsenault2019-01-082-5/+21
| | | | llvm-svn: 350589
* AMDGPU/GlobalISel: InstrMapping for G_UNMERGE_VALUESMatt Arsenault2019-01-081-0/+12
| | | | llvm-svn: 350588
* [RegisterCoalescer] dst register's live interval needs to be updated whenWei Mi2019-01-081-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | merging a src register in ToBeUpdated set. This is to fix PR40061 related with https://reviews.llvm.org/rL339035. In https://reviews.llvm.org/rL339035, live interval of source pseudo register in rematerialized copy may be saved in ToBeUpdated set and its update may be postponed. In PR40061, %t2 = %t1 is rematerialized and %t1 is added into toBeUpdated set to postpone its live interval update. After the rematerialization, the live interval of %t1 is larger than necessary. Then %t1 is merged into %t3 and %t1 gets removed. After the merge, %t3 contains live interval larger than necessary. Because %t3 is not in toBeUpdated set, its live interval is not updated after register coalescing and it will break some assumption in regalloc. The patch requires the live interval of destination register in a merge to be updated if the source register is in ToBeUpdated. Differential revision: https://reviews.llvm.org/D55867 llvm-svn: 350586
* [Verifier] Reject invalid type for DILocalVariable.Davide Italiano2019-01-071-0/+2
| | | | | | | | | | Reviewers: aprantl Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D56414 llvm-svn: 350578
* Recommit r350554 "[X86] Remove AVX512VBMI2 concat and shift intrinsics. ↵Craig Topper2019-01-072-98/+50
| | | | | | | | Replace with target independent funnel shift intrinsics." The MSVC limit we hit on AutoUpgrade.cpp has been worked around for now. llvm-svn: 350567
* [ObjectYAML] [COFF] Support multiple symbols with the same nameMartin Storsjo2019-01-071-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D56294 llvm-svn: 350566
* [X86][AutoUpgrade] Make some tweaks to reduce the number of nested if/else ↵Craig Topper2019-01-071-96/+79
| | | | | | | | | | | | in the intrinsic upgrade code to avoid an MSVC compiler limit. MSVC has a nesting limit of around 110-130. An if/else if/else if counts against this next level. The autoupgrade code consists a long chain of these checking matches against strings. This commit moves some code to a helper function to move out a large if/else chain that was inside of one of the blocks into a separate function. There are more of these we could move or we could change some to lookup tables. I've also merged together a few similar blocks in the outer chain. This should buy us some margin for a little bit. llvm-svn: 350564
* Revert r350554 "[X86] Remove AVX512VBMI2 concat and shift intrinsics. ↵Craig Topper2019-01-072-50/+98
| | | | | | | | Replace with target independent funnel shift intrinsics." The AutoUpgrade.cpp if/else cascade hit an MSVC limit again. llvm-svn: 350562
* [MemorySSA] Add SkipSelfWalker.Alina Sbirlea2019-01-071-1/+49
| | | | | | | | | | | | Summary: Add implementation of SkipSelfWalker. Reviewers: george.burgess.iv Subscribers: sanjoy, jlebar, Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D56285 llvm-svn: 350561
* [TargetLowering][AMDGPU] Remove the SimplifyDemandedBits function that takes ↵Craig Topper2019-01-072-80/+52
| | | | | | | | | | | | | | a User and OpIdx. Stop using it in AMDGPU target for simplifyI24. As we saw in D56057 when we tried to use this function on X86, it's unsafe. It allows the operand node to have multiple users, but doesn't prevent recursing past the first node when it does have multiple users. This can cause other simplifications earlier in the graph without regard to what bits are needed by the other users of the first node. Ideally all we should do to the first node if it has multiple uses is bypass it when its not needed by the user we started from. Doing any other transformation that SimplifyDemandedBits can do like turning ZEXT/SEXT into AEXT would result in an increase in instructions. Fortunately, we already have a function that can do just that, GetDemandedBits. It will only make transformations that involve bypassing a node. This patch changes AMDGPU's simplifyI24, to use a combination of GetDemandedBits to handle the multiple use simplifications. And then uses the regular SimplifyDemandedBits on each operand to handle simplifications allowed when the operand only has a single use. Unfortunately, GetDemandedBits simplifies constants more aggressively than SimplifyDemandedBits. This caused the -7 constant in the changed test to be simplified to remove the upper bits. I had to modify computeKnownBits to account for this by ignoring the upper 8 bits of the input. Differential Revision: https://reviews.llvm.org/D56087 llvm-svn: 350560
* [MemorySSA] Refactor CachingWalker.Alina Sbirlea2019-01-071-49/+95
| | | | | | | | | | | | | | Summary: Refactor caching walker to make creating a walker that skips the starting access strightforward. Reviewers: george.burgess.iv Subscribers: sanjoy, jlebar, Prazek, llvm-commits, jfb Differential Revision: https://reviews.llvm.org/D55957 llvm-svn: 350558
* [X86] Remove AVX512VBMI2 concat and shift intrinsics. Replace with target ↵Craig Topper2019-01-072-98/+50
| | | | | | | | independent funnel shift intrinsics. Differential Revision: https://reviews.llvm.org/D56377 llvm-svn: 350554
* [ARM] ComputeKnownBits to handle extract vectorsDiogo N. Sampaio2019-01-071-0/+27
| | | | | | | | | This patch adds the sign/zero extension done by vgetlane to ARM computeKnownBitsForTargetNode. Differential revision: https://reviews.llvm.org/D56098 llvm-svn: 350553
* [MemorySSA] Extend the clobber walker with the option to skip the starting ↵Alina Sbirlea2019-01-071-8/+19
| | | | | | | | | | | | | | | | | | | access. Summary: The option enables loop transformations to hoist accesses that do not have clobbers in the loop. If the clobber queries skips the starting access, the result may be outside the loop instead of the header Phi. Adding the walker that uses this option in a separate patch. Reviewers: george.burgess.iv Subscribers: sanjoy, jlebar, Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D55944 llvm-svn: 350551
* Revert "[DemandedBits] Use SetVector for Worklist"Nikita Popov2019-01-071-6/+7
| | | | | | | | This reverts commit r350547. Seeing assertion failures on clang tests. llvm-svn: 350549
* [DemandedBits] Use SetVector for WorklistNikita Popov2019-01-071-7/+6
| | | | | | | | | | | | DemandedBits currently uses a simple vector for the worklist, which means that instructions may be inserted multiple times into it. Especially in combination with the deep lattice, this may cause instructions too be recomputed very often. To avoid this, switch to a SetVector. Differential Revision: https://reviews.llvm.org/D56362 llvm-svn: 350547
* AMDGPU: test for uniformity of branch instruction, not its conditionRhys Perry2019-01-072-9/+3
| | | | | | | | | | | | | | | | | Summary: If a divergent branch instruction is marked as divergent by propagation rule 2 in DivergencePropagator::exploreSyncDependency() and its condition is uniform, that branch would incorrectly be assumed to be uniform. Reviewers: arsenm, tstellar Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D56331 llvm-svn: 350532
* [CodeView] More appropriate name and type for a Microsoft precompiled ↵Alexandre Ganea2019-01-071-21/+21
| | | | | | headers parameter. NFC llvm-svn: 350520
* AMDGPU: Remove v16i8 from register classesMatt Arsenault2019-01-071-3/+3
| | | | llvm-svn: 350518
* AMDGPU: Remove VS/SV mappings from selectMatt Arsenault2019-01-071-16/+0
| | | | | | These would violate the constant bus restriction llvm-svn: 350517
* [CallSite removal] Move the rest of IR implementation code away fromChandler Carruth2019-01-074-51/+44
| | | | | | | | | | | | | | `CallSite`. With this change, the remaining `CallSite` usages are just for implementing the wrapper type itself. This does update the C API but leaves the names of that API alone and only updates their implementation. Differential Revision: https://reviews.llvm.org/D56184 llvm-svn: 350509
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