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* [Hexagon] Implement bit-tracking facility with specifics for HexagonKrzysztof Parzyszek2015-07-075-0/+2832
| | | | | | | | This includes code that is intended to be target-independent as well as the Hexagon-specific details. This is just the framework without any users. llvm-svn: 241595
* Common symbols don't have a value.Rafael Espindola2015-07-071-3/+2
| | | | | | | | | | | | | At least not in the interface exposed by ObjectFile. This matches what ELF and COFF implement. Adjust existing code that was expecting them to have values. No overall functionality change intended. Another option would be to change the interface and the ELF and COFF implementations to say that the value of a common symbol is its size. llvm-svn: 241593
* use range-based for loops; NFCISanjay Patel2015-07-071-35/+17
| | | | llvm-svn: 241592
* Common symbols are not undefined, at least for ObjectFile.Rafael Espindola2015-07-071-3/+2
| | | | | | | | | They are implemented like that in some object formats, but for the interface provided by lib/Object, SF_Undefined and SF_Common are different things. This matches the ELF and COFF implementation and fixes llvm-nm for MachO. llvm-svn: 241587
* Simplify, NFC.Rafael Espindola2015-07-071-3/+2
| | | | | | | | In these two contexts we really just want the raw n_value. No need to use getSymbolValue which checks for special cases where, semantically, the symbol has no value. llvm-svn: 241584
* [IR] Make getFirstNonPHI return null if the BB is emptyDavid Majnemer2015-07-071-29/+22
| | | | | | | | | | | | getFirstNonPHI's documentation states that it returns null if there is no non-PHI instruction. However, it instead returns a pointer to the end iterator. The implementation of getFirstNonPHI claims that dereferencing the iterator will result in an assertion failure but this doesn't occur. Instead, machinery like getFirstInsertionPt will attempt to isa<> this invalid memory which results in unpredictable behavior. Instead, make getFirst* return null if no such instruction exists. llvm-svn: 241570
* Fix gcc warnings of different enum and non-enum types in ternariesDenis Protivensky2015-07-072-9/+9
| | | | llvm-svn: 241567
* [ARM] Define a subtarget feature and use it to decide whether long calls shouldAkira Hatanaka2015-07-075-12/+14
| | | | | | | | | | | | | | | | | be emitted. This is needed to enable ARM long calls for LTO and enable and disable it on a per-function basis. Out-of-tree projects currently using EnableARMLongCalls to emit long calls should start passing "+long-calls" to the feature string (see the changes made to clang in r241565). rdar://problem/21529937 Differential Revision: http://reviews.llvm.org/D9364 llvm-svn: 241566
* MIR Parser: Verify the implicit machine register operands.Alex Lorenz2015-07-071-5/+88
| | | | | | | | | | | | This commit verifies that the parsed machine instructions contain the implicit register operands as specified by the MCInstrDesc. Variadic and call instructions aren't verified. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10781 llvm-svn: 241537
* [StackMap Liveness] Calling the base class' getAnalysisUsage method. NFCI.Juergen Ributzka2015-07-071-2/+1
| | | | | | | | Calling into the base class' getAnalysisUsage method after we did our pass specific modifications. This shouldn't really matter since this is the last pass in the pipeline anyways. llvm-svn: 241536
* [StackMap Liveness] No need to cache the MachineFunction. NFC.Juergen Ributzka2015-07-071-22/+20
| | | | | | Don't cache the MachineFunction in the pass and range'ify some loops. llvm-svn: 241535
* [Triple] Add a helper to switch between big/little endian variantsBenjamin Kramer2015-07-061-0/+116
| | | | | | This will be used from clang's driver. llvm-svn: 241527
* [FaultMaps] Add statistic to count the # of implicit null checks.Sanjoy Das2015-07-061-0/+8
| | | | llvm-svn: 241521
* MIR Serialization: Serialize the implicit register flag.Alex Lorenz2015-07-064-21/+54
| | | | | | | | | | | | | | This commit serializes the implicit flag for the register machine operands. It introduces two new keywords into the machine instruction syntax: 'implicit' and 'implicit-def'. The 'implicit' keyword is used for the implicit register operands, and the 'implicit-def' keyword is used for the register operands that have both the implicit and the define flags set. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10709 llvm-svn: 241519
* Remove JumpInstrTableInfo.h as it is no longer used.Eric Christopher2015-07-061-1/+0
| | | | llvm-svn: 241517
* [X86][AVX] Add support for shuffle decoding of vperm2f128/vperm2i128 with ↵Simon Pilgrim2015-07-062-5/+8
| | | | | | | | | | | | zero'd lanes The vperm2f128/vperm2i128 shuffle mask decoding was not attempting to deal with shuffles that give zero lanes. This patch fixes this so that the assembly printer can provide shuffle comments. As this decoder is also used in X86ISelLowering for shuffle combining, I've added an early-out to match existing behaviour. The hope is that we can add zero support in the future, this would allow other ops' decodes (e.g. insertps) to be combined as well. Differential Revision: http://reviews.llvm.org/D10593 llvm-svn: 241516
* [x86] extend machine combiner reassociation optimization to SSE scalar addsSanjay Patel2015-07-061-13/+19
| | | | | | | | | | | | Extend the reassociation optimization of http://reviews.llvm.org/rL240361 (D10460) to SSE scalar FP SP adds in addition to AVX scalar FP SP adds. With the 'switch' in place, we can trivially add other opcodes and test cases in future patches. Differential Revision: http://reviews.llvm.org/D10975 llvm-svn: 241515
* [X86][SSE] Vectorized i64 uniform constant SRA shiftsSimon Pilgrim2015-07-062-2/+51
| | | | | | | | This patch adds vectorization support for uniform constant i64 arithmetic shift right operators. Differential Revision: http://reviews.llvm.org/D9645 llvm-svn: 241514
* WebAssembly: add some TODOJF Bastien2015-07-061-0/+11
| | | | | | | | | | Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D10971 llvm-svn: 241513
* [WinEH] Insert the EH code load before the block terminatorReid Kleckner2015-07-061-1/+1
| | | | | | | The previous code put the load after the terminator, leading to invalid IR and downstream crashes. This caused http://crbug.com/506446. llvm-svn: 241509
* [X86][SSE4A] Shuffle lowering using SSE4A EXTRQ/INSERTQ instructionsSimon Pilgrim2015-07-068-6/+300
| | | | | | | | | | | | This patch adds support for v8i16 and v16i8 shuffle lowering using the immediate versions of the SSE4A EXTRQ and INSERTQ instructions. Although rather limited (they can only act on the lower 64-bits of the source vectors, leave the upper 64-bits of the result vector undefined and don't have VEX encoded variants), the instructions are still useful for the zero extension of any lane (EXTRQ) or inserting a lane into another vector (INSERTQ). Testing demonstrated that it wasn't typically worth it to use these instructions for v2i64 or v4i32 vector shuffles although they are capable of it. As well as adding specific pattern matching for the shuffles, the patch uses EXTRQ for zero extension cases where SSE41 isn't available and its more efficient than the SSE2 'unpack' default approach. It also adds shuffle decode support for the EXTRQ / INSERTQ cases when the instructions are handling full byte-sized extractions / insertions. From this foundation, future patches will be able to make use of the instructions for situations that use their ability to extract/insert at the bit level. Differential Revision: http://reviews.llvm.org/D10146 llvm-svn: 241508
* [X86][SSE] Use the general SMAX/SMIN/UMAX/UMIN opcodes and remove the X86 ↵Simon Pilgrim2015-07-066-138/+177
| | | | | | | | | | | | implementation With the completion of D9746 there is now a common implementation of integer signed/unsigned min/max nodes, removing the need for the equivalent X86 specific implementations. This patch removes the old X86ISD nodes, legalizes the relevant SSE2/SSE41/AVX2/AVX512 instructions for the ISD versions and converts the small amount of existing X86 code. Differential Revision: http://reviews.llvm.org/D10947 llvm-svn: 241506
* [TwoAddressInstructionPass] Rename a variable to match the coding style.Quentin Colombet2015-07-061-4/+4
| | | | | | Spot by Bruno. llvm-svn: 241505
* [llvm-extract] Drop comdats from declarationsReid Kleckner2015-07-061-2/+8
| | | | | | The verifier rejects comdats on declarations. llvm-svn: 241483
* llc: Add a 'run-pass' option.Alex Lorenz2015-07-064-15/+20
| | | | | | | | | | | | | | | This commit adds a 'run-pass' option to llc, which instructs the compiler to run one specific code generation pass only. Llc already has the 'start-after' and the 'stop-after' options, and this new option complements the other two by making it easier to write tests that want to invoke a single pass only. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10776 llvm-svn: 241476
* AMDGPU: Run SIInsertWaits as pre-emit passMatt Arsenault2015-07-061-1/+1
| | | | | | | | | | | Running this after the scheduler enables scheduling waits later so other ALU instructions can run while this would be waiting. When combined with enabling the post-RA scheduler, this gives about a ~20% improvement on sgemm. llvm-svn: 241473
* Change the last few internal StringRef triples into Triple objects.Daniel Sanders2015-07-0615-59/+64
| | | | | | | | | | | | | | | | | | | | Summary: This concludes the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. At this point, the StringRef-form of GNU Triples should only be used in the public API (including IR serialization) and a couple objects that directly interact with the API (most notably the Module class). The next step is to replace these Triple objects with the TargetTuple object that will represent our authoratative/unambiguous internal equivalent to GNU Triples. Reviewers: rengolin Subscribers: llvm-commits, jholewinski, ted, rengolin Differential Revision: http://reviews.llvm.org/D10962 llvm-svn: 241472
* DIBuilder: Don't rauw null pointers with empty arrays in finalize().Adrian Prantl2015-07-061-6/+12
| | | | | | This makes the IR a little easier to read. llvm-svn: 241470
* Where Triple has a suitable predicate, use it rather than the enum values. NFC.Daniel Sanders2015-07-065-9/+7
| | | | | | | | | | Reviewers: mcrosier Subscribers: llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10960 llvm-svn: 241469
* use range-based for loops; NFCISanjay Patel2015-07-061-10/+8
| | | | llvm-svn: 241468
* Resubmit "Add new EliminateAvailableExternally module pass" (r239480)Teresa Johnson2015-07-063-0/+112
| | | | | | | | | | | | | | | | | | | | | | This change includes a fix for https://code.google.com/p/chromium/issues/detail?id=499508#c3, which required updating the visibility for symbols with eliminated definitions. --Original Commit Message-- Add new EliminateAvailableExternally module pass, which is performed in O2 compiles just before GlobalDCE, unless we are preparing for LTO. This pass eliminates available externally globals (turning them into declarations), regardless of whether they are dead/unreferenced, since we are guaranteed to have a copy available elsewhere at link time. This enables additional opportunities for GlobalDCE. If we are preparing for LTO (e.g. a -flto -c compile), the pass is not included as we want to preserve available externally functions for possible link time inlining. The FE indicates whether we are doing an -flto compile via the new PrepareForLTO flag on the PassManagerBuilder. llvm-svn: 241466
* Use an early exit in DIBuilder::finalize() to improve readability.Adrian Prantl2015-07-061-28/+32
| | | | llvm-svn: 241465
* use range-based for loops; NFCISanjay Patel2015-07-061-8/+6
| | | | llvm-svn: 241463
* AMDGPU/SI: Add debugging subtarget feature for DS offsetsMatt Arsenault2015-07-064-1/+18
| | | | | | | | We don't have a good way to detect most situations where DS offsets are usable on SI, so add an option to force using them even if unsafe for debugging performance problems. llvm-svn: 241462
* [Sparc] Add more instruction aliases.James Y Knight2015-07-062-12/+125
| | | | | | | | | These are mostly from the chart in the SparcV8 spec, section "A.3 Synthetic Instructions". Differential Revision: http://reviews.llvm.org/D9834 llvm-svn: 241461
* [Sparc] Add support for flush instruction.James Y Knight2015-07-062-0/+17
| | | | | | Differential Revision: http://reviews.llvm.org/D9833 llvm-svn: 241460
* Remove getRelocationAddress.Rafael Espindola2015-07-069-36/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Originally added in r139314. Back then it didn't actually get the address, it got whatever value the relocation used: address or offset. The values in different object formats are: * MachO: Always an offset. * COFF: Always an address, but when talking about the virtual address of sections it says: "for simplicity, compilers should set this to zero". * ELF: An offset for .o files and and address for .so files. In the case of the .so, the relocation in not linked to any section (sh_info is 0). We can't really compute an offset. Some API mappings would be: * Use getAddress for everything. It would be quite cumbersome. To compute the address elf has to follow sh_info, which can be corrupted and therefore the method has to return an ErrorOr. The address of the section is also the same for every relocation in a section, so we shouldn't have to check the error and fetch the value for every relocation. * Use a getValue and make it up to the user to know what it is getting. * Use a getOffset and: * Assert for dynamic ELF objects. That is a very peculiar case and it is probably fair to ask any tool that wants to support it to use ELF.h. The only tool we have that reads those (llvm-readobj) already does that. The only other use case I can think of is a dynamic linker. * Check that COFF .obj files have sections with zero virtual address spaces. If it turns out that some assembler/compiler produces these, we can change COFFObjectFile::getRelocationOffset to subtract it. Given COFF format, this can be done without the need for ErrorOr. The getRelocationAddress method was never implemented for COFF. It also had exactly one use in a very peculiar case: a shortcut for adding the section value to a pcrel reloc on MachO. Given that, I don't expect that there is any use out there of the C API. If that is not the case, let me know and I will add it back with the implementation inlined and do a proper deprecation. llvm-svn: 241450
* Fix a bug in the A57FPLoadBalancing register tracking/scavenger.Chad Rosier2015-07-061-3/+11
| | | | | | | | | | | | The code in AArch64A57FPLoadBalancing::scavengeRegister() to handle dead defs was not correctly handling aliased registers. E.g. if the dead def was of D2, then S2 was not being marked as unavailable, so it could potentially be used across a live-range in which it would be clobbered. Patch by Geoff Berry <gberry@codeaurora.org>! Phabricator: http://reviews.llvm.org/D10900 llvm-svn: 241449
* Check that COFF .obj files have sections with zero virtual address spaces.Rafael Espindola2015-07-061-0/+2
| | | | | | | | | | | | | When talking about the virtual address of sections the coff spec says: ... for simplicity, compilers should set this to zero. Otherwise, it is an arbitrary value that is subtracted from offsets during relocation. We don't currently subtract it, so check that it is zero. If some producer does create such files, we can change getRelocationOffset instead. llvm-svn: 241447
* [X86][AVX512] Multiply Packed Unsigned Integers with Round and ScaleAsaf Badouh2015-07-065-0/+9
| | | | | | | | | pmulhrsw review: http://reviews.llvm.org/D10948 llvm-svn: 241443
* [Mips] Add support for MCJIT for MIPS32r6Petar Jovanovic2015-07-061-3/+58
| | | | | | | | | | Add support for resolving MIPS32r6 relocations in MCJIT. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D10687 llvm-svn: 241442
* [TableGen] Change a couple methods to return an ArrayRef instead of a const ↵Craig Topper2015-07-063-3/+3
| | | | | | std::vector reference. NFC llvm-svn: 241430
* remove unnecessary temp variable; NFCISanjay Patel2015-07-051-5/+4
| | | | llvm-svn: 241415
* Verifier: Forbid comdats on linker declarations.Peter Collingbourne2015-07-051-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D10945 llvm-svn: 241414
* IR: Do not consider available_externally linkage to be linker-weak.Peter Collingbourne2015-07-0513-67/+46
| | | | | | | | | | | | | | | From the linker's perspective, an available_externally global is equivalent to an external declaration (per isDeclarationForLinker()), so it is incorrect to consider it to be a weak definition. Also clean up some logic in the dead argument elimination pass and clarify its comments to better explain how its behavior depends on linkage, introduce GlobalValue::isStrongDefinitionForLinker() and start using it throughout the optimizers and backend. Differential Revision: http://reviews.llvm.org/D10941 llvm-svn: 241413
* use range-based for loops; NFCISanjay Patel2015-07-051-8/+7
| | | | llvm-svn: 241412
* [TargetLowering] StringRefize asm constraint getters.Benjamin Kramer2015-07-0525-107/+78
| | | | | | | | There is some functional change here because it changes target code from atoi(3) to StringRef::getAsInteger which has error checking. For valid constraints there should be no difference. llvm-svn: 241411
* [x86][AVX512] add Multiply High OpAsaf Badouh2015-07-053-0/+12
| | | | | | | | | include encoding and intrinsics tests. review http://reviews.llvm.org/D10896 llvm-svn: 241406
* [X86] Fix incorrect/inefficient pushw encodings for x86-64 targetsMichael Kuperstein2015-07-052-9/+4
| | | | | | | | | | | | | Correctly support assembling "pushw $imm8" on x86-64 targets. Also some cleanup of the PUSH instructions (PUSH64i16 and PUSHi16 actually represent the same instruction) This fixes PR23996 Patch by: david.l.kreitzer@intel.com Differential Revision: http://reviews.llvm.org/D10878 llvm-svn: 241404
* Add missing builtins to the PPC back end for ABI compliance (vol. 2)Nemanja Ivanovic2015-07-051-0/+6
| | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D10874 Back end portion of the second round of additions to altivec.h. llvm-svn: 241398
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