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* [AArch64] Address Chad's post commit review comments for r217504 (PBQP ↵Arnaud A. de Grandmaison2014-09-101-11/+10
| | | | | | experimental support) llvm-svn: 217518
* typoSanjay Patel2014-09-101-1/+1
| | | | llvm-svn: 217516
* Fix comments of createReplaceableForwardDecl() and createForwardDecl().Frederic Riss2014-09-101-4/+3
| | | | | | | | | | | | | Noticed while trying to understand how the merge of forward decalred types and defintions work. Reviewers: echristo, dblaikie, aprantl Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5291 llvm-svn: 217514
* [AArch64] Pacify lld buildbot complaining about an unused static function in ↵Arnaud A. de Grandmaison2014-09-101-0/+2
| | | | | | release build. llvm-svn: 217505
* [AArch64] Add experimental PBQP supportArnaud A. de Grandmaison2014-09-105-2/+435
| | | | | | | | | | This adds target specific support for using the PBQP register allocator on the AArch64, for the A57 cpu. By default, the PBQP allocator is not used, unless explicitely required on the command line with "-aarch64-pbqp". llvm-svn: 217504
* [AArch 64] Use a constant pool load for weak symbol references whenAsiri Rathnayake2014-09-104-6/+39
| | | | | | | | | | | | | | using static relocation model and small code model. Summary: currently we generate GOT based relocations for weak symbol references regardless of the underlying relocation model. This should be change so that in static relocation model we use a constant pool load instead. Patch from: Keith Walker Reviewers: Renato Golin, Tim Northover llvm-svn: 217503
* Add missing HWEncoding to base register class.Sid Manning2014-09-101-8/+10
| | | | | | | This change gives tblgen the information needed to fill in the HexagonRegEncodingTable. llvm-svn: 217500
* Attempt to pacify buildbots.David Majnemer2014-09-101-11/+0
| | | | llvm-svn: 217499
* ARM: don't size-reduce STMs using the LR register.Tim Northover2014-09-101-1/+1
| | | | | | | | | The only Thumb-1 multi-store capable of using LR is the PUSH instruction, which translates to STMDB, so we shouldn't convert STMIAs. Patch by Sergey Dmitrouk. llvm-svn: 217498
* Object: Add support for bigobjDavid Majnemer2014-09-102-114/+161
| | | | | | | | | | | | | | | | | | | | | | This adds support for reading the "bigobj" variant of COFF produced by cl's /bigobj and mingw's -mbig-obj. The most significant difference that bigobj brings is more than 2**16 sections to COFF. bigobj brings a few interesting differences with it: - It doesn't have a Characteristics field in the file header. - It doesn't have a SizeOfOptionalHeader field in the file header (it's only used in executable files). - Auxiliary symbol records have the same width as a symbol table entry. Since symbol table entries are bigger, so are auxiliary symbol records. Write support will come soon. Differential Revision: http://reviews.llvm.org/D5259 llvm-svn: 217496
* [mips] Remove inverted predicates from MipsSubtarget that were only used by ↵Daniel Sanders2014-09-102-14/+15
| | | | | | | | | | | | | | | | MipsCallingConv.td Summary: No functional change Reviewers: echristo, vmedic Reviewed By: echristo, vmedic Subscribers: echristo, llvm-commits Differential Revision: http://reviews.llvm.org/D5266 llvm-svn: 217494
* [mips] Return an ArrayRef from MipsCC::intArgRegs() and remove ↵Daniel Sanders2014-09-102-24/+19
| | | | | | | | | | | | | | | | MipsCC::numIntArgRegs() Summary: No functional change. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5265 llvm-svn: 217485
* MergeFunctions: FunctionPtr has been renamed to FunctionNode.Stepan Dyatkovskiy2014-09-101-7/+7
| | | | | | | It's supposed to store additional pass information for current function here. That was the reason for name change. llvm-svn: 217483
* [asan-assembly-instrumentation] Added CFI directives to the generated ↵Yuri Gorshenin2014-09-104-1/+67
| | | | | | | | | | | | | | instrumentation code. Summary: [asan-assembly-instrumentation] Added CFI directives to the generated instrumentation code. Reviewers: eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5189 llvm-svn: 217482
* Drop the W postfix on the 16-bit registers.Job Noorman2014-09-107-196/+196
| | | | | | | This ensures the inline assembly register constraints are properly recognised in TargetLowering::getRegForInlineAsmConstraint. llvm-svn: 217479
* [MIPS] Add aliases for sync instruction used by Octeon CPUKai Nacke2014-09-101-0/+6
| | | | | | | | | This commit adds aliases for the sync instruction (synciobdma, syncs, syncw, syncws) which are used by the Octeon CPU. Reviewed by D. Sanders llvm-svn: 217477
* Use cast to MVT instead of EVT on a couple calls to getSizeInBits.Craig Topper2014-09-101-2/+2
| | | | llvm-svn: 217473
* [MCJIT] Remove redundant architecture check from RuntimeDyldMachOI386.Lang Hames2014-09-101-1/+1
| | | | llvm-svn: 217470
* Sink PrevCU updating into DwarfUnit::addRange to ensure consistencyDavid Blaikie2014-09-094-6/+8
| | | | | | | | | So that the two operations in DwarfDebug couldn't get separated (because I accidentally separated them in some work in progress), put them together. While we're here, move DwarfUnit::addRange to DwarfCompileUnit, since it's not relevant to type units. llvm-svn: 217468
* Remove DwarfDebug::PrevSection, PrevCU is sufficient for handling address ↵David Blaikie2014-09-093-15/+3
| | | | | | | | | | | | | range holes. PrevSection/PrevCU are used to detect holes in the address range of a CU to ensure the DW_AT_ranges does not include those holes. When we see a function with no debug info, though it may be in the same range as the prior and subsequent functions, there should be a gap in the CU's ranges. By setting PrevCU to null in that case, the range would not be extended to cover the gap. llvm-svn: 217466
* SampleProfile.cpp: Prune a stray \param added in r217437. [-Wdocumentation]NAKAMURA Takumi2014-09-091-1/+0
| | | | llvm-svn: 217465
* Add a scheduling model for AMD 16H Jaguar (btver2).Sanjay Patel2014-09-093-4/+350
| | | | | | | | | | | | | This is a first pass at a scheduling model for Jaguar. It's structured largely on the existing SandyBridge and SLM sched models. Using this model, in addition to turning on the PostRA scheduler, results in some perf wins on internal and 3rd party benchmarks. There's not much difference in LLVM's test-suite benchmarking subset of tests. Differential Revision: http://reviews.llvm.org/D5229 llvm-svn: 217457
* Merge alignment of common GlobalValue.Rafael Espindola2014-09-091-1/+10
| | | | | | Fixes pr20882. llvm-svn: 217455
* Use armv6k default for FreeBSD/ARMEd Maste2014-09-091-0/+1
| | | | | | Patch by Andrew Turner. llvm-svn: 217454
* When merging two common GlobalValues, keep the largest.Rafael Espindola2014-09-091-2/+17
| | | | llvm-svn: 217451
* Move some logic to ModuleLinker::shouldLinkFromSource. NFC.Rafael Espindola2014-09-091-49/+51
| | | | llvm-svn: 217449
* ScalarOpts/LLVMBuild.txt: Prune unused dependency to IPA.NAKAMURA Takumi2014-09-091-1/+1
| | | | llvm-svn: 217448
* ScalarOpts/LLVMBuild.txt: Reorder.NAKAMURA Takumi2014-09-091-1/+1
| | | | llvm-svn: 217447
* LLVMProfileData: Update LLVMBuild.txt corresponding to r217437.NAKAMURA Takumi2014-09-091-1/+1
| | | | llvm-svn: 217446
* Fix a use of an undefined value (the linkage).Rafael Espindola2014-09-091-0/+3
| | | | llvm-svn: 217445
* Prefer common over weak linkage when linking.Rafael Espindola2014-09-091-2/+3
| | | | | | This matches the behavior of ELF linkers. llvm-svn: 217443
* Simplify ModuleLinker::getLinkageResult. NFC.Rafael Espindola2014-09-091-25/+30
| | | | llvm-svn: 217441
* [mips] Add assembler support for .set mips0 directive.Toma Tabacu2014-09-093-0/+21
| | | | | | | | | | | | | | | | | | Summary: This directive is used to reset the assembler options to their initial values. Assembly programmers use it in conjunction with the ".set mipsX" directives. This patch depends on the .set push/pop directive (http://reviews.llvm.org/D4821). Contains work done by Matheus Almeida. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4957 llvm-svn: 217438
* Re-factor sample profile reader into lib/ProfileData.Diego Novillo2014-09-094-394/+306
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch moves the profile reading logic out of the Sample Profile transformation into a generic profile reader facility in lib/ProfileData. The intent is to use this new reader to implement a sample profile reader/writer that can be used to convert sample profiles from external sources into LLVM. This first patch introduces no functional changes. It moves the profile reading code from lib/Transforms/SampleProfile.cpp into lib/ProfileData/SampleProfReader.cpp. In subsequent patches I will: - Add a bitcode format for sample profiles to allow for more efficient encoding of the profile. - Add a writer for both text and bitcode format profiles. - Add a 'convert' command to llvm-profdata to be able to convert between the two (and serve as entry point for other sample profile formats). Reviewers: bogner, echristo Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5250 llvm-svn: 217437
* [mips] Move MipsTargetLowering::MipsCC::regSize() to ↵Daniel Sanders2014-09-093-32/+32
| | | | | | | | | | | | | | | | | | | | MipsSubtarget::getGPRSizeInBytes() Summary: The GPR size is more a property of the subtarget than that of the ABI so move this information to the MipsSubtarget. No functional change. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5009 llvm-svn: 217436
* [x32] Emit callq for CALLpcrel32Pavel Chupin2014-09-093-4/+19
| | | | | | | | | | | | | | | | | Summary: In AT&T annotation for both x86_64 and x32 calls should be printed as callq in assembly. It's only a matter of correct mnemonic, object output is ok. Test Plan: trivial test added Reviewers: nadav, dschuff, craig.topper Subscribers: llvm-commits, zinovy.nis Differential Revision: http://reviews.llvm.org/D5213 llvm-svn: 217435
* [mips] Don't cache IsO32 and IsFP64 in MipsTargetLowering::MipsCCDaniel Sanders2014-09-092-23/+28
| | | | | | | | | | | | | | | | | Summary: Use a MipsSubtarget reference instead. No functional change. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5008 llvm-svn: 217434
* [mips] Add assembler support for .set push/pop directive.Toma Tabacu2014-09-093-17/+95
| | | | | | | | | | | | | | | Summary: These directives are used to save the current assembler options (in the case of ".set push") and restore the previously saved options (in the case of ".set pop"). Contains work done by Matheus Almeida. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4821 llvm-svn: 217432
* ARM: Negative offset support problemRenato Golin2014-09-091-2/+2
| | | | | | | | This patch is to permit a negative offset usage for a non frame access. Patch by Igor Oblakov. llvm-svn: 217431
* [MachineSinking] Conservatively clear kill flags after coalescing.Patrik Hagglund2014-09-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This solves the problem of having a kill flag inside a loop with a definition of the register prior to the loop: %vreg368<def> ... Inside loop: %vreg520<def> = COPY %vreg368 %vreg568<def,tied1> = add %vreg341<tied0>, %vreg520<kill> => was coalesced into => %vreg568<def,tied1> = add %vreg341<tied0>, %vreg368<kill> MachineVerifier then complained: *** Bad machine code: Virtual register killed in block, but needed live out. *** The kill flag for %vreg368 is incorrect, and is cleared by this patch. This is similar to the clearing done at the end of MachineSinking::SinkInstruction(). Patch provided by Jonas Paulsson. Reviewed by Quentin Colombet and Juergen Ributzka. llvm-svn: 217427
* Set trunc store action to Expand for all X86 targets.Bob Wilson2014-09-091-2/+2
| | | | | | | | When compiling without SSE2, isTruncStoreLegal(F64, F32) would return Legal, whereas with SSE2 it would return Expand. And since the Target doesn't seem to actually handle a truncstore for double -> float, it would just output a store of a full double in the space for a float hence overwriting other bits on the stack. Patch by Luqman Aden! llvm-svn: 217410
* llvm-cov: Try to appease MSVC after r217404Justin Bogner2014-09-081-2/+2
| | | | llvm-svn: 217406
* llvm-cov: Use ErrorOr rather than an error_code* (NFC)Justin Bogner2014-09-081-24/+17
| | | | llvm-svn: 217404
* Fast-ISel: Remove dead code after falling back from selecting call ↵Hans Wennborg2014-09-081-15/+10
| | | | | | | | | | | | | | | | | instructions (PR20863) Previously, fast-isel would not clean up after failing to select a call instruction, because it would have called flushLocalValueMap() which moves the insertion point, making SavedInsertPt in selectInstruction() invalid. Fixing this by making SavedInsertPt a member variable, and having flushLocalValueMap() update it. This removes some redundant code at -O0, and more importantly fixes PR20863. Differential Revision: http://reviews.llvm.org/D5249 llvm-svn: 217401
* Group unsafe fmul math folds together for easier reading. No functional change.Sanjay Patel2014-09-081-6/+10
| | | | llvm-svn: 217399
* Be more careful in parsing Module::ModFlagBehavior valueAlexey Samsonov2014-09-082-17/+27
| | | | | | | | | | to make sure we don't do invalid load of an enum. Share the conversion code between llvm::Module implementation and the verifier. This bug was reported by UBSan. llvm-svn: 217395
* Fix the FIXME that was just added in r217390 - remove a bunch of redundant ↵Sanjay Patel2014-09-081-43/+2
| | | | | | | | fold permutations. The testcases for these folds already exist in test/CodeGen/X86/fp-fast.ll. llvm-svn: 217393
* group unsafe math folds together for easier readingSanjay Patel2014-09-081-150/+142
| | | | | | Also added a FIXME regarding redundant folds for non-canonicalized constants. llvm-svn: 217390
* [AArch64] Enabled AA support for Cortex-A57.Chad Rosier2014-09-081-1/+1
| | | | llvm-svn: 217381
* R600/SI: Fix assertion from copying a TargetGlobalAddressMatt Arsenault2014-09-081-1/+2
| | | | | | | | | | | | | Assert in scheduler from an inserted copy_to_regclass from a constant. This only seems to break sometimes when a constant initializer address is forced into VGPRs in a non-entry block. No test since the only case I've managed to hit only happens with a future patch, and that case will also not be a problem once scalar instructions are used in non-entry blocks. llvm-svn: 217380
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