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* Move RegAllocBase into its own cpp file separate from RABasic.Jakob Stoklund Olesen2012-01-113-312/+336
| | | | | | No functional change. llvm-svn: 147972
* Re-fix the issue Bill fixed in r147899 in a slightly different way, which ↵Eli Friedman2012-01-111-5/+7
| | | | | | doesn't abuse the semantics of linker_private. We don't really want to merge any string constant with a weak_odr global. llvm-svn: 147971
* Fix assert.Eric Christopher2012-01-111-2/+2
| | | | llvm-svn: 147966
* Disable the crash reporter when running lit tests.Argyrios Kyrtzidis2012-01-112-1/+21
| | | | llvm-svn: 147965
* On AVX, we can load v8i32 at a time. The bug happens when two uneven loads ↵Nadav Rotem2012-01-111-5/+23
| | | | | | | | | | are used. When we load the v12i32 type, the GenWidenVectorLoads method generates two loads: v8i32 and v4i32 and attempts to use CONCAT_VECTORS to join them. In this fix I concat undef values to widen the smaller value. The test "widen_load-2.ll" also exposes this bug on AVX. llvm-svn: 147964
* Support segmented stacks on mac.Rafael Espindola2012-01-112-18/+68
| | | | | | | | This uses TLS slot 90, which actually belongs to JavaScriptCore. We only support frames with static size Patch by Brian Anderson. llvm-svn: 147960
* Generate the segmented stack prologue for fastcc too.Rafael Espindola2012-01-111-1/+2
| | | | | | Patch by Brian Anderson. llvm-svn: 147958
* Revert r147945 which disabled an addressing mode transformation. I hadChandler Carruth2012-01-111-4/+0
| | | | | | | | | hoped this would revive one of the llvm-gcc selfhost build bots, but it didn't so it doesn't appear that my transform is the culprit. If anyone else is seeing failures, please let me know! llvm-svn: 147957
* Use unsigned comparison in segmented stack prologue.Rafael Espindola2012-01-111-1/+1
| | | | | | | | This is a comparison of two addresses, and GCC does the comparison unsigned. Patch by Brian Anderson. llvm-svn: 147954
* [asan] extend the workaround for http://llvm.org/bugs/show_bug.cgi?id=11395: ↵Kostya Serebryany2012-01-111-1/+1
| | | | | | don't instrument the function at all on x86_32 if it has a large asm blob llvm-svn: 147953
* Explicitly set the scale to 1 on some segstack prologue instrs.Rafael Espindola2012-01-112-4/+4
| | | | | | Patch by Brian Anderson. llvm-svn: 147952
* The error check for using -g with a .s file already containing dwarf .fileKevin Enderby2012-01-111-4/+4
| | | | | | | directives was in the wrong place and getting triggered incorectly with a cpp .file directive. This change fixes that and adds a test case. llvm-svn: 147951
* Add XOP Intrinsics and testsJan Sjödin2012-01-111-73/+662
| | | | llvm-svn: 147949
* Fix a bug in the lowering of BUILD_VECTOR for AVX. SCALAR_TO_VECTOR does not ↵Nadav Rotem2012-01-111-4/+2
| | | | | | zero untouched elements. Use INSERT_VECTOR_ELT instead. llvm-svn: 147948
* Don't try to create a GEP when the pointee type is unsized (such GEPsDuncan Sands2012-01-111-1/+2
| | | | | | | are invalid). Fixes a crash on array1.C from the GCC testsuite when compiled with dragonegg. llvm-svn: 147946
* Disable the transformation I added in r147936 to see if it fixes someChandler Carruth2012-01-111-0/+4
| | | | | | | | strange build bot failures that look like a miscompile into an infloop. I'll investigate this tomorrow, but I'd both like to know whether my patch is the culprit, and get the bots back to green. llvm-svn: 147945
* Hoist a really redundant code pattern into a helper function, and deleteChandler Carruth2012-01-111-80/+29
| | | | | | lots of lines of code. No functionality changed. llvm-svn: 147942
* Simplify the AND-rooted mask+shift checking code to match that of theChandler Carruth2012-01-111-8/+6
| | | | | | SRL-rooted code. llvm-svn: 147941
* Unify the interface of the three mask+shift transform helpers, andChandler Carruth2012-01-111-26/+34
| | | | | | | factor the differences that were hiding in one of them into its other caller, the SRL handling code. No change in behavior. llvm-svn: 147940
* Clarify and make explicit some of the requirements for transformingChandler Carruth2012-01-111-52/+64
| | | | | | | | | | mask+shift pairs at the beginning of the ISD::AND case block, and then hoist the final pattern into a helper function, simplifying and reflowing it appropriately. This should have no observable behavior change, but several simplifications fell out of this such as directly computing the new mask constant, etc. llvm-svn: 147939
* Fix undefined code and reenable test case.Jakob Stoklund Olesen2012-01-111-2/+2
| | | | | | | I don't think the compact encoding code is right, but at least is has defined behavior now. llvm-svn: 147938
* Hoist the logic to transform shift+mask combinations into sub-registerChandler Carruth2012-01-111-56/+68
| | | | | | | | extracts and scaled addressing modes into its own helper function. No functionality changed here, just hoisting and layout fixes falling out of that hoisting. llvm-svn: 147937
* Teach the X86 instruction selection to do some heroic transforms toChandler Carruth2012-01-112-0/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | detect a pattern which can be implemented with a small 'shl' embedded in the addressing mode scale. This happens in real code as follows: unsigned x = my_accelerator_table[input >> 11]; Here we have some lookup table that we look into using the high bits of 'input'. Each entity in the table is 4-bytes, which means this implicitly gets turned into (once lowered out of a GEP): *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2)); The shift right followed by a shift left is canonicalized to a smaller shift right and masking off the low bits. That hides the shift right which x86 has an addressing mode designed to support. We now detect masks of this form, and produce the longer shift right followed by the proper addressing mode. In addition to saving a (rather large) instruction, this also reduces stalls in Intel chips on benchmarks I've measured. In order for all of this to work, one part of the DAG needs to be canonicalized *still further* than it currently is. This involves removing pointless 'trunc' nodes between a zextload and a zext. Without that, we end up generating spurious masks and hiding the pattern. llvm-svn: 147936
* Improved compile time:Stepan Dyatkovskiy2012-01-111-38/+98
| | | | | | | | | | | | 1. Size heuristics changed. Now we calculate number of unswitching branches only once per loop. 2. Some checks was moved from UnswitchIfProfitable to processCurrentLoop, since it is not changed during processCurrentLoop iteration. It allows decide to skip some loops at an early stage. Extended statistics: - Added total number of instructions analyzed. llvm-svn: 147935
* Clarified the SCEV getSmallConstantTripCount interface with in-your-face ↵Andrew Trick2012-01-111-9/+18
| | | | | | | | comments. This interface is misleading and dangerous, but it is actually what we need for unrolling. llvm-svn: 147926
* Add big endian mips support. Based on a patch by Jack Carter.Rafael Espindola2012-01-113-16/+20
| | | | llvm-svn: 147924
* Add the skeleton of an asm parser for mips.Rafael Espindola2012-01-117-2/+114
| | | | llvm-svn: 147923
* ARM Ld/St Optimizer fix.Andrew Trick2012-01-111-3/+4
| | | | | | | | Allow LDRD to be formed from pairs with different LDR encodings. This was the original intention of the pass. Somewhere along the way, the LDR opcodes were refined which broke the optimization. We really don't care what the original opcodes are as long as they both map to the same LDRD and the immediate still fits. Fixes rdar://10435045 ARMLoadStoreOptimization cannot handle mixed LDRi8/LDRi12 llvm-svn: 147922
* Detect when a value is undefined on an edge to a landing pad.Jakob Stoklund Olesen2012-01-111-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consider this code: int h() { int x; try { x = f(); g(); } catch (...) { return x+1; } return x; } The variable x is undefined on the first edge to the landing pad, but it has the f() return value on the second edge to the landing pad. SplitAnalysis::getLastSplitPoint() would assume that the return value from f() was live into the landing pad when f() throws, which is of course impossible. Detect these cases, and treat them as if the landing pad wasn't there. This allows spill code to be inserted after the function call to f(). <rdar://problem/10664933> llvm-svn: 147912
* Exclusively use SplitAnalysis::getLastSplitPoint().Jakob Stoklund Olesen2012-01-113-25/+14
| | | | | | | | | Delete the alternative implementation in LiveIntervalAnalysis. These functions computed the same thing, but SplitAnalysis caches the result. llvm-svn: 147911
* Avoid CSE of instructions which define physical registers across MBBs unlessEvan Cheng2012-01-111-4/+12
| | | | | | the physical registers are not allocatable. llvm-svn: 147902
* If the global variable is removed by the linker, then don't constant merge itBill Wendling2012-01-111-6/+10
| | | | | | | | | | | | | | with other symbols. An object in the __cfstring section is suppoed to be filled with CFString objects, which have a pointer to ___CFConstantStringClassReference followed by a pointer to a __cstring. If we allow the object in the __cstring section to be merged with another global, then it could end up in any section. Because the linker is going to remove these symbols in the final executable, we shouldn't bother to merge them. <rdar://problem/10564621> llvm-svn: 147899
* Don't avoid recursing for pointer types, just reference types. Expand onEric Christopher2012-01-111-3/+4
| | | | | | | | the comment. Fixes constvars.exp on the gdb test builder. llvm-svn: 147897
* Fixed order of operands in comment to match code.Lang Hames2012-01-101-1/+1
| | | | llvm-svn: 147890
* Default stack alignment for 32bit x86 should be 4 Bytes, not 8 Bytes.Joerg Sonnenberger2012-01-101-1/+1
| | | | | | | Add a test that checks the stack alignment of a simple function for Darwin, Linux and NetBSD for 32bit and 64bit mode. llvm-svn: 147888
* Consider unknown alignment caused by OptimizeThumb2Instructions().Jakob Stoklund Olesen2012-01-101-4/+25
| | | | | | | | | | | | | | | | | | | | This function runs after all constant islands have been placed, and may shrink some instructions to their 2-byte forms. This can actually cause some constant pool entries to move out of range because of growing alignment padding. Treat instructions that may be shrunk the same as inline asm - they erode the known alignment bits. Also reinstate an old assertion in verify(). It is correct now that basic block offsets include alignments. Add a single large test case that will hopefully exercise many parts of the constant island pass. <rdar://problem/10670199> llvm-svn: 147885
* 80 col violation.Evan Cheng2012-01-101-2/+2
| | | | llvm-svn: 147884
* Add missing VEX predicates to VMOVSDto64rr/VMOVSDto64mr. This fixes a fewChad Rosier2012-01-101-2/+3
| | | | | | | failing test cases on our internal AVX nightly tester. rdar://10663637 llvm-svn: 147881
* Let asm parser query asm syntax dialect.Devang Patel2012-01-101-0/+1
| | | | llvm-svn: 147880
* This is the matching change for the data structure name changes for theKevin Enderby2012-01-102-21/+21
| | | | | | | functional change in r147860 to use DW_TAG_label's instead TAG_subprogram's. This only changes names and updates comments. No functional change. llvm-svn: 147877
* ARM updating VST2 pseudo-lowering fixed vs. register update.Jim Grosbach2012-01-103-8/+8
| | | | | | rdar://10663487 llvm-svn: 147876
* Fix some leftover control reaches end of non-void function warnings.Benjamin Kramer2012-01-104-8/+9
| | | | llvm-svn: 147874
* Teach the triple library about the androideabi environment.Chandler Carruth2012-01-101-0/+3
| | | | | | Patch by Evgeniy Stepanov. llvm-svn: 147871
* Move default case for covered enum outside of switch.Richard Smith2012-01-101-1/+1
| | | | llvm-svn: 147870
* For i386, don't use the generic code.Bill Wendling2012-01-101-2/+3
| | | | | | | | | As the comment around 7746 says, it's better to use the x87 extended precision here than SSE. And the generic code doesn't know how to do that. It also regains the speed lost for the uint64_to_float.c testcase. <rdar://problem/10669858> llvm-svn: 147869
* Fix a -Wreturn-type warning in g++.Richard Smith2012-01-101-0/+1
| | | | llvm-svn: 147867
* Cleanup these asserts to follow common LLVM style and codingChandler Carruth2012-01-101-5/+5
| | | | | | | conventions. Also, clarify the grouping of one of the asserts to silence -Wparentheses. llvm-svn: 147863
* Add 'llvm_unreachable' to passify GCC's understanding of the constraintsChandler Carruth2012-01-1011-0/+15
| | | | | | | | of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. llvm-svn: 147861
* Various crash reporting tools have a problem with the dwarf generated forKevin Enderby2012-01-101-17/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | assembly source when it generates the TAG_subprogram dwarf debug info for the labels that have nothing between them as in this bit of assembly source: % cat ZeroLength.s _func1: _func2: nop One solution would be to not emit the subsequent labels with the same address and use the next label with a different address or the end of the section for the AT_high_pc value of the TAG_subprogram. Turns out in llvm-mc it is not possible in all cases to determine of two symbols have the same value at the point we put out the TAG_subprogram dwarf debug info. So we will have llvm-mc instead of putting out TAG_subprogram's put out DW_TAG_label's. And the DW_TAG_label does not have a AT_high_pc value which avoids the problem. This commit is only the functional change to make the diffs clear as to what is really being changed. The next commit will be to clean up the names of such things like MCGenDwarfSubprogramEntry to something like MCGenDwarfLabelEntry. rdar://10666925 llvm-svn: 147860
* Add definition for intel asm variant.Devang Patel2012-01-101-1/+11
| | | | | | Right now, this just adds additional entries in match table. The parser does not use them yet. llvm-svn: 147859
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