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* {DAGCombiner] Fold (rot x, 0) -> xSimon Pilgrim2017-07-051-0/+4
| | | | llvm-svn: 307184
* [PowerPC] Make sure that we remove dead PHI nodes after the PPCCTRLoops pass.Sean Fertile2017-07-051-1/+4
| | | | | | | Commiting on behalf of Stefan Pintilie. Differential Revision: https://reviews.llvm.org/D34829 llvm-svn: 307180
* [DAGCombiner] visitRotate patch to optimize pair of ROTR/ROTL instructions ↵Andrew Zhogin2017-07-051-0/+19
| | | | | | | | | | into one with combined shift operand. For two ROTR operations with shifts C1, C2; combined shift operand will be (C1 + C2) % bitsize. Differential revision: https://reviews.llvm.org/D12833 llvm-svn: 307179
* [Power9] Exploit vector extract with variable index.Tony Jiang2017-07-051-0/+92
| | | | | | | | | | | | | | | | This patch adds the exploitation for new power 9 instructions which extract variable elements from vectors: VEXTUBLX VEXTUBRX VEXTUHLX VEXTUHRX VEXTUWLX VEXTUWRX Differential Revision: https://reviews.llvm.org/D34032 Commit on behalf of Zaara Syeda (syzaara@ca.ibm.com) llvm-svn: 307174
* [Power9] Exploit vector integer extend instructions when indices aren't correct.Tony Jiang2017-07-054-26/+216
| | | | | | | | | | | | | | | This patch adds on to the exploitation added by https://reviews.llvm.org/D33510. This now catches build vector nodes where the inputs are coming from sign extended vector extract elements where the indices used by the vector extract are not correct. We can still use the new hardware instructions by adding a shuffle to move the elements to the correct indices. I introduced a new PPCISD node here because adding a vector_shuffle and changing the elements of the vector_extracts was getting undone by another DAG combine. Commit on behalf of Zaara Syeda (syzaara@ca.ibm.com) Differential Revision: https://reviews.llvm.org/D34009 llvm-svn: 307169
* DebugInfo: Generalize LoadedObjectInfoHelper from RuntimeDyldDavid Blaikie2017-07-053-4/+9
| | | | | | | | Make it usable by any class derived (even indirectly) from LoadedObjectInfo by allowing a custom base class to be specified and perfect forwarding to the ctor. llvm-svn: 307166
* [globalisel][tablegen] Finish fixing compile-time regressions by merging the ↵Daniel Sanders2017-07-051-149/+0
| | | | | | | | | | | | | | | | | | | | | | | matcher and emitter state machines. Summary: Also, made a few minor tweaks to shave off a little more cumulative memory consumption: * All rules share a single NewMIs instead of constructing their own. Only one will end up using it. * Use MIs.resize(1) instead of MIs.clear();MIs.push_back(I) and prevent GIM_RecordInsn from changing MIs[0]. Depends on D33764 Reviewers: rovka, vitalybuka, ab, t.p.northover, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33766 llvm-svn: 307159
* [SLPVectorizer] Add an extra parameter to cancelScheduling function, NFCI.Dinar Temirbulatov2017-07-051-22/+23
| | | | llvm-svn: 307158
* [IndVarSimplify] Add AShr exact flags using induction variables ranges.David Green2017-07-051-2/+34
| | | | | | | | | | This adds exact flags to AShr/LShr flags where we can statically prove it is valid using the range of induction variables. This allows further optimisations to remove extra loads. Differential Revision: https://reviews.llvm.org/D34207 llvm-svn: 307157
* [SystemZ] Simplify handling of 128-bit multiply/divide instructionUlrich Weigand2017-07-057-106/+106
| | | | | | | | | | | Several integer multiply/divide instructions require use of a register pair as input and output. This patch moves setting up the input register pair from C++ code to TableGen, simplifying the whole process and making it more easily extensible. No functional change. llvm-svn: 307155
* [SystemZ] Small cleanups to SystemZScheduleZ13.tdUlrich Weigand2017-07-051-25/+36
| | | | | | | | | | Fixes a couple of whitespace errors, re-sorts the vector floating-point instructions to make them more easily extensible, and adds a missing pseudo instruction. No functional change. llvm-svn: 307154
* [GlobalISel] Refactor Legalizer helpers for libcallsDiana Picus2017-07-052-20/+29
| | | | | | | | | | We used to have a helper that replaced an instruction with a libcall. That turns out to be too aggressive, since sometimes we need to replace the instruction with at least two libcalls. Therefore, change our existing helper to only create the libcall and leave the instruction removal as a separate step. Also rename the helper accordingly. llvm-svn: 307149
* [AsmParser] Mnemonic Spell CorrectorSjoerd Meijer2017-07-051-2/+8
| | | | | | | | | | | | | | | | | | This implements suggesting other mnemonics when an invalid one is specified, for example: $ echo "adXd r1,r2,#3" | llvm-mc -triple arm <stdin>:1:1: error: invalid instruction, did you mean: add, qadd? adXd r1,r2,#3 ^ The implementation is target agnostic, but as a first step I have added it only to the ARM backend; so the ARM backend is a good example if someone wants to enable this too for another target. Differential Revision: https://reviews.llvm.org/D33128 llvm-svn: 307148
* [ARM] GlobalISel: Extract tiny helper. NFCDiana Picus2017-07-051-2/+5
| | | | | | Extract functionality for determining if the target uses AEABI. llvm-svn: 307145
* [MachineIRBuilder] Fix formatting. NFC.Diana Picus2017-07-051-1/+1
| | | | llvm-svn: 307144
* [GlobalISel][X86] For now don't handle not trivial function arguments lowering.Igor Breger2017-07-051-1/+11
| | | | llvm-svn: 307142
* [MachineIRBuilder] Add buildOr helper. NFC.Diana Picus2017-07-051-0/+4
| | | | | | This isn't used anywhere yet, but I need it for a future commit. llvm-svn: 307141
* [GlobalIsel] allow x86_fp80 values to be dumped.Igor Breger2017-07-051-0/+8
| | | | | | | | | | | | | | | | Summary: Otherwise the fallback path fails with an assertion on x86_64 targets, when "x86_fp80" is encountered. Reviewers: t.p.northover, zvi, guyblank Reviewed By: zvi Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34975 llvm-svn: 307140
* [MachineIRBuilder] Add buildBinaryOp helper. NFCDiana Picus2017-07-051-29/+11
| | | | | | | Add a helper for building simple binary ops like add, mul, sub, and. This can be used in the future for quickly adding support for or, xor. llvm-svn: 307139
* [globalisel][tablegen] Fix an unused variable warning in release builds ↵Daniel Sanders2017-07-051-1/+1
| | | | | | after r307133 llvm-svn: 307138
* Revert "[IndVars] Canonicalize comparisons between non-negative values and ↵Max Kazantsev2017-07-051-4/+0
| | | | | | | | | | | indvars" This patch seems to cause failures of test MathExtras.SaturatingMultiply on multiple buildbots. Reverting until the reason of that is clarified. Differential Revision: https://reviews.llvm.org/rL307126 llvm-svn: 307135
* [globalisel][tablegen] Added instruction emission to the state-machine-based ↵Daniel Sanders2017-07-051-0/+153
| | | | | | | | | | | | | | | | | | | | | | | matcher. Summary: This further improves the compile-time regressions that will be caused by a re-commit of r303259. Also added included preliminary work in preparation for the multi-insn emitter since I needed to change the relevant part of the API for this patch anyway. Depends on D33758 Reviewers: rovka, vitalybuka, ab, t.p.northover, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33764 llvm-svn: 307133
* [IndVars] Canonicalize comparisons between non-negative values and indvarsMax Kazantsev2017-07-051-0/+4
| | | | | | | | | | | | | | | | | -If there is a IndVar which is known to be non-negative, and there is a value which is also non-negative, then signed and unsigned comparisons between them produce the same result. Both of those can be seen in the same loop. To allow other optimizations to simplify them, we turn all instructions like %c = icmp slt i32 %iv, %b to %c = icmp ult i32 %iv, %b if both %iv and %b are known to be non-negative. Differential Revision: https://reviews.llvm.org/D34979 llvm-svn: 307126
* [GlobalISel][X86] Allow graceful fallback for struct/array argument/return ↵Igor Breger2017-07-052-11/+26
| | | | | | value lowering. Going to support it in follow patch. llvm-svn: 307125
* [PowerPC] Fix for PR33636Nemanja Ivanovic2017-07-051-2/+4
| | | | | | | | Remove casts to a constant when a node can be an undef. Differential Revision: https://reviews.llvm.org/D34808 llvm-svn: 307120
* [Bash-autocompletion] Show flags which has HelpText or GroupIDYuka Takahashi2017-07-051-1/+1
| | | | | | | | Summary: Otherwise internal flags will be also completed. Differential Revision: https://reviews.llvm.org/D34930 llvm-svn: 307116
* Rewrite areNonVolatileConsecutiveLoads to use BaseIndexOffsetNirav Dave2017-07-052-45/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | Relanding after rewriting undef.ll test to avoid host-dependant endianness. As discussed in D34087, rewrite areNonVolatileConsecutiveLoads using generic checks. Also, propagate missing local handling from there to BaseIndexOffset checks. Tests of note: * test/CodeGen/X86/build-vector* - Improved. * test/CodeGen/BPF/undef.ll - Improved store alignment allows an additional store merge * test/CodeGen/X86/clear_upper_vector_element_bits.ll - This is a case we already do not handle well. Here, the DAG is improved, but scheduling causes a code size degradation. Reviewers: RKSimon, craig.topper, spatel, andreadb, filcab Subscribers: nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D34472 llvm-svn: 307114
* [SafepointIRVerifier] Add verifier pass for finding GC relocation bugsAnna Thomas2017-07-053-0/+360
| | | | | | | | | | | | | | | | | | | | Original Patch and summary by Philip Reames. RewriteStatepointsForGC tries to rewrite a function in a manner where the optimizer can't end up using a pointer value after it might have been relocated by a safepoint. This pass checks the invariant that RSForGC is supposed to establish and that (if we constructed semantics correctly) later passes must preserve. This has been a really useful diagnostic tool when initially developing the rewriting scheme and has found numerous bugs. Differential Revision: https://reviews.llvm.org/D15940 Reviewed by: swaroop.sridhar, mjacob Subscribers: llvm-commits llvm-svn: 307112
* Revert "[AVR] Add the branch selection pass from the GitHub repository"Dylan McKay2017-07-053-269/+0
| | | | | | This reverts commit 602ef067c1d58ecb425d061f35f2bc4c7e92f4f3. llvm-svn: 307111
* [AVR] Add the branch selection pass from the GitHub repositoryDylan McKay2017-07-053-0/+269
| | | | | | | We should rewrite this using the generic branch relaxation pass, but for the moment having this pass is better than hitting an assertion error. llvm-svn: 307109
* [X86][SSE4A] Add support for combining from non-v16i8 EXTRQI/INSERTQI shufflesSimon Pilgrim2017-07-041-3/+3
| | | | | | With the improved shuffle decoding we can now combine EXTRQI/INSERTQI shuffles from non-v16i8 vector types llvm-svn: 307099
* Fix signed/unsigned comparison warningsSimon Pilgrim2017-07-041-4/+4
| | | | llvm-svn: 307098
* [AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev2017-07-041-1/+1
| | | | | | Differential revision: https://reviews.llvm.org/D34407 llvm-svn: 307097
* [LoopDeletion] NFC: Add loop being analyzed debug statementAnna Thomas2017-07-041-0/+2
| | | | llvm-svn: 307096
* [X86][SSE4A] Generalized EXTRQI/INSERTQI shuffle decodesSimon Pilgrim2017-07-044-31/+41
| | | | | | The existing decodes only worked for v16i8 vectors, this adds support for any 128-bit vector llvm-svn: 307095
* fix trivial typos in comments; NFCHiroshi Inoue2017-07-043-3/+3
| | | | llvm-svn: 307094
* [DAGCombiner] Intermediate variables in visitRotate promoted to the ↵Andrew Zhogin2017-07-041-6/+9
| | | | | | function's begin. NFC precommit for D12833. llvm-svn: 307091
* [FastISel][SelectionDAG]Teach fastISel about GC intrinsicsAnna Thomas2017-07-041-1/+5
| | | | | | | | | | | | | | | | | | | | | | | Summary: We are crashing in LLC at O0 when gc intrinsics are present in the block. The reason being FastISel performs basic block ISel by modifying GC.relocates to be the first instruction in the block. This can cause us to visit the GC relocate before it's corresponding GC.statepoint is visited, which is incorrect. When we lower the statepoint, we record the base and derived pointers, along with the gc.relocates. After this we can visit the gc.relocate. This patch avoids fastISel from incorrectly creating the block with gc.relocate as the first instruction. Reviewers: qcolombet, skatkov, qikon, reames Reviewed by: skatkov Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34421 llvm-svn: 307084
* [AMDGPU] Fix latency of MIMG instructionsMarek Olsak2017-07-041-0/+1
| | | | | | Patch by cwabbott (Connor Abbott). llvm-svn: 307081
* [globalisel][tablegen] Partially fix compile-time regressions by converting ↵Daniel Sanders2017-07-044-0/+9
| | | | | | | | | | | | | | | | | | | | | | matcher to state-machine(s) Summary: Replace the matcher if-statements for each rule with a state-machine. This significantly reduces compile time, memory allocations, and cumulative memory allocation when compiling AArch64InstructionSelector.cpp.o after r303259 is recommitted. The following patches will expand on this further to fully fix the regressions. Reviewers: rovka, ab, t.p.northover, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: vitalybuka, aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33758 llvm-svn: 307079
* [LoopDeletion] NFC: Add debug statements to the optimizationAnna Thomas2017-07-041-13/+24
| | | | | | | We have a DEBUG option for loop deletion, but no related debug messages. Added some debug messages to state why loop deletion failed. llvm-svn: 307078
* [InstCombine] Add TODOs for a couple things that should maybe be in ↵Craig Topper2017-07-041-1/+3
| | | | | | InstSimplify instead. NFC llvm-svn: 307065
* [X86] Add comment string for broadcast loads from the constant pool.Craig Topper2017-07-041-37/+156
| | | | | | | | | | | | | | | | | Summary: When broadcasting from the constant pool its useful to print out the final vector similar to what we do for normal moves from the constant pool. I changed only a couple tests that were broadcast focused. One of them had been previously hand tweaked after running the script so that it could check the constant pool declaration. But I think this patch makes that unnecessary now since we can check the comment instead. Reviewers: spatel, RKSimon, zvi Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34923 llvm-svn: 307062
* [X86] Add RDRAND feature to GLM CPUCraig Topper2017-07-041-0/+1
| | | | | | | | | | | | | | Summary: I believe this should be supported on GLM since RDSEED is. Reviewers: m_zuckerman, zvi, RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34828 llvm-svn: 307060
* [Orc] Remove the memory manager argument to addModule, and de-templatize theLang Hames2017-07-042-12/+18
| | | | | | | | | | | | | | | | symbol resolver argument. De-templatizing the symbol resolver is part of the ongoing simplification of ORC layer API. Removing the memory management argument (and delegating construction of memory managers for RTDyldObjectLinkingLayer to a functor passed in to the constructor) allows us to build JITs whose base object layers need not be compatible with RTDyldObjectLinkingLayer's memory mangement scheme. For example, a 'remote object layer' that sends fully relocatable objects directly to the remote does not need a memory management scheme at all (that will be handled by the remote). llvm-svn: 307058
* [AVR] Fix bug which caused assertion errors for some FRMIDX instructionsDylan McKay2017-07-041-3/+8
| | | | | | | | | | | | | Previously, if a basic block ended with a FRMIDX instruction, we would end up doing something like this. *std::next(MBB.end()) Which would hit an error: "Assertion `!NodePtr->isKnownSentinel()' failed." llvm-svn: 307057
* [AVR] Add a missing clobber declaration to LPMWDylan McKay2017-07-041-6/+6
| | | | llvm-svn: 307056
* [DAG] Fixed predicate for determining when two frame indicesNirav Dave2017-07-041-5/+5
| | | | | | addresses are comparable. NFCI. llvm-svn: 307055
* Revert r307026, "[AMDGPU] Switch scalarize global loads ON by default"NAKAMURA Takumi2017-07-041-1/+1
| | | | | | | | | It broke a testcase. Failing Tests (1): LLVM :: CodeGen/AMDGPU/alignbit-pat.ll llvm-svn: 307054
* [legalize-types] Clean up softening machinery.Anton Yartsev2017-07-044-42/+89
| | | | | | | | The patch makes SoftenFloatResult/Operand logic just the same as all other legalization routines have: SoftenFloatResult() now fills the SoftenFloats map and SoftenFloatOperand() perform all needed replacements. This prevents softening mashinery from leaving stale entries in SoftenFloats map (that resulted in errors during the legalize type checking) and clarifies softening. The patch replaces https://reviews.llvm.org/D29265. Differential Revision: https://reviews.llvm.org/D31946 llvm-svn: 307053
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