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* [SelectionDAG] ComputeNumSignBits - add support for SMIN+SMAX clamp patternsSimon Pilgrim2018-02-171-1/+26
| | | | | | | | | | If we have a clamp pattern, SMIN(SMAX(X, LO),HI) or SMAX(SMIN(X, HI),LO) then we can deduce that the number of signbits will be at least the minimum of the LO and HI constants. I haven't bothered with the UMIN/UMAX equivalent as (1) we don't have any current use cases and (2) I wonder if we'd be better off immediately falling back for ComputeKnownBits for UMIN/UMAX which already has optimization patterns useful for unsigned cases. Differential Revision: https://reviews.llvm.org/D43338 llvm-svn: 325450
* [SelectionDAG] SimplifyDemandedVectorElts - add support for VECTOR_INSERT_ELTSimon Pilgrim2018-02-171-0/+34
| | | | | | Differential Revision: https://reviews.llvm.org/D43431 llvm-svn: 325449
* [ThinLTO] Add GraphTraits for FunctionSummariesCharles Saternos2018-02-173-1/+32
| | | | | | | | Add GraphTraits definitions to the FunctionSummary and ModuleSummaryIndex classes. These GraphTraits will be used to construct find SCC's in ThinLTO analysis passes. Second attempt, since last patch caused stage2 build to fail (now using function_ref rather than std::function). llvm-svn: 325448
* [MIPS][MSA] Convert vector integer min/max opcodes to use generic implementationSimon Pilgrim2018-02-174-98/+45
| | | | | | | | | | Found while investigating D43338 Simon^3 - the LLVM project needs more Simons. Differential Revision: https://reviews.llvm.org/D43433 llvm-svn: 325447
* [X86] Add 'sahf' to getHostCPUFeatures so -march=native will pick it up ↵Craig Topper2018-02-171-0/+1
| | | | | | | | | | | | | | | | correctly. Summary: We probably mostly get this right due to family/model/stepping mapping to CPU names. But we should detect it explicitly. Reviewers: RKSimon, echristo, dim, spatel Reviewed By: dim Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43418 llvm-svn: 325439
* [DebugInfo][FastISel] Fix dropping dbg.value()Sander de Smalen2018-02-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: https://llvm.org/PR36263 shows that when compiling at -O0 a dbg.value() instruction (that remains from an original dbg.declare()) is dropped by FastISel. Since FastISel selects instructions by iterating a basic block backwards, it drops the dbg.value if one of its operands is not yet instantiated by a previously selected instruction. Instead of calling 'lookUpRegForValue()' we can call 'getRegForValue()' instead that will insert a placeholder for the operand to be filled in when continuing the instruction selection. Reviewers: aprantl, dblaikie, probinson Reviewed By: aprantl Subscribers: llvm-commits, dstenb, JDevlieghere Differential Revision: https://reviews.llvm.org/D43386 llvm-svn: 325438
* [InstSimplify] move select undef cond fold with other constant cond folds; NFCISanjay Patel2018-02-171-20/+21
| | | | llvm-svn: 325434
* [AArch64] Implement dynamic stack probing for windowsMartin Storsjo2018-02-176-1/+87
| | | | | | | | | This makes sure that alloca() function calls properly probe the stack as needed. Differential Revision: https://reviews.llvm.org/D42356 llvm-svn: 325433
* Fix unused variable warning. NFCI.Simon Pilgrim2018-02-171-3/+2
| | | | | | We were casting to AArch64InstrInfo but only using it for static methods which some compilers complain about. llvm-svn: 325432
* [dwarfdump] Fix spurious verification errors for DW_AT_location attributesJonas Devlieghere2018-02-171-15/+20
| | | | | | | | | | | Verifying any DWARF file that is optimized and contains at least one tag with a DW_AT_location with a location list offset as a DW_AT_form_dataXXX results in dwarfdump spuriously claiming that the location list is invalid. Differential revision: https://reviews.llvm.org/D40199 llvm-svn: 325430
* [DAGCombiner] Remove simplifyShuffleMask - now handled more generally by ↵Simon Pilgrim2018-02-171-35/+0
| | | | | | SimplifyDemandedVectorElts. llvm-svn: 325429
* [DebugInfo] Removed assert on missing CountVarDIESander de Smalen2018-02-171-7/+2
| | | | | | | | | | | | | | | | | | | | Summary: The assert for a DISubrange's CountVarDIE to be available fails when the dbg.value() has been optimized away for any reason. Having the assert for that is a little heavy, so instead removing it now in favor of not generating the 'count' expression. Addresses http://llvm.org/PR36263 . Reviewers: aprantl, dblaikie, probinson Reviewed By: aprantl Subscribers: JDevlieghere, llvm-commits, dstenb Differential Revision: https://reviews.llvm.org/D43387 llvm-svn: 325427
* Report fatal error in the case of out of memorySerge Pavlov2018-02-171-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | This is partial recommit of r325224, reverted in 325227. The relevant part of original comment is below. Analysis of fails in the case of out of memory errors can be tricky on Windows. Such error emerges at the point where memory allocation function fails, but manifests itself when null pointer is used. These two points may be distant from each other. Besides, next runs may not exhibit allocation error. Usual programming practice does not require checking result of 'operator new' because it throws 'std::bad_alloc' in the case of allocation error. However, LLVM is usually built with exceptions turned off, so 'new' can return null pointer. This change installs custom new handler, which causes fatal error in the case of out of memory. The handler is installed automatically prior to call to 'main' during construction of a static object defined in 'lib/Support/ErrorHandling.cpp'. If the application does not use this file, the handler may be installed manually by a call to 'llvm::install_out_of_memory_new_handler', declared in 'include/llvm/Support/ErrorHandling.h". Differential Revision: https://reviews.llvm.org/D43010 llvm-svn: 325426
* [AMDGPU] Return true in enableMultipleCopyHints().Jonas Paulsson2018-02-171-0/+2
| | | | | | | | | | Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Stanislav Mekhanoshin, Tom Stellard. llvm-svn: 325425
* Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Quentin Colombet2018-02-172-210/+1
| | | | | | | | | | | | | | | | | This reverts commit r323991. This commit breaks target that don't model all the register constraints in TableGen. So far the workaround was to set the hasExtraXXXRegAllocReq, but it proves that it doesn't cover all the cases. For instance, when mutating an instruction (like in the lowering of COPYs) the isRenamable flag is not properly updated. The same problem will happen when attaching machine operand from one instruction to another. Geoff Berry is working on a fix in https://reviews.llvm.org/D43042. llvm-svn: 325421
* [DAG, X86] Revert r324797, r324491, and r324359.Chandler Carruth2018-02-172-116/+242
| | | | | | | | | | | | Sadly, r324359 caused at least PR36312. There is a patch out for review but it seems to be taking a bit and we've already had these crashers in tree for too long. We're hitting this PR in real code now and are blocked on shipping new compilers as a consequence so I'm reverting us back to green. Sorry for the churn due to the stacked changes that I had to revert. =/ llvm-svn: 325420
* [X86] Turn selects with constant condition into vector shuffles during DAG ↵Craig Topper2018-02-171-0/+17
| | | | | | | | | | | | | | | | | | | | | | | combine Summary: Currently we convert to shuffles during lowering. This moves it to DAG combine so hopefully we can get it done before type legalization has to extend the condition. I believe in some cases we're creating SHRUNKBLENDs that end up with constant conditions because we see the extended on the condition and think its a dynamic selelect before DAG combine gets a chance to constant fold the extend. We could add combines to turn SHRUNKBLENDs with constant condition back to vselect. But it seemed like it might be better to just send them to shuffles as early as possible so they never get a chance to become SHRUNKBLENDs. This the reason some tests went from blends controlled by a constant pool load to just move. Some of the constant pool entries changed because the sign_extend introduced by type legalization turned undef elements in select condition into 0s. While the select->shuffle used -1 in the shuffle mask. So now the shuffle lowering can do what it wants with them. I'll remove the lowering code as a follow up. We might be able to simplify some of the pre-checks for SHRUNKBLEND as the FIXME there says. Reviewers: spatel, RKSimon, efriedma, zvi, andreadb Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43367 llvm-svn: 325417
* [ThinLTO] Allow indexing to request backend to ignore the moduleVitaly Buka2018-02-162-5/+11
| | | | | | | | | | | | | | | | | | Summary: Gold plugin does not add pass to ThinLTO modules without useful symbols. In this case ThinLTO can't create corresponding index file and some features, like CFI, cannot be processes by backed correctly without index. Given that we don't need the backed output we can request it to avoid processing the module. This is implemented by this patch using new "SkipModuleByDistributedBackend" flag. Reviewers: pcc, tejohnson Subscribers: mehdi_amini, inglorion, eraman, cfe-commits Differential Revision: https://reviews.llvm.org/D42995 llvm-svn: 325411
* AMDGPU: Remove unused private member of AMDGPUTargetELFStreamerKonstantin Zhuravlyov2018-02-162-2/+1
| | | | llvm-svn: 325408
* Remove an unused function.Eric Christopher2018-02-161-4/+0
| | | | llvm-svn: 325403
* AMDGPU: Bring elf flags in sync with the specKonstantin Zhuravlyov2018-02-166-31/+116
| | | | | | | | | | | - Add MACH flags - Add XNACK flag - Add reserved flags - Minor cleanups in docs Differential Revision: https://reviews.llvm.org/D43356 llvm-svn: 325399
* [Constant] add floating-point helpers for normal/finite-nz; NFCSanjay Patel2018-02-162-42/+39
| | | | | | | | | ...and delete the equivalent local functiona from InstCombine. These might be useful to other InstCombine files or other passes and makes FP queries more similar to integer constant queries. llvm-svn: 325398
* [X86] In lowerVSELECTtoVectorShuffle, don't map undef select condition to ↵Craig Topper2018-02-161-3/+6
| | | | | | | | | | undef in shuffle mask. Undef in select condition means we should pick the element from one side or the other. An undef in a shuffle mask means pick any element from either source or worse. I suspect by the time we get here most of the undefs in a constant vector have been removed by other things, but doing this for safety. llvm-svn: 325394
* AMDGPU: Bring processors and features in sync with the specKonstantin Zhuravlyov2018-02-164-18/+6
| | | | | | | | | | - Remove gfx800 - Make iceland gfx802 - Add xnack to gfx902 Differential Revision: https://reviews.llvm.org/D43355 llvm-svn: 325393
* Fix emission of PDB string table.Zachary Turner2018-02-164-171/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was originally reported as a bug with the symptom being "cvdump crashes when printing an LLD-linked PDB that has an S_FILESTATIC record in it". After some additional investigation, I determined that this was a symptom of a larger problem, and in fact the real problem was in the way we emitted the global PDB string table. As evidence of this, you can take any lld-generated PDB, run cvdump -stringtable on it, and it would return no results. My hypothesis was that cvdump could not *find* the string table to begin with. Normally it would do this by looking in the "named stream map", finding the string /names, and using its value as the stream index. If this lookup fails, then cvdump would fail to load the string table. To test this hypothesis, I looked at the name stream map generated by a link.exe PDB, and I emitted exactly those bytes into an LLD-generated PDB. Suddenly, cvdump could read our string table! This code has always been hacky and we knew there was something we didn't understand. After all, there were some comments to the effect of "we have to emit strings in a specific order, otherwise things don't work". The key to fixing this was finally understanding this. The way it works is that it makes use of a generic serializable hash map that maps integers to other integers. In this case, the "key" is the offset into a buffer, and the value is the stream number. If you index into the buffer at the offset specified by a given key, you find the name. The underlying cause of all these problems is that we were using the identity function for the hash. i.e. if a string's offset in the buffer was 12, the hash value was 12. Instead, we need to hash the string *at that offset*. There is an additional catch, in that we have to compute the hash as a uint32 and then truncate it to uint16. Making this work is a little bit annoying, because we use the same hash table in other places as well, and normally just using the identity function for the hash function is actually what's desired. I'm not totally happy with the template goo I came up with, but it works in any case. The reason we never found this bug through our own testing is because we were building a /parallel/ hash table (in the form of an llvm::StringMap<>) and doing all of our lookups and "real" hash table work against that. I deleted all of that code and now everything goes through the real hash table. Then, to test it, I added a unit test which adds 7 strings and queries the associated values. I test every possible insertion order permutation of these 7 strings, to verify that it really does work as expected. Differential Revision: https://reviews.llvm.org/D43326 llvm-svn: 325386
* Remove useless comment - seems to be a copy+paste typo. NFCISimon Pilgrim2018-02-161-1/+0
| | | | llvm-svn: 325385
* [AArch64] Fix BITCAST lowering crashEvandro Menezes2018-02-161-1/+2
| | | | | | | | | | | The data type is assumed to be a vector, but sometimes it is not, leading to an assertion. Add simple test-case to verify this. Differential revision: https://reviews.llvm.org/D42599 llvm-svn: 325378
* AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elementsChangpeng Fang2018-02-161-1/+12
| | | | | | | | | | | | | | Summary: This patch extends the promotion of alloca to vector to the arrays of up to 16 elements. Also we introduce an option, -disable-promote-alloca-to-vector, to switch promotion to vector off, if needed. Reviewers: arsenm Differential Revision: https://reviews.llvm.org/D33559 llvm-svn: 325372
* [X86] Only reorder srl/and on last DAG combiner runCraig Topper2018-02-161-2/+8
| | | | | | | | | | This seems to interfere with a target independent brcond combine that looks for the (srl (and X, C1), C2) pattern to enable TEST instructions. Once we flip, that combine doesn't fire and we end up exposing it to the X86 specific BT combine which causes us to emit a BT instruction. BT has lower throughput than TEST. We could try to make the brcond combine aware of the alternate pattern, but since the flip was just a code size reduction and not likely to enable other combines, it seemed easier to just delay it until after lowering. Differential Revision: https://reviews.llvm.org/D43201 llvm-svn: 325371
* [X86] Remove call to ShrinkDemandedCosntant from the SHRUNKBLEND creation code.Craig Topper2018-02-161-2/+1
| | | | | | We only run this code if know the condition isn't a constant vector. ShrinkDemandedConstant isn't going to find any different. llvm-svn: 325368
* [WebAssembly] MC: Make explicit our current lack of support for relocations ↵Sam Clegg2018-02-162-6/+19
| | | | | | | | | | | | against unnamed temporary symbols. Add an explicit check before looking up symbol in SymbolIndices. This was previously silently succeeding and returning zero for such unnamed temporaries. Differential Revision: https://reviews.llvm.org/D43365 llvm-svn: 325367
* [InstCombine] clean up fdiv-with-fdiv folds; NFCISanjay Patel2018-02-161-28/+23
| | | | llvm-svn: 325366
* Fix signed/unsigned comparison warning. NFCI.Simon Pilgrim2018-02-161-1/+1
| | | | llvm-svn: 325363
* Fix signed/unsigned comparison warning. NFCI.Simon Pilgrim2018-02-161-3/+3
| | | | llvm-svn: 325359
* [InstCombine] remove redundant debug info setting; NFCSanjay Patel2018-02-161-2/+0
| | | | | | The IRBuilder sets debuginfo in Insert(), so this was duplicating what already happened. llvm-svn: 325358
* [JumpThreading] PR36133 enable/disable DominatorTree for LVI analysisBrian M. Rzycki2018-02-163-1/+69
| | | | | | | | | | | | | | | | | | | | | | Summary: The LazyValueInfo pass caches a copy of the DominatorTree when available. Whenever there are pending DominatorTree updates within JumpThreading's DeferredDominance object we cannot use the cached DT for LVI analysis. This commit adds the new methods enableDT() and disableDT() to LVI. JumpThreading also sets the appropriate usage model before calling LVI analysis methods. Fixes https://bugs.llvm.org/show_bug.cgi?id=36133 Reviewers: sebpop, dberlin, kuhar Reviewed by: sebpop, kuhar Subscribers: uabelho, llvm-commits, aprantl, hiraditya, a.elovikov Differential Revision: https://reviews.llvm.org/D42717 llvm-svn: 325356
* AMDGPU/SI: Turn off GPR Indexing Mode immediately after the interested ↵Changpeng Fang2018-02-161-38/+23
| | | | | | | | | | | | | | | | | | instruction. Summary: In the current implementation of GPR Indexing Mode when the index is of non-uniform, the s_set_gpr_idx_off instruction is incorrectly inserted after the loop. This will lead the instructions with vgpr operands (v_readfirstlane for example) to read incorrect vgpr. In this patch, we fix the issue by inserting s_set_gpr_idx_on/off immediately around the interested instruction. Reviewers: rampitec Differential Revision: https://reviews.llvm.org/D43297 llvm-svn: 325355
* [SelectionDAG] Enable SimplifyDemandedVectorElts support for simplifying ↵Simon Pilgrim2018-02-161-0/+25
| | | | | | | | | | shuffle masks Based off the DemandedElts mask the and UNDEF elements returned from the SimplifyDemandedVectorElts calls to the shuffle operands, we can attempt to simplify the shuffle mask. I had to be very conservative here as accepting post-legalized shuffle masks could cause problems for targets that legalize UNDEF mask elements back to inrange values (PowerPC), similarly combining to identity shuffle masks could cause too much UNDEF information to disappear for later combines. llvm-svn: 325354
* [InstCombine] reduce code duplication; NFCSanjay Patel2018-02-161-31/+19
| | | | llvm-svn: 325353
* [X86][SSE] Allow float domain crossing if we are merging 2 or more shuffles ↵Simon Pilgrim2018-02-161-0/+1
| | | | | | and the root started as a float domain shuffle llvm-svn: 325349
* [PowerPC] Fix transform in table gen file causing UBNemanja Ivanovic2018-02-161-1/+1
| | | | | | | | Running a bootstrap build with UBSan produces a number of instances where we have signed integer overflow due to this transform. Change the type to long to prevent this UB on 64-bit build machines. llvm-svn: 325347
* [mips] Remove codegen support from some 16 bit instructionsSimon Dardis2018-02-161-12/+5
| | | | | | | | | | | | These instructions conflict with their full length variants for the purposes of FastISel as they cannot be distingushed based on the number and type of operands and predicates. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D41285 llvm-svn: 325341
* [SelectionDAG] Add initial SimplifyDemandedVectorElts support for ↵Simon Pilgrim2018-02-161-0/+20
| | | | | | | | simplifying VSELECT operands This just adds a basic pass through - we can add constant selection mask handling in a future patch to fully match InstCombine. llvm-svn: 325338
* [Transforms] Propagate TBAA info in SROAIvan A. Kosarev2018-02-161-22/+61
| | | | | | | | | | | | | | | Now that we have the new TBAA metadata format that is capable of representing accesses to aggregates, we can propagate TBAA access tags from memory setting and transferring intrinsics to load and store instructions and vice versa. Since SROA produces lots of new loads and stores on optimized builds, this change significantly decreases the share of undecorated memory accesses on such builds. Differential Revision: https://reviews.llvm.org/D41563 llvm-svn: 325329
* [ARM] Return true in enableMultipleCopyHints().Jonas Paulsson2018-02-161-0/+1
| | | | | | | | | | Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Eli Friedman llvm-svn: 325327
* [LegalizeDAG] Fix legalization of SETCCMikhail Maltsev2018-02-161-1/+1
| | | | | | | | | | | | | | | | | | | Summary: Currently when expanding a SETCC node into a SELECT_CC, LLVM uses an incorrect type for determining BooleanContent of the result. This patch fixes the issue. Fixes PR36079. Reviewers: rogfer01, javed.absar, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43282 llvm-svn: 325325
* [ARM] Materialise some boolean values to avoid a branchRoger Ferrer Ibanez2018-02-161-10/+89
| | | | | | | | | | | | | This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
* [ThinLTO] Import global variablesEugene Leviant2018-02-162-20/+88
| | | | | | Differential revision: https://reviews.llvm.org/D43077 llvm-svn: 325320
* [X86] Allow CMOVs of constants to be sign extended from i32.Craig Topper2018-02-161-4/+5
| | | | | | Sign extending i32 constants only requires a REX prefix as does widening the CMOV. This is cheaper than the explicit sign extend op. llvm-svn: 325318
* [X86] Don't zero_extend cmov up to i64, stop at i32.Craig Topper2018-02-161-11/+26
| | | | | | Zero extend from i32 to i64 is free. So extend from i16 to i32, and then use a free zero extend to finish. llvm-svn: 325317
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