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* [AMDGPU] gfx1010 sgpr register changesStanislav Mekhanoshin2019-04-2410-41/+123
| | | | | | Differential Revision: https://reviews.llvm.org/D61045 llvm-svn: 359117
* [LLVM-C] Deprecate the LLVMValueRef-returning metadata creation functionsRobert Widmann2019-04-241-0/+10
| | | | | | | | | | | | | | | | Summary: There is still some value in using these functions while the remaining LLVMValueRef-based accessors are still around, but LLVMMDNodeInContext in particular has some wonky semantics that make it worth replacing outright. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60524 llvm-svn: 359114
* [AMDGPU] Add gfx1010 target definitionsStanislav Mekhanoshin2019-04-2416-112/+537
| | | | | | Differential Revision: https://reviews.llvm.org/D61041 llvm-svn: 359113
* [InstCombine][X86] Use generic expansion of PACKSS/PACKUS for constant ↵Simon Pilgrim2019-04-241-51/+45
| | | | | | | | | | folding. NFCI. This patch rewrites the existing PACKSS/PACKUS constant folding code to expand as a generic expansion. This is a first NFCI step toward expanding PACKSS/PACKUS intrinsics which are acting as non-saturating truncations (although technically the expansion could be used in all cases - but we'll probably want to be conservative). llvm-svn: 359111
* llvm-undname: Fix assert-on->4GiB-string-literal, found by oss-fuzzNico Weber2019-04-241-1/+4
| | | | llvm-svn: 359109
* [JITLink] Refer to FDE's CIE (not the most recent CIE) when parsing eh-frame.Lang Hames2019-04-242-13/+27
| | | | | | | | | | | | | | | Frame Descriptor Entries (FDEs) have a pointer back to a Common Information Entry (CIE) that describes how the rest FDE should be parsed. JITLink had been assuming that FDEs always referred to the most recent CIE encountered, but the spec allows them to point back to any previously encountered CIE. This patch fixes JITLink to look up the correct CIE for the FDE. The testcase is a MachO binary with an FDE that refers to a CIE that is not the one immediately proceeding it (the layout can be viewed wit 'dwarfdump --eh-frame <testcase>'. This test case had to be a binary as llvm-mc now sorts FDEs (as of r356216) to ensure FDEs *do* point to the most recent CIE. llvm-svn: 359105
* [AMDGPU][MC] Parser cleanup and refactoringDmitry Preobrazhensky2019-04-241-93/+48
| | | | | | | | Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D60767 llvm-svn: 359096
* [x86] make sure horizontal op and broadcast types match to simplify (PR41414)Sanjay Patel2019-04-241-2/+6
| | | | | | | | | If the types don't match, we can't just remove the shuffle. There may be some other opportunity for optimization here, but this should prevent the crashing seen in: https://bugs.llvm.org/show_bug.cgi?id=41414 llvm-svn: 359095
* [LLVM-C] Use dyn_cast instead of unwrap in LLVMGetDebugLoc functionswhitequark2019-04-241-15/+21
| | | | | | | | | | | | | | | | | | | | | Summary: The `unwrap<Type>` calls can assert with: ``` Assertion failed: (isa<X>(Val) && "cast<Ty>() argument of incompatible type!"), function cast ``` so replace them with `dyn_cast`. Reviewers: whitequark, abdulras, hiraditya, compnerd Reviewed By: whitequark Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60473 llvm-svn: 359093
* [X86] Add shouldFoldConstantShiftPairToMask override placeholder. NFCI.Simon Pilgrim2019-04-242-0/+9
| | | | | | Prep work toward fixing PR40758 llvm-svn: 359088
* Let llvm-cvtres (and lld-link) report duplicate resourcesNico Weber2019-04-241-23/+63
| | | | | | | | | | | | | | | | | If two .res files contain the same resource, cvtres.exe (and hence link.exe) reject the input with this message: CVTRES : fatal error CVT1100: duplicate resource. type:STRING, name:101, language:0x0409 LINK : fatal error LNK1123: failure during conversion to COFF: file invalid or corrupt llvm-cvtres (and lld-link) used to silently pick one of the duplicate resources instead. This patch makes them report an error as well. We slightly improve on cvtres by printing the name of two .res files containing duplicate entries as well. Differential Revision: https://reviews.llvm.org/D61049 llvm-svn: 359083
* Add "const" in GetUnderlyingObjects. NFCBjorn Pettersson2019-04-2412-53/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Both the input Value pointer and the returned Value pointers in GetUnderlyingObjects are now declared as const. It turned out that all current (in-tree) uses of GetUnderlyingObjects were trivial to update, being satisfied with have those Value pointers declared as const. Actually, in the past several of the users had to use const_cast, just because of ValueTracking not providing a version of GetUnderlyingObjects with "const" Value pointers. With this patch we get rid of those const casts. Reviewers: hfinkel, materi, jkorous Reviewed By: jkorous Subscribers: dexonsmith, jkorous, jholewinski, sdardis, eraman, hiraditya, jrtc27, atanasyan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61038 llvm-svn: 359072
* [Mips][CodeGen] Remove MachineFunction::setSubtarget. Change Mips to just ↵Craig Topper2019-04-242-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | copy the subtarget from the MachineFunction instead of recalculating it. Summary: The MachineFunction should have been created with the correct subtarget. As long as there is no way to change it, MipsTargetMachine can just capture it directly from the MachineFunction without calling getSubtargetImpl again. While there, const correct the Subtarget pointer to avoid a const_cast. I believe the Mips16Subtarget and NoMips16Subtarget members are never used, but I'll leave there removal for a separate patch. Reviewers: echristo, atanasyan Reviewed By: atanasyan Subscribers: sdardis, arichardson, hiraditya, jrtc27, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60936 llvm-svn: 359071
* [CommandLine] Provide parser<unsigned long> instantiation to allow ↵Fangrui Song2019-04-245-28/+37
| | | | | | | | | | | | | cl::opt<uint64_t> on LP64 platforms Summary: And migrate opt<unsigned long long> to opt<uint64_t> Fixes PR19665 Differential Revision: https://reviews.llvm.org/D60933 llvm-svn: 359068
* Revert [AliasAnalysis] AAResults preserves AAManager.Alina Sbirlea2019-04-241-4/+6
| | | | | | Triggers use-after-free. llvm-svn: 359055
* [Remarks] Add string deduplication using a string tableFrancis Visoiu Mistrih2019-04-2410-20/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add support for uniquing strings in the remark streamer and emitting the string table in the remarks section. * Add parsing support for the string table in the RemarkParser. From this remark: ``` --- !Missed Pass: inline Name: NoDefinition DebugLoc: { File: 'test-suite/SingleSource/UnitTests/2002-04-17-PrintfChar.c', Line: 7, Column: 3 } Function: printArgsNoRet Args: - Callee: printf - String: ' will not be inlined into ' - Caller: printArgsNoRet DebugLoc: { File: 'test-suite/SingleSource/UnitTests/2002-04-17-PrintfChar.c', Line: 6, Column: 0 } - String: ' because its definition is unavailable' ... ``` to: ``` --- !Missed Pass: 0 Name: 1 DebugLoc: { File: 3, Line: 7, Column: 3 } Function: 2 Args: - Callee: 4 - String: 5 - Caller: 2 DebugLoc: { File: 3, Line: 6, Column: 0 } - String: 6 ... ``` And the string table in the .remarks/__remarks section containing: ``` inline\0NoDefinition\0printArgsNoRet\0 test-suite/SingleSource/UnitTests/2002-04-17-PrintfChar.c\0printf\0 will not be inlined into \0 because its definition is unavailable\0 ``` This is mostly supposed to be used for testing purposes, but it gives us a 2x reduction in the remark size, and is an incremental change for the updates to the remarks file format. Differential Revision: https://reviews.llvm.org/D60227 llvm-svn: 359050
* [Lint] Permit aliasing noalias readonly argumentsJosh Stone2019-04-231-2/+6
| | | | | | | | | | | | | | | | | | Summary: If two arguments are both readonly, then they have no memory dependency that would violate noalias, even if they do actually overlap. Reviewers: hfinkel, efriedma Reviewed By: efriedma Subscribers: efriedma, hiraditya, llvm-commits, tstellar Tags: #llvm Differential Revision: https://reviews.llvm.org/D60239 llvm-svn: 359047
* [AArch64][GlobalISel] Select G_INTRINSIC_ROUNDJessica Paquette2019-04-231-0/+58
| | | | | | | Add selection support for G_INTRINSIC_ROUND, add a selection test, and add check lines to arm64-vfloatintrinsics.ll and f16-instructions.ll. llvm-svn: 359046
* [AArch64][GlobalISel] Mark G_INTRINSIC_ROUND as a pre-isel floating point opcodeJessica Paquette2019-04-231-0/+1
| | | | | | | | | Add G_INTRINSIC_ROUND to isPreISelGenericFloatingPointOpcode to ensure that its input and output are assigned the correct register bank. Add a regbankselect test to verify that we get what we expect here. llvm-svn: 359044
* The error message for mismatched value sites is very cryptic.Dmitry Mikulin2019-04-232-3/+11
| | | | | | | | Make it more readable for an average user. Differential Revision: https://reviews.llvm.org/D60896 llvm-svn: 359043
* [CGP] Look through bitcasts when duplicating returns for tail callsFrancis Visoiu Mistrih2019-04-231-1/+3
| | | | | | | | | | | | | | | | | | | | | The simple case of: ``` int *callee(); void *caller(void *a) { if (a == NULL) return callee(); return a; } ``` would generate a regular call instead of a tail call because we don't look through the bitcast of the call to `callee` when duplicating the return blocks. Differential Revision: https://reviews.llvm.org/D60837 llvm-svn: 359041
* [WebAssembly] Emit br_table for most switch instructionsHeejin Ahn2019-04-231-0/+5
| | | | | | | | | | | | | | | | | | Summary: Always convert switches to br_tables unless there is only one case, which is equivalent to a simple branch. This reduces code size for wasm, and we defer possible jump table optimizations to the VM. Addresses PR41502. Reviewers: kripken, sunfish Subscribers: dschuff, sbc100, jgravelle-google, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60966 llvm-svn: 359038
* Revert "[MS] Emit S_HEAPALLOCSITE debug info" because of ToTWin64(db)Amy Huang2019-04-234-36/+0
| | | | | | | | | buildbot failure. This reverts commit d07d6d617713bececf57f3547434dd52f0f13f9e and c774f687b6880484a126ed3e3d737e74c926f0ae. llvm-svn: 359034
* [AArch64][GlobalISel] Legalize G_INTRINSIC_ROUNDJessica Paquette2019-04-232-2/+3
| | | | | | | Add it to the same rule as G_FCEIL etc. Add a legalizer test, and add a missing switch case to AArch64LegalizerInfo.cpp. llvm-svn: 359033
* [MemorySSA] LCSSA preserves MemorySSA.Alina Sbirlea2019-04-233-6/+9
| | | | | | | | | | | | | | | | | | | | | Summary: Enabling MemorySSA in the old pass manager leads to MemorySSA being run twice due to the fact that LCSSA and LoopSimplify do not preserve MemorySSA. This is the first step to address that: target LCSSA. LCSSA does not make any changes that invalidate MemorySSA, so it preserves it by design. It must preserve AA as well, for this to hold. After this patch, MemorySSA is still run twice in the old pass manager. Step two follows: target LoopSimplify. Subscribers: mehdi_amini, jlebar, Prazek, llvm-commits, george.burgess.iv, chandlerc Tags: #llvm Differential Revision: https://reviews.llvm.org/D60832 llvm-svn: 359032
* [AArch64][GlobalISel] Actually select G_INTRINSIC_TRUNCJessica Paquette2019-04-231-1/+58
| | | | | | | | | | | | | | Apparently FileCheck wasn't actually matching the fallback check lines in arm64-vfloatintrinsics.ll properly. So, there were selection fallbacks for G_INTRINSIC_TRUNC there. Actually hook it up into AArch64InstructionSelector.cpp and write a proper selection test. I guess I'll figure out the FileCheck magic to make the fallback checks work properly in arm64-vfloatintrinsics.ll. llvm-svn: 359030
* [ObjC][ARC] Check the basic block size before callingAkira Hatanaka2019-04-231-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DominatorTree::dominate. ARC contract pass has an optimization that replaces the uses of the argument of an ObjC runtime function call with the call result. For example: ; Before optimization %1 = tail call i8* @foo1() %2 = tail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* %1) store i8* %1, i8** @g0, align 8 ; After optimization %1 = tail call i8* @foo1() %2 = tail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* %1) store i8* %2, i8** @g0, align 8 // %1 is replaced with %2 Before replacing the argument use, DominatorTree::dominate is called to determine whether the user instruction is dominated by the ObjC runtime function call instruction. The call to DominatorTree::dominate can be expensive if the two instructions belong to the same basic block and the size of the basic block is large. This patch checks the basic block size and just bails out if the size exceeds the limit set by command line option "arc-contract-max-bb-size". rdar://problem/49477063 Differential Revision: https://reviews.llvm.org/D60900 llvm-svn: 359027
* Reapply: "DebugInfo: Emit only one kind of accelerated access/name table""David Blaikie2019-04-233-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Originally committed in r358931 Reverted in r358997 Seems this change made Apple accelerator tables miss names (because names started respecting the CU NameTableKind GNU & assuming that shouldn't produce accelerated names too), which is never correct (apple accelerator tables don't have separators or CU lists - if present, they must describe all names in all CUs). Original Description: Currently to opt in to debug_names in DWARFv5, the IR must contain 'nameTableKind: Default' which also enables debug_pubnames. Instead, only allow one of {debug_names, apple_names, debug_pubnames, debug_gnu_pubnames}. nameTableKind: Default gives debug_names in DWARFv5 and greater, debug_pubnames in v4 and earlier - and apple_names when tuning for lldb on MachO. nameTableKind: GNU always gives gnu_pubnames llvm-svn: 359026
* [ThinLTO] Pass down opt level to LTO backend and handle -O0 LTO in new PMTeresa Johnson2019-04-231-1/+14
| | | | | | | | | | | | | | | | | | | | | | | Summary: The opt level was not being passed down to the ThinLTO backend when invoked via clang (for distributed ThinLTO). This exposed an issue where the new PM was asserting if the Thin or regular LTO backend pipelines were invoked with -O0 (not a new issue, could be provoked by invoking in-process *LTO backends via linker using new PM and -O0). Fix this similar to the old PM where -O0 only does the necessary lowering of type metadata (WPD and LowerTypeTest passes) and then quits, rather than asserting. Reviewers: xur Subscribers: mehdi_amini, inglorion, eraman, hiraditya, steven_wu, dexonsmith, cfe-commits, llvm-commits, pcc Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D61022 llvm-svn: 359025
* llvm-cvtres: Split addChild(ID) into two functionsNico Weber2019-04-231-13/+23
| | | | | | | | | | | Before, there was an IsData parameter. Now, there are two different functions for data nodes and ID nodes. No behavior change, needed for a follow-up change to make two data nodes (but not two ID nodes) with the same ID an error. For consistency, rename another addChild() overload to addNameChild(). llvm-svn: 359024
* [AArch64][GlobalISel] Teach regbankselect about G_INTRINSIC_TRUNCJessica Paquette2019-04-231-0/+1
| | | | | | | | Add it to isPreISelGenericFloatingPointOpcode, and add a regbankselect test. Update arm64-vfloatintrinsics.ll now that we can select it. llvm-svn: 359022
* [AArch64][GlobalISel] Legalize G_INTRINSIC_TRUNCJessica Paquette2019-04-232-1/+2
| | | | | | | | | Same patch as G_FCEIL etc. Add the missing switch case in widenScalar, add G_INTRINSIC_TRUNC to the correct rule in AArch64LegalizerInfo.cpp, and add a test. llvm-svn: 359021
* [ConstantRange] Add urem supportNikita Popov2019-04-231-0/+15
| | | | | | | | | | | | | Add urem support to ConstantRange, so we can handle in in LVI. This is an approximate implementation that tries to capture the most useful conditions: If the LHS is always strictly smaller than the RHS, then the urem is a no-op and the result is the same as the LHS range. Otherwise the lower bound is zero and the upper bound is min(LHSMax, RHSMax - 1). Differential Revision: https://reviews.llvm.org/D60952 llvm-svn: 359019
* [AMDGPU] Fixed addReg() in SIOptimizeExecMaskingPreRA.cppStanislav Mekhanoshin2019-04-231-1/+1
| | | | | | | | The second argument is flags, not subreg. Differential Revision: https://reviews.llvm.org/D61031 llvm-svn: 359017
* [AArch64][GlobalISel] Legalize G_FMA for more vector typesJessica Paquette2019-04-231-2/+3
| | | | | | | | | Same as G_FCEIL, G_FABS, etc. Just move it into that rule. Add a legalizer test for G_FMA, which we didn't have before and update arm64-vfloatintrinsics.ll. llvm-svn: 359015
* [AliasAnalysis] AAResults preserves AAManager.Alina Sbirlea2019-04-231-6/+4
| | | | | | | | | | | | | | | | Summary: AAResults should not invalidate AAManager. Update tests. Reviewers: chandlerc Subscribers: mehdi_amini, jlebar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60914 llvm-svn: 359014
* [AArch64][GlobalISel] Add G_FMA to isPreISelGenericFloatingPointOpcodeJessica Paquette2019-04-231-0/+1
| | | | | | | | Noticed an unnecessary fallback in arm64-vmul caused by this. Also add a regbankselect test for G_FMA. llvm-svn: 359013
* llvm-undname: Support demangling the spaceship operatorNico Weber2019-04-232-5/+5
| | | | | | Also add a test for demanling the co_await operator. llvm-svn: 359007
* [InstCombine] Convert a masked.load of a dereferenceable address to an ↵Philip Reames2019-04-231-4/+14
| | | | | | | | | | unconditional load If we have a masked.load from a location we know to be dereferenceable, we can simply issue a speculative unconditional load against that address. The key advantage is that it produces IR which is well understood by the optimizer. The select (cnd, load, passthrough) form produced should be pattern matchable back to hardware predication if profitable. Differential Revision: https://reviews.llvm.org/D59703 llvm-svn: 359000
* [x86] use psubus for more vsetcc lowering (PR39859)Sanjay Patel2019-04-231-8/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Circling back to a leftover bit from PR39859: https://bugs.llvm.org/show_bug.cgi?id=39859#c1 ...we have this counter-intuitive (based on the test diffs) opportunity to use 'psubus'. This appears to be the better perf option for both Haswell and Jaguar based on llvm-mca. We already do this transform for the SETULT predicate, so this makes the code more symmetrical too. If we have pminub/pminuw, we prefer those, so this should not affect anything but pre-SSE4.1 subtargets. $ cat before.s movdqa -16(%rip), %xmm2 ## xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] pxor %xmm0, %xmm2 pcmpgtw -32(%rip), %xmm2 ## xmm2 = [255,255,255,255,255,255,255,255] pand %xmm2, %xmm0 pandn %xmm1, %xmm2 por %xmm2, %xmm0 $ cat after.s movdqa -16(%rip), %xmm2 ## xmm2 = [256,256,256,256,256,256,256,256] psubusw %xmm0, %xmm2 pxor %xmm3, %xmm3 pcmpeqw %xmm2, %xmm3 pand %xmm3, %xmm0 pandn %xmm1, %xmm3 por %xmm3, %xmm0 $ llvm-mca before.s -mcpu=haswell Iterations: 100 Instructions: 600 Total Cycles: 909 Total uOps: 700 Dispatch Width: 4 uOps Per Cycle: 0.77 IPC: 0.66 Block RThroughput: 1.8 $ llvm-mca after.s -mcpu=haswell Iterations: 100 Instructions: 700 Total Cycles: 409 Total uOps: 700 Dispatch Width: 4 uOps Per Cycle: 1.71 IPC: 1.71 Block RThroughput: 1.8 Differential Revision: https://reviews.llvm.org/D60838 llvm-svn: 358999
* [SPARC] Use the correct register set for the "r" asm constraint.Joerg Sonnenberger2019-04-231-0/+2
| | | | | | | | 64bit mode must use 64bit registers, otherwise assumptions about the top half of the registers are made. Problem found by Takeshi Nakayama in NetBSD. llvm-svn: 358998
* Revert "DebugInfo: Emit only one kind of accelerated access/name table"David Blaikie2019-04-233-8/+3
| | | | | | | | Regresses some apple_names situations - still investigating. This reverts commit r358931. llvm-svn: 358997
* Use llvm::stable_sortFangrui Song2019-04-2340-159/+128
| | | | | | While touching the code, simplify if feasible. llvm-svn: 358996
* [RISCV] Support assembling %tls_{ie,gd}_pcrel_hi modifiersLewis Revill2019-04-238-4/+48
| | | | | | | | | This patch adds support for parsing and assembling the %tls_ie_pcrel_hi and %tls_gd_pcrel_hi modifiers. Differential Revision: https://reviews.llvm.org/D55342 llvm-svn: 358994
* [AMDGPU] Fix hidden argument metadata duplication for V3Scott Linder2019-04-231-30/+0
| | | | | | | | | | Essentially complete a proper rebase of the V3 metadata change over https://reviews.llvm.org/D49096. Minimize the diff between the V2 and V3 variants of the relevant lit tests, and clean up some trailing whitespace. llvm-svn: 358992
* [X86] Pull out collectConcatOps helper. NFCI.Simon Pilgrim2019-04-231-21/+51
| | | | | | Create collectConcatOps helper that returns all the subvector ops for CONCAT_VECTORS or a INSERT_SUBVECTOR series. llvm-svn: 358989
* ARM: disallow add/sub to sp unless Rn is also sp.Tim Northover2019-04-232-1/+27
| | | | | | | | The manual says that Thumb2 add/sub instructions are only allowed to modify sp if the first source is also sp. This is slightly different from the usual rGPR restriction since it's context-sensitive, so implement it in C++. llvm-svn: 358987
* [DAGCombiner] generalize binop-of-splats scalarizationSanjay Patel2019-04-231-46/+38
| | | | | | | | | | | | | | If we only match build vectors, we can miss some patterns that use shuffles as seen in the affected tests. Note that the underlying calls within getSplatSourceVector() have the potential for compile-time explosion because of exponential recursion looking through binop opcodes, but currently the list of supported opcodes is very limited. Both of those problems should be addressed in follow-up patches. llvm-svn: 358984
* AMDGPU: Fix LCSSA phi lowering in SILowerI1CopiesNicolai Haehnle2019-04-231-1/+8
| | | | | | | | | | | | | | | | | | | | | | Summary: When an LCSSA phi survives through instruction selection, the pass ends up removing that phi entirely because it is dominated by the logic that does the lanemask merging. This then used to trigger an assertion when processing a dependent phi instruction. Change-Id: Id4949719f8298062fe476a25718acccc109113b6 Reviewers: llvm-commits Subscribers: kzhuravl, jvesely, wdng, yaxunl, t-tye, tpr, dstuttard, rtaylor, arsenm Tags: #llvm Differential Revision: https://reviews.llvm.org/D60999 llvm-svn: 358983
* [CallSite removal] move InlineCost to CallBase usageFedor Sergeev2019-04-236-114/+113
| | | | | | | | | | | Converting InlineCost interface and its internals into CallBase usage. Inliners themselves are still not converted. Reviewed By: reames Tags: #llvm Differential Revision: https://reviews.llvm.org/D60636 llvm-svn: 358982
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