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* [SelectionDAG] Improve selection of DBG_VALUE using a PHI node resultBjorn Pettersson2018-04-304-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When building the selection DAG at ISel all PHI nodes are selected and lowered to Machine Instruction PHI nodes before we start to create any SDNodes. So there are no SDNodes for values produced by the PHI nodes. In the past when selecting a dbg.value intrinsic that uses the value produced by a PHI node we have been handling such dbg.value intrinsics as "dangling debug info". I.e. we have not created a SDDbgValue node directly, because there is no existing SDNode for the PHI result, instead we deferred the creationg of a SDDbgValue until we found the first use of the PHI result. The old solution had a couple of flaws. The position of the selected DBG_VALUE instruction would end up quite late in a basic block, and for example not directly after the PHI node as in the LLVM IR input. And in case there were no use at all in the basic block the dbg.value could be dropped completely. This patch introduces a new VREG kind of SDDbgValue nodes. It is similar to a SDNODE kind of node, but it refers directly to a virtual register and not a SDNode. When we do selection for a dbg.value that is using the result of a PHI node we can do a lookup of the virtual register directly (as it already is determined for the PHI node) and create a SDDbgValue node immediately instead of delaying the selection until we find a use. This should fix a problem with losing debug info at ISel as seen in PR37234 (https://bugs.llvm.org/show_bug.cgi?id=37234). It does not resolve PR37234 completely, because the debug info is dropped later on in the BranchFolder (see D46184). Reviewers: #debug-info, aprantl Reviewed By: #debug-info, aprantl Subscribers: rnk, gbedwell, aprantl, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D46129 llvm-svn: 331182
* NFC, Avoid a warning on pointer casting in PassPlugin.cppGabor Buella2018-04-301-2/+4
| | | | llvm-svn: 331179
* Revert "[mips] Fix the predicates of jump and branch and link instructions"Simon Dardis2018-04-303-67/+50
| | | | | | | | That commit broke one of the LLD builders, reverting while I investigate. This patch reverts r331175. llvm-svn: 331178
* [mips] Fix the predicates of jump and branch and link instructionsSimon Dardis2018-04-303-50/+67
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D46114 llvm-svn: 331175
* [LV] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).Florian Hahn2018-04-301-8/+3
| | | | | | | | | | | | | | This patch updates some code responsible the skip debug info to use BasicBlock::instructionsWithoutDebug. I think this makes things slightly simpler and more direct. Reviewers: mkuper, rengolin, dcaballe, aprantl, vsk Reviewed By: rengolin Differential Revision: https://reviews.llvm.org/D46254 llvm-svn: 331174
* [X86] Fix typo in skylake-avx512 model for PMAXSD/PMINSD instructionsSimon Pilgrim2018-04-301-20/+20
| | | | | | The PMAXSD/PMINSD instregexs had been written as PMAX(C?)SD - looks like this was a search+replace error when matching float MAXSD/MINSD commutative instructions. llvm-svn: 331167
* [mips] Fix microMIPS loads and stores.Simon Dardis2018-04-302-33/+41
| | | | | | | | | | | Previously these instructions were unselectable and instead were generated through the instruction mapping tables. Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46055 llvm-svn: 331165
* [AArch64][SVE] Asm: Improve diagnostics for gather loads.Sander de Smalen2018-04-303-19/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends the 'isSVEVectorRegWithShiftExtend' function to improve diagnostics for SVE's gather load (scalar + vector) addressing modes. Instead of always suggesting the 'unscaled' addressing mode, the use of DiagnosticPredicate enables a more specific error message in the context where the scaling is incorrect. For example: ld1h z0.d, p0/z, [x0, z0.d, lsl #2] ^ shift amount should be '1' Instead of suggesting the packed, unscaled addressing mode: expected 'z[0..31].d, (uxtw|sxtw)' the assembler now suggests using the proper scaling: expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46124 llvm-svn: 331162
* [X86] Add a Requires<[In64BitMode]> to FARJMP64Craig Topper2018-04-301-1/+1
| | | | | | Otherwise we can try to assemble it in 32-bit mode and throw an assert in the encoder. llvm-svn: 331161
* [X86] Hide another instruction from the assembly matcher table to avoid a ↵Craig Topper2018-04-301-0/+1
| | | | | | duplicate entry. NFC llvm-svn: 331160
* [X86] Remove some InstAliases aren't needed because a MnemonicAlias makes ↵Craig Topper2018-04-301-3/+0
| | | | | | them unreachable. llvm-svn: 331159
* [X86] Remove some instructions from the Intel assembly matcher table as ↵Craig Topper2018-04-301-2/+2
| | | | | | | | | | there are equivalent mode aware InstAliases that conflict. The instructions have predicates of Not64BitMode, but there are identical strings in InstAliases that have Mode32Bit and Mode16Bit. But the ordering is uncontrolled and the less specific Not64BitMode was ordered first. This patch hides the Not64BitMode from the table so there is no conflict anymore. llvm-svn: 331158
* [X86] Use a MnemonicAlias instead of an InstAlias.Craig Topper2018-04-302-9/+8
| | | | llvm-svn: 331157
* [X86] Remove support for accepting 'fnstsw %eax' and 'fnstsw %al'.Craig Topper2018-04-301-4/+1
| | | | | | I assume this was done because gas accepted it at one point, but current versions of gas don't. llvm-svn: 331154
* [X86] Mark some more InstAliases as 'att' syntax only.Craig Topper2018-04-301-6/+6
| | | | | | These aliases are used to default the memory forms of call and jmp to the size of the operating mode. This doesn't work for Intel syntax. We have a different hack in the AsmParser code itself to force a size on unsized memory operands. llvm-svn: 331153
* Remove a dead #ifdef.Nico Weber2018-04-301-2/+0
| | | | | | | Unix/Threading.inc should never be included on _WIN32. See also https://reviews.llvm.org/D30526#1082292 llvm-svn: 331151
* [X86] Make 64-bit sysret/sysexit not ambiguous in Intel assembly syntax.Craig Topper2018-04-291-2/+2
| | | | | | This also makes it default to the 32-bit non REX.W version in 64-bit mode. This seems to be more consistent with gas. llvm-svn: 331149
* [X86] Remove unnecessary BT InstRW overrides.Simon Pilgrim2018-04-291-5/+1
| | | | llvm-svn: 331147
* [AArch64][AsmParser] NFC: Cleanup of addOperands functionsSander de Smalen2018-04-294-230/+81
| | | | | | | | | | | | | | | | Most of the add<operandname>Operands() functions are the same and can be replaced by using a single 'RenderMethod' in the AArch64InstrFormats.td file. Since many of the scaled immediates (with different scaling/bits) are the same, most of these can reuse the same AsmOperandClass. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: samparker Differential Revision: https://reviews.llvm.org/D46122 llvm-svn: 331146
* [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (vector + imm) load ↵Sander de Smalen2018-04-294-4/+156
| | | | | | | | | | | | instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46120 llvm-svn: 331145
* [X86] Merge more instregex single matches to reduce InstrRW compile time.Simon Pilgrim2018-04-296-393/+195
| | | | llvm-svn: 331143
* [X86] Remove unnecessary add/adc+sub/sbb InstRW overrides.Simon Pilgrim2018-04-291-9/+0
| | | | llvm-svn: 331142
* [NFC][LV][LoopUtil] Move LoopVectorizationLegality to its own fileHideki Saito2018-04-293-1456/+1075
| | | | | | | | | | | | | | | | | | | | | Summary: This is a follow up to D45420 (included here since it is still under review and this change is dependent on that) and D45072 (committed). Actual change for this patch is LoopVectorize* and cmakefile. All others are all from D45420. LoopVectorizationLegality is an analysis and thus really belongs to Analysis tree. It is modular enough and it is reusable enough ---- we can further improve those aspects once uses outside of LV picks up. Hopefully, this will make it easier for people familiar with vectorization theory, but not necessarily LV itself to contribute, by lowering the volume of code they should deal with. We probably should start adding some code in LV to check its own capability (i.e., vectorization is legal but LV is not ready to handle it) and then bail out. Reviewers: rengolin, fhahn, hfinkel, mkuper, aemerson, mssimpso, dcaballe, sguggill Reviewed By: rengolin, dcaballe Subscribers: egarcia, rogfer01, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D45552 llvm-svn: 331139
* [X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in Intel syntax. Add ↵Craig Topper2018-04-291-8/+17
| | | | | | | | | | aliases based on 16/32-bit mode to choose the default. This allows the instruction selection to follow mode in Intel syntax. And allows a suffix to be used to change size. This matches gas behavior from what I could tell. llvm-svn: 331138
* [X86] Remove SLDT64m instruction.Craig Topper2018-04-295-7/+0
| | | | | | | | It doesn't really exist. The instruction always writes 16-bits of memory. Putting a REX.w on it won't change anything. While I was touching the encoding tests to remove it, I added some other missing register form test cases. llvm-svn: 331135
* [X86] Remove unnecessary InstAliases. NFCICraig Topper2018-04-291-6/+0
| | | | | | These used to disambiguate MOV16ms/MOV16sm from other size instructions that no longer exist. llvm-svn: 331134
* [X86] Use getX86SubSuperRegister in addGR32orGR64Operands in the AsmParser ↵Craig Topper2018-04-291-24/+1
| | | | | | instead of duplicating its functionality. NFC llvm-svn: 331128
* s/LLVM_ON_WIN32/_WIN32/, llvmNico Weber2018-04-2925-50/+50
| | | | | | | | | | | | | | LLVM_ON_WIN32 is set exactly with MSVC and MinGW (but not Cygwin) in HandleLLVMOptions.cmake, which is where _WIN32 defined too. Just use the default macro instead of a reinvented one. See thread "Replacing LLVM_ON_WIN32 with just _WIN32" on llvm-dev and cfe-dev. No intended behavior change. This moves over all uses of the macro, but doesn't remove the definition of it in (llvm-)config.h yet. llvm-svn: 331127
* [LLVM-C] Add DIBuilder bindings to create import declarationsRobert Widmann2018-04-281-0/+49
| | | | | | | | | | | | | | Summary: Add bindings to create import declarations for modules, functions, types, and other entities. This wraps the conveniences available in the existing DIBuilder API, but these seem C++-specific. Reviewers: whitequark, harlanhaskins, deadalnix Reviewed By: whitequark Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46167 llvm-svn: 331123
* [X86] Restrict many of the InstAliases to either to only att or intel ↵Craig Topper2018-04-283-103/+103
| | | | | | | | | | | | syntax. NFCI Many of these aliases exist to give one syntax or the other a slightly different mnemonic and the other variant gets a duplicate of its normal mnemonic This patch restricts a lot of these to only one variant so we don't get the duplication. This removes a lot of duplicate entries from the matcher table. It also reduces the number of warnings printed when you enable the ambiguous match warning in tablegen. llvm-svn: 331117
* [X86] Remove unnecessary rotate-carry folded InstRW overrides.Simon Pilgrim2018-04-281-17/+2
| | | | | | Merge some remaining instregex entries. llvm-svn: 331116
* [globalisel][legalizerinfo] Introduce dedicated extending loads and add ↵Daniel Sanders2018-04-283-5/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | lowerings for them Summary: Previously, a extending load was represented at (G_*EXT (G_LOAD x)). This had a few drawbacks: * G_LOAD had to be legal for all sizes you could extend from, even if registers didn't naturally hold those sizes. * All sizes you could extend from had to be allocatable just in case the extend went missing (e.g. by optimization). * At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we improve optimization of extends and truncates, this legality requirement would spread without considerable care w.r.t when certain combines were permitted. * The SelectionDAG importer required some ugly and fragile pattern rewriting to translate patterns into this style. This patch begins changing the representation to: * (G_[SZ]EXTLOAD x) * (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits() which resolves these issues by allowing targets to work entirely in their native register sizes, and by having a more direct translation from SelectionDAG patterns. This patch introduces the new generic instructions and new variation on G_LOAD and adds lowering for them to convert back to the existing representations. Depends on D45466 Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, aemerson, javed.absar Reviewed By: aemerson Subscribers: aemerson, kristof.beyls, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D45540 llvm-svn: 331115
* [LLVM-C] Miscellaneous Cleanups in DIBuilder BindingsRobert Widmann2018-04-281-16/+52
| | | | | | | | | | | | | | | | Summary: * rL328953 does not include bindings for LLVMDIBuilderCreateClassType and LLVMDIBuilderCreateBitFieldMemberType despite declaring their prototypes. Provide these bindings now. * Switch to more precise types with specific numeric limits matching the DIBuilder's C++ API. Reviewers: harlanhaskins, whitequark, deadalnix Reviewed By: whitequark Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46168 llvm-svn: 331114
* [InstCombine] Canonicalize variable mask in masked mergeRoman Lebedev2018-04-281-0/+33
| | | | | | | | | | | | | | | | | | | Summary: Masked merge has a pattern of: `((x ^ y) & M) ^ y`. But, there is no difference between `((x ^ y) & M) ^ y` and `((x ^ y) & ~M) ^ x`, We should canonicalize the pattern to non-inverted mask. https://rise4fun.com/Alive/Yol Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45664 llvm-svn: 331112
* [X86] Remove unnecessary shift/rotate folded InstRW overrides.Simon Pilgrim2018-04-284-24/+3
| | | | llvm-svn: 331110
* [X86][SSE] Stop hard coding some instruction scheduler classes.Simon Pilgrim2018-04-281-49/+58
| | | | | | Make these arguments to the multiclass to allow easier specialization. llvm-svn: 331107
* [X86][HW] Cleanup Haswell model. NFCI.Simon Pilgrim2018-04-281-9/+3
| | | | | | | | Moved LAHF/SAHF to instrs instead of instregex. Removed some unnecessary instregex entries. llvm-svn: 331106
* [X86] Remove mayLoad flag from BNDMK/BNDCL/BNDCN/BNDCU.Craig Topper2018-04-281-4/+1
| | | | | | The instruction documentation specifically says that these instruction don't access memory. llvm-svn: 331105
* [X86] Change memory operand of BNDMK/BNDCL/BNDCU/BNDCN/BNDST to anymem.Craig Topper2018-04-281-5/+5
| | | | | | These instruction don't use their memory operands as normal memory operands. They're just used as addresses. They don't have a size because they aren't directly representing a load or store. llvm-svn: 331104
* [SCEV] Touch the unsused stats variables for product build.Serguei Katkov2018-04-281-0/+3
| | | | | | This is a fix by elimination compiler warnings considered as errors. llvm-svn: 331103
* [X86] Remove REX.W from 64-bit mode BND instructions.Craig Topper2018-04-281-5/+5
| | | | | | As far as I can tell from the docs, the instructions are automatically 64-bit in 64-bit mode. We don't need REX.W. llvm-svn: 331102
* [X86] Rename BNDMOV instructions and hide redundant instruction encoding ↵Craig Topper2018-04-282-20/+21
| | | | | | | | | | | | from the assembler. Favor the 0x1a encoding for register/register move to match gas. The instructions used RM and MR in their name along with rr/rm/mr at the end. To make more consistent with other instructions remove the RM/MR and use rr/rm/mr/rr_REV. Hide the _REV encoding from the assembler but leave it for the disassembler. llvm-svn: 331101
* [SCEV] Reduce the number of invocation to non trivial getExact functionSerguei Katkov2018-04-281-2/+5
| | | | | | | | | | | | | | | | | The invocation of getExact in ScalarEvolution::getBackedgeTakenInfo is used only for getting statistic and for assert. Even if statistics is disabled, the code related to it will be eliminated the invocation to getExact itself will not be eliminated because it may have side-effects like creation of new SCEVs. So do invocation only when we collect statistics or executes asserts. Reviewers: mkazantsev, sanjoy, javed.absar Reviewed By: javed.absar Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46178 llvm-svn: 331099
* [MachineOutliner] Add defs to calls + don't track liveness on outlined functionsJessica Paquette2018-04-272-6/+39
| | | | | | | | | | | | | This commit makes it so that if you outline a def of some register, then the call instruction created by the outliner actually reflects that the register is defined by the call. It also makes it so that outlined functions don't have the TracksLiveness property. Outlined calls shouldn't break liveness assumptions that someone might make. This also un-XFAILs the noredzone test, and updates the calls test. llvm-svn: 331095
* [LoopGuardWidening] Make PostDomTree optionalPhilip Reames2018-04-271-10/+28
| | | | | | | | The effect of doing so is not disrupting the LoopPassManager when mixing this pass with other loop passes. This should help locality of access substaintially and avoids the cost of computing PostDom. The assumption here is that the full GuardWidening (which does use PostDom) is run as a canonicalization before loop opts and that this version is just catching cases exposed by other loop passes. (i.e. LoopPredication, IndVarSimplify, LoopUnswitch, etc..) llvm-svn: 331094
* [DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisorHeejin Ahn2018-04-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector dividers. But when there is a 1 in a vector, the instruction sequence to be generated involves shifting a value by the number of its bit widths, which is undefined (https://github.com/llvm-mirror/llvm/blob/c64f4dbfe31e509f9c1092b951e524b056245af8/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6000-L6006). Especially, in architectures that do not support vector instructions, each of element in a vector will be computed separately using scalar operations, and then the resulting value will be undef for '1' values in a vector. (All 1's vector is fine; only vectors mixed with 1 and others will be affected.) Reviewers: RKSimon, jgravelle-google Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D46161 llvm-svn: 331092
* [X86] Make the STTNI flag intrinsics use the flags from pcmpestrm/pcmpistrm ↵Craig Topper2018-04-276-217/+215
| | | | | | | | | | | | | | | | | | | | | | | if the mask instrinsics are also used in the same basic block. Summary: Previously the flag intrinsics always used the index instructions even if a mask instruction also exists. To fix fix this I've created a single ISD node type that returns index, mask, and flags. The SelectionDAG CSE process will merge all flavors of intrinsics with the same inputs to a s ingle node. Then during isel we just have to look at which results are used to know what instruction to generate. If both mask and index are used we'll need to emit two instructions. But for all other cases we can emit a single instruction. Since I had to do manual isel anyway, I've removed the pseudo instructions and custom inserter code that was working around tablegen limitations with multiple implicit defs. I've also renamed the recently added sse42.ll test case to sttni.ll since it focuses on that subset of the sse4.2 instructions. Reviewers: chandlerc, RKSimon, spatel Reviewed By: chandlerc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46202 llvm-svn: 331091
* Fix a bug that prevents global variables from having a DW_OP_deref.Adrian Prantl2018-04-273-3/+10
| | | | | | | | | | | | | | For local variables the first DW_OP_deref is consumed by turning the location kind into a memeory location, but that only makes sense for values that are in a register to begin with, which cannot happen for global variables that are attached to a symbol. rdar://problem/39741860 This reapplies r330970 after fixing an uncovered bug in r331086 and working around the situation caused by it. llvm-svn: 331090
* [FastISel] Actually enable local value sinking by defaultReid Kleckner2018-04-271-4/+2
| | | | llvm-svn: 331088
* [FastISel] Fix local value sinking algorithmic complexityReid Kleckner2018-04-271-3/+12
| | | | | | | | | | Now local value sinking only scans and numbers instructions added between the current flush point and the last flush point. This ensures that ISel is overall linear in the size of the BB. Fixes PR37010 and re-enables local value sinking by default. llvm-svn: 331087
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