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* [fast-isel] Add support for UDIV.Chad Rosier2012-02-031-8/+10
| | | | llvm-svn: 149712
* ArrayRef'ize MI::setPhysRegsDeadExcept().Jakob Stoklund Olesen2012-02-031-3/+3
| | | | llvm-svn: 149709
* Handle all live physreg defs in the same place.Jakob Stoklund Olesen2012-02-032-44/+47
| | | | | | | | | | | SelectionDAG has 4 different ways of passing physreg defs to users. Collect all of the uses at the same time, and pass all of them to MI->setPhysRegsDeadExcept() to mark the remaining defs dead. The setPhysRegsDeadExcept() function will soon add the required implicit-defs to instructions with register mask operands. llvm-svn: 149708
* [fast-isel] Add support for FPToUI. Also add test cases for FPToSI.Chad Rosier2012-02-031-6/+8
| | | | llvm-svn: 149706
* Initialize all common codegen passes before configuration so we can use ↵Andrew Trick2012-02-031-0/+7
| | | | | | their PassIDs. llvm-svn: 149705
* [fast-isel] Add support for selecting UIToFP.Chad Rosier2012-02-031-6/+8
| | | | llvm-svn: 149704
* Simplify some GEP checks in the verifier.Duncan Sands2012-02-031-4/+2
| | | | llvm-svn: 149698
* The type-legalizer often scalarizes code. One of the common patterns is ↵Nadav Rotem2012-02-031-0/+34
| | | | | | | | | extract-and-truncate. In this patch we optimize this pattern and convert the sequence into extract op of a narrow type. This allows the BUILD_VECTOR dag optimizations to construct efficient shuffle operations in many cases. llvm-svn: 149692
* Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate ↵Craig Topper2012-02-031-30/+1
| | | | | | performs the same calculation. llvm-svn: 149683
* Remove unnecessary qualification on 256-bit vector handling in ↵Craig Topper2012-02-031-2/+2
| | | | | | LowerBUILD_VECTOR. Condition was already guaranteed by earlier code. llvm-svn: 149680
* Add auto upgrade support for x86 pcmpgt/pcmpeq intrinics removed in r149367.Craig Topper2012-02-031-3/+40
| | | | llvm-svn: 149678
* Added TargetPassConfig. The first little step toward configuring codegen passes.Andrew Trick2012-02-0323-198/+451
| | | | | | | | | | | Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. llvm-svn: 149672
* whitespaceAndrew Trick2012-02-037-32/+32
| | | | llvm-svn: 149671
* Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which isAkira Hatanaka2012-02-0310-3/+45
| | | | | | | | needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. llvm-svn: 149668
* Incorporate suggestions Chad, Jakob and Evan's suggestions on r149957.Lang Hames2012-02-031-22/+33
| | | | llvm-svn: 149655
* Narrow test further. Make bot and test happy.Jim Grosbach2012-02-031-1/+3
| | | | llvm-svn: 149650
* Tidy up. Trailing whitespace.Jim Grosbach2012-02-031-55/+55
| | | | llvm-svn: 149649
* Restrict InstCombine from converting varargs to or from fixed args.Jim Grosbach2012-02-031-0/+7
| | | | | | More targetted fix replacing d0e277d272d517ca1cda368267d199f0da7cad95. llvm-svn: 149648
* Revert "Disable InstCombine unsafe folding bitcasts of calls w/ varargs."Jim Grosbach2012-02-031-5/+14
| | | | | | This reverts commit d0e277d272d517ca1cda368267d199f0da7cad95. llvm-svn: 149647
* Require non-NULL register masks.Jakob Stoklund Olesen2012-02-024-11/+5
| | | | | | | It doesn't seem worthwhile to give meaning to a NULL register mask pointer. It complicates all the code using register mask operands. llvm-svn: 149646
* Add pseudo-registers for pairs, triples, and quads of D registers.Jakob Stoklund Olesen2012-02-021-15/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | NEON loads and stores accept single and double spaced pairs, triples, and quads of D registers. This patch adds new register classes to accurately model those constraints: Dn, Dn+1 Dn, Dn+2 ---------------------- DPair DPairSpc DTriple DTripleSpc DQuad DQuadSpc Also extend the existing QQ and QQQQ register classes to contains all Q pairs and quads instead of just the aligned ones. These new register classes will make it possible to accurately model constraints on NEON loads and stores, and we can get rid of all the NEON pseudo-instructions. The late scheduler will be able to accurately model instruction dependencies from the explicit operands. This more than doubles the number of ARM registers, but the backend passes are quite good at handling this. The llc -O0 compile time only regresses by 1.5%. Future work on register mask operands will recover this regression. llvm-svn: 149640
* BBVectorize: Simplify code, no functionality change.Benjamin Kramer2012-02-021-9/+3
| | | | | | Also silences warnings about bodyless for loops. llvm-svn: 149612
* Minor changes from review.Hal Finkel2012-02-021-19/+17
| | | | | | As suggested by Nick Lewycky, the tree traversal queues have been changed to SmallVectors and the associated loops have been rotated. Also, an 80-col violation was fixed. llvm-svn: 149607
* Minor change in signature of the getZeroVector() Elena Demikhovsky2012-02-021-30/+21
| | | | llvm-svn: 149601
* Optimization for SIGN_EXTEND operation on AVX.Elena Demikhovsky2012-02-024-0/+67
| | | | | | | Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32 extensions. llvm-svn: 149600
* Unbreak the MSVC build.Francois Pichet2012-02-021-1/+1
| | | | llvm-svn: 149599
* Re-apply the coalescer fix from r149147. Commit r149597 should have fixed ↵Lang Hames2012-02-021-0/+24
| | | | | | the llvm-gcc and clang self-host issues. llvm-svn: 149598
* Set EFLAGS correctly in EmitLoweredSelect on X86.Lang Hames2012-02-021-2/+29
| | | | llvm-svn: 149597
* Break as soon as the MustMapCurValNos flag is set - no need to reiterate.Lang Hames2012-02-021-1/+3
| | | | llvm-svn: 149596
* Vectorize long blocks in groups.Hal Finkel2012-02-021-41/+90
| | | | | | Long basic blocks with many candidate pairs (such as in the SHA implementation in Perl 5.14; thanks to Roman Divacky for the example) used to take an unacceptably-long time to compile. Instead, break long blocks into groups so that no group has too many candidate pairs. llvm-svn: 149595
* PR11868. The previous loop in LiveIntervals::join would sometimes fall over ifLang Hames2012-02-021-11/+12
| | | | | | | more than two adjacent ranges needed to be merged. The new version should be able to handle an arbitrary sequence of adjancent ranges. llvm-svn: 149588
* Set the correct stack pointer register.Akira Hatanaka2012-02-021-1/+1
| | | | llvm-svn: 149585
* Expand EHSELECTION and EHSELECTION nodes. Set the correct exception pointer andAkira Hatanaka2012-02-021-2/+4
| | | | | | | selector registers. llvm-svn: 149584
* Add DWARF numbers of 64-bit registers.Akira Hatanaka2012-02-021-64/+64
| | | | llvm-svn: 149583
* TypoPete Cooper2012-02-011-1/+1
| | | | llvm-svn: 149562
* Fix the cmake buildRafael Espindola2012-02-011-0/+1
| | | | llvm-svn: 149561
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-0115-514/+1016
| | | | | | | | | | | | | | Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
* Move ARM subreg index compositions to the SubRegIndex itself.Jakob Stoklund Olesen2012-02-011-28/+22
| | | | llvm-svn: 149557
* fix cmakeAndrew Trick2012-02-011-1/+1
| | | | llvm-svn: 149553
* Avoid creating an extract element to an illegal type after LegalizeTypes has ↵Mon P Wang2012-02-011-2/+10
| | | | | | run. llvm-svn: 149548
* VLIW specific scheduler framework that utilizes deterministic finite ↵Andrew Trick2012-02-019-1/+980
| | | | | | | | | | automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! llvm-svn: 149547
* Tidy up.Chad Rosier2012-02-011-1/+1
| | | | llvm-svn: 149521
* Passing AVX 256-bit structures in Win64 was wrong.Elena Demikhovsky2012-02-011-0/+4
| | | | | | Fixed Win64 calling conventions. llvm-svn: 149494
* Shortened code in shuffle masksElena Demikhovsky2012-02-011-33/+11
| | | | llvm-svn: 149493
* Optimization for "truncate" operation on AVX.Elena Demikhovsky2012-02-012-0/+101
| | | | | | Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles. llvm-svn: 149485
* SwitchInst refactoring.Stepan Dyatkovskiy2012-02-0123-115/+132
| | | | | | | | | | | | | | | | | The purpose of refactoring is to hide operand roles from SwitchInst user (programmer). If you want to play with operands directly, probably you will need lower level methods than SwitchInst ones (TerminatorInst or may be User). After this patch we can reorganize SwitchInst operands and successors as we want. What was done: 1. Changed semantics of index inside the getCaseValue method: getCaseValue(0) means "get first case", not a condition. Use getCondition() if you want to resolve the condition. I propose don't mix SwitchInst case indexing with low level indexing (TI successors indexing, User's operands indexing), since it may be dangerous. 2. By the same reason findCaseValue(ConstantInt*) returns actual number of case value. 0 means first case, not default. If there is no case with given value, ErrorIndex will returned. 3. Added getCaseSuccessor method. I propose to avoid usage of TerminatorInst::getSuccessor if you want to resolve case successor BB. Use getCaseSuccessor instead, since internal SwitchInst organization of operands/successors is hidden and may be changed in any moment. 4. Added resolveSuccessorIndex and resolveCaseIndex. The main purpose of these methods is to see how case successors are really mapped in TerminatorInst. 4.1 "resolveSuccessorIndex" was created if you need to level down from SwitchInst to TerminatorInst. It returns TerminatorInst's successor index for given case successor. 4.2 "resolveCaseIndex" converts low level successors index to case index that curresponds to the given successor. Note: There are also related compatability fix patches for dragonegg, klee, llvm-gcc-4.0, llvm-gcc-4.2, safecode, clang. llvm-svn: 149481
* Add pass printer passes in the right place.Andrew Trick2012-02-011-81/+46
| | | | | | | | | | | | The pass pointer should never be referenced after sending it to schedulePass(), which may delete the pass. To fix this bug I had to clean up the design leading to more goodness. You may notice now that any non-analysis pass is printed. So things like loop-simplify and lcssa show up, while target lib, target data, alias analysis do not show up. Normally, analysis don't mutate the IR, but you can now check this by using both -print-after and -print-before. The effects of analysis will now show up in between the two. The llc path is still in bad shape. But I'll be improving it in my next checkin. Meanwhile, print-machineinstrs still works the same way. With print-before/after, many llc passes that were not printed before now are, some of these should be converted to analysis. A few very important passes, isel and scheduler, are not properly initialized, so not printed. llvm-svn: 149480
* Don't create VBROADCAST nodes if any nodes use the chain result from the ↵Craig Topper2012-02-011-0/+4
| | | | | | load. Fixes PR11900. llvm-svn: 149478
* BBVectorize.cpp: Try to fix MSVC build. map::iterator and multimap::iterator ↵NAKAMURA Takumi2012-02-011-2/+2
| | | | | | are incompatible. llvm-svn: 149475
* A few of the changes suggested in code review (by Nick Lewycky)Hal Finkel2012-02-011-7/+8
| | | | llvm-svn: 149472
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