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* [InstCombine] fix demanded-bits propagation for zext/truncSanjay Patel2018-01-171-1/+1
| | | | | | | | | I was comparing the demanded-bits implementations between InstCombine and TargetLowering as part of investigating questions in D42088 and noticed that this was wrong in IR. We were losing all of the prior known bits when we got back to the 'zext'. llvm-svn: 322662
* [RISCV] Allow RISCVAsmBackend::writeNopData to generate c.nop when supportedAlex Bradbury2018-01-171-8/+18
| | | | | | | | | | When the compressed instruction set is enabled, the 16-bit c.nop can be generated if necessary. Differential Revision: https://reviews.llvm.org/D41221 Patch by Shiva Chen. llvm-svn: 322658
* [ARM GlobalISel] Map G_FPEXT and G_FPTRUNC to FPRDiana Picus2018-01-171-0/+18
| | | | llvm-svn: 322657
* [AMDGPU] add LDS f32 intrinsicsDaniil Fukalov2018-01-178-11/+85
| | | | | | | | | | | | added llvm.amdgcn.atomic.{add|min|max}.f32 intrinsics to allow generate ds_{add|min|max}[_rtn]_f32 instructions needed for OpenCL float atomics in LDS Reviewed by: arsenm Differential Revision: https://reviews.llvm.org/D37985 llvm-svn: 322656
* [AMDGPU][MC][GFX9] Enable inline constants for SDWA operandsDmitry Preobrazhensky2018-01-175-65/+124
| | | | | | | | | See bug 35771: https://bugs.llvm.org/show_bug.cgi?id=35771 Differential Revision: https://reviews.llvm.org/D42058 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 322655
* [ARM GlobalISel] Legalize G_FPEXT and G_FPTRUNCDiana Picus2018-01-172-0/+59
| | | | | | | | | | | Mark G_FPEXT and G_FPTRUNC as legal or libcall, depending on hardware support, but only for conversions between float and double. Also add the necessary boilerplate so that the LegalizerHelper can introduce the required libcalls. This also works only for float and double, but isn't too difficult to extend when the need arises. llvm-svn: 322651
* [Transforms] Support making mutable versions of new-format TBAA access tagsIvan A. Kosarev2018-01-172-16/+29
| | | | | | Differential Revision: https://reviews.llvm.org/D41565 llvm-svn: 322650
* [X86] Don't mutate shuffle arguments after early-out for AVX512Benjamin Kramer2018-01-171-18/+22
| | | | | | | | | | The match* functions have the annoying behavior of modifying its inputs. Save and restore the inputs, just in case the early out for AVX512 is hit. This is still not great and its only a matter of time this kind of bug happens again, but I couldn't come up with a better pattern without rewriting significant chunks of this code. Fixes PR35977. llvm-svn: 322644
* [X86] Constify DebugLoc parameters. No functionality change.Benjamin Kramer2018-01-171-13/+10
| | | | llvm-svn: 322643
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-01-176-9/+9
| | | | | | "the the" -> "the" llvm-svn: 322636
* Don't emit apple accelerator tables on non-darwin targetsPavel Labath2018-01-171-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Currently -glldb turns on emission of apple tables on all targets, but lldb is only really capable of consuming them on darwin. Furthermore, making lldb consume these tables is not straight-forward because of the differences in how the debug info is distributed on darwin vs. elf targets. The darwin debug model assumes that the debug info (along with accelerator tables) will either remain in the .o files or it will be linked into a dsym bundle by a linker that knows how to merge these tables. In the elf world, all present linkers will simply concatenate these accelerator tables into the shared object. Since the tables are not self-terminating, this renders the tables unusable, as the debugger cannot pry the individual tables apart anymore. It might theoretically be possible to make the tables work with split dwarf, as that is somewhat similar to the apple .o model, but unfortunately right now the combination of -glldb and -gsplit-dwarf produces broken object files. Until these issues are resolved there is no point in emitting the apple tables for these targets. At best, it wastes space; at worst, it breaks compilation and prevents the user from getting other benefits of -glldb. Reviewers: probinson, aprantl, dblaikie Subscribers: emaste, dim, llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D41986 llvm-svn: 322633
* [SCEV] fix typoJaved Absar2018-01-171-1/+1
| | | | llvm-svn: 322629
* [ThinLTO] - Remove code duplication. NFC.George Rimar2018-01-171-22/+17
| | | | | | | Refactors 3 copies of isExpected. Splitted from D42107. llvm-svn: 322627
* Allow usage of X86-prefixes as separate instrs.Andrew V. Tischenko2018-01-171-0/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D42102 llvm-svn: 322623
* [MC] Fix -stack-size-section on ARMSean Eveson2018-01-171-2/+1
| | | | | | | | Change symbol values in the stack_size section from being 8 bytes, to being a target dependent size. Differential Revision: https://reviews.llvm.org/D42108 llvm-svn: 322619
* [X86] In LowerBUILD_VECTOR, rename ExtVT to EltVT so it makes sense.Craig Topper2018-01-171-7/+7
| | | | llvm-svn: 322616
* [X86] Remove duplicate lines from scheduler models. NFCCraig Topper2018-01-174-8/+0
| | | | llvm-svn: 322615
* [Support] Return an enum instead of an unsigned; NFC.George Burgess IV2018-01-171-2/+2
| | | | | | | | | | | | | | We seem to be (logically) returning ArchExtKinds here in all cases, so the return type should reflect that. The static_cast is necessary because `A.ID` is actually an `unsigned`, presumably since we use `decltype(A)` to represent extended attributes for both ARM and AArch64, which use distinct `ArchExtKinds`. We can't trivially make the same change for ARM, because one of the values it returns is the bitwise-or of two `ARM::ArchExtKind`s. llvm-svn: 322613
* Fix pretty printing the unspecified param of a variadic functionAaron Smith2018-01-171-0/+19
| | | | | | | | | | | | | | | | | | | | | | | Summary: - Fix a bug in PrettyBuiltinDumper that returns "void" as the name for an unspecified builtin type. Since the unspecified param of a variadic function is considered a builtin of unspecified type in PDBs, we set "..." for its name. - Provide a method to determine if a PDBSymbolFunc is variadic in PrettyFunctionDumper since PDBSymbolFunc::getArgument() doesn't return the last unspecified-type param. - Add a pretty-func-dumper.test to test pretty dumping of variadic functions. Reviewers: zturner, llvm-commits Reviewed By: zturner Differential Revision: https://reviews.llvm.org/D41801 llvm-svn: 322608
* [hwasan] Rename sized load/store callbacks to be consistent with ASan.Evgeniy Stepanov2018-01-161-1/+1
| | | | | | | | | | | | Summary: __hwasan_load is now __hwasan_loadN. Reviewers: kcc Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D42138 llvm-svn: 322601
* [X86][BTVER2] Fix scheduling of VCMPSD/VCMPSS instructionsSimon Pilgrim2018-01-161-2/+2
| | | | | | For some reason they don't have a trailing i like the packed equivalents. llvm-svn: 322600
* [CallSiteSplitting] Pass list of (BB, Conditions) pairs to splitCallSite.Florian Hahn2018-01-161-76/+71
| | | | | | | | | | | | | | | This removes some duplication from splitCallSite and makes it easier to add additional code dealing with each predecessor. It also allows us to split for more than 2 predecessors, although that is not enabled for now. Reviewers: junbuml, mcrosier, davidxl, davide Reviewed By: junbuml Differential Revision: https://reviews.llvm.org/D41858 llvm-svn: 322599
* [X86][BTVER2] Use instrs instead of instregex for low match counts (PR35955)Simon Pilgrim2018-01-161-30/+22
| | | | llvm-svn: 322598
* [X86][BTVER2] Use instrs instead of instregex for single use matches (PR35955)Simon Pilgrim2018-01-161-36/+33
| | | | llvm-svn: 322597
* Specify inline for isWhitespace in CommandLine.cppRui Ueyama2018-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Takuto Ikuta. In chromium's component build, there are many directive sections and commandline parsing takes much time. This patch is for speed up of lld in RelWithDebInfo build by forcing inline heavily called isWhitespace function. 10 times link perf stats of blink_core.dll changed like below. master: TotalSeconds: 9.8764878 TotalSeconds: 10.1455242 TotalSeconds: 10.075279 TotalSeconds: 10.3397347 TotalSeconds: 9.8361665 TotalSeconds: 9.9544441 TotalSeconds: 9.8960686 TotalSeconds: 9.8877865 TotalSeconds: 10.0551879 TotalSeconds: 10.0492254 Avg: 10.01159047 with this patch: TotalSeconds: 8.8696762 TotalSeconds: 9.1021585 TotalSeconds: 9.0233893 TotalSeconds: 9.1886175 TotalSeconds: 9.156954 TotalSeconds: 9.0978564 TotalSeconds: 9.1316824 TotalSeconds: 8.8354606 TotalSeconds: 9.2549431 TotalSeconds: 9.4473085 Avg: 9.11080465 llvm-svn: 322595
* [ExecutionEngine] Rename JITSymbol::isStrongDefinition to isStrong.Lang Hames2018-01-162-4/+4
| | | | | | For symmetry with isWeak, isCommon. llvm-svn: 322594
* [PPC] Add a new register XER aliased to CARRYGuozhi Wei2018-01-161-2/+6
| | | | | | | | | | When "xer" is specified as clobbered register in inline assembler, clang can accept it, but llvm simply ignore it when lowered to machine instructions. It may cause problems later in scheduler. This patch adds a new register XER aliased to CARRY, and adds it to register class CARRYRC. Now PPCTargetLowering::getRegForInlineAsmConstraint can return correct register number for inline asm constraint "{xer}", and scheduler behave correctly. Differential Revision: https://reviews.llvm.org/D41967 llvm-svn: 322591
* [CodeGen] Skip some instructions that shouldn't affect shrink-wrappingFrancis Visoiu Mistrih2018-01-161-5/+5
| | | | | | | | | | | r320606 checked for MI.isMetaInstruction which skips all DBG_VALUEs. This also skips IMPLICIT_DEFs and other instructions that may def / read a register. Differential Revision: https://reviews.llvm.org/D42119 llvm-svn: 322584
* [GlobalISel][TableGen] Add support for SDNodeXFormVolkan Keles2018-01-162-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds CustomRenderer which renders the matched operands to the specified instruction. Targets can enable the matching of SDNodeXForm by adding a definition that inherits from GICustomOperandRenderer and GISDNodeXFormEquiv as follows. def gi_imm8 : GICustomOperandRenderer<"renderImm8”>, GISDNodeXFormEquiv<imm8_xform>; Custom renderer functions should be of the form: void render(MachineInstrBuilder &MIB, const MachineInstr &I); Reviewers: dsanders, ab, rovka Reviewed By: dsanders Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet Differential Revision: https://reviews.llvm.org/D42012 llvm-svn: 322582
* [SLP] Fix for PR32164: Improve vectorization of reverse order of extract ↵Alexey Bataev2018-01-161-10/+17
| | | | | | | | | | | | | | operations. Summary: Sometimes vectorization of insertelement instructions with extractelement operands may produce an extra shuffle operation, if these operands are in the reverse order. Patch tries to improve this situation by the reordering of the operands to remove this extra shuffle operation. Reviewers: mkuper, hfinkel, RKSimon, spatel Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D33954 llvm-svn: 322579
* [X86][MMX] Accept UNDEF upper bits for MOVD GR32->MMXSimon Pilgrim2018-01-161-3/+4
| | | | llvm-svn: 322574
* [LiveDebugValues] recognize spilled reg killed in instruction after spillPetar Jovanovic2018-01-161-7/+30
| | | | | | | | | | | Current condition for spill instruction recognition in LiveDebugValues does not recognize case when register is spilled and killed in next instruction. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D41226 llvm-svn: 322554
* [X86][MMX] Improve MMX constant generationSimon Pilgrim2018-01-161-3/+12
| | | | | | Extend the MMX zero code to take any constant with zero'd upper 32-bits llvm-svn: 322553
* [DebugInfo] Unify dumping of address rangesJonas Devlieghere2018-01-164-12/+23
| | | | | | | | | | | | | | | Summary: This patch unifies the printing of address ranges as [0x0, 0x1). rdar://34822059 Reviewers: aprantl, dblaikie Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D42056 llvm-svn: 322543
* [CodeGen] Remove special case of printing subRegIdx from MachineInstr::printFrancis Visoiu Mistrih2018-01-161-3/+0
| | | | | | | Support in MachineOperand has been added in r320209. No need to special case this anymore. llvm-svn: 322542
* [CodeGen][NFC] Correct case for printSubRegIdxFrancis Visoiu Mistrih2018-01-163-3/+3
| | | | llvm-svn: 322541
* [BPF] Mark pseudo insn patterns as isCodeGenOnlyYonghong Song2018-01-161-2/+2
| | | | | | | | | | | | | | | | | | | | These pseudos are not supposed to be visible to user. This patch reduced the auto-generated instruction matcher. For example, the following words are removed from keyword list of LLVM BPF assembler. - MCK__35_, // '#' - MCK__COLON_, // ':' - MCK__63_, // '?' - MCK_ADJCALLSTACKDOWN, // 'ADJCALLSTACKDOWN' - MCK_ADJCALLSTACKUP, // 'ADJCALLSTACKUP' - MCK_PSEUDO, // 'PSEUDO' - MCK_Select, // 'Select' Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com> Acked-by: Yonghong Song <yhs@fb.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> llvm-svn: 322535
* [BPF] Teach DAG2DAG AND elimination about load intrinsicsYonghong Song2018-01-161-7/+31
| | | | | | | | | | | | | | | | | | As commented on the existing code: // The Reg operand should be a virtual register, which is defined // outside the current basic block. DAG combiner has done a pretty // good job in removing truncating inside a single basic block. However, when the Reg operand comes from bpf_load_[byte | half | word] intrinsics, the generic optimizer doesn't understand their results are zero extended, so these single basic block elimination opportunities were missed. Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com> Acked-by: Yonghong Song <yhs@fb.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> llvm-svn: 322534
* [SROA] fix assetion failureHiroshi Inoue2018-01-161-9/+4
| | | | | | | | | | | | | | This patch fixes the assertion failure in SROA reported in PR35657. PR35657 reports the assertion failure due to r319522 (splitting for non-whole-alloca slices), but this problem can happen even without r319522. The problem exists in a check for reusing an existing alloca when rewriting partitions. As the original comment said, we can reuse the existing alloca if the new alloca has the same type and offset with the existing one. But the code checks only type of the alloca and then check the offset using an assert. In a corner case with out-of-bounds access (e.g. @PR35657 function added in unit test), it is possible that the two allocas have the same type but different offsets. This patch makes the check of the offset in the if condition, and re-enables the splitting for non-whole-alloca slices. Differential Revision: https://reviews.llvm.org/D41981 llvm-svn: 322533
* [X86] Revisit the fix I made years ago to make 'xchgl %eax, %eax' not encode ↵Craig Topper2018-01-162-16/+8
| | | | | | | | | | using the 0x90 encoding in 64-bit mode. Prior to this we had a separate instruction and register class that excluded eax to prevent matching the instruction that would encode with 0x90. This patch changes this to just use an InstAlias to force xchgl %eax, %eax to use XCHG32rr instruction in 64-bit mode. This gets rid of the separate instruction and register class. llvm-svn: 322532
* [X86] Make 'xchgq %rax, %rax' an alias for the 0x90 nop encoding to match gas.Craig Topper2018-01-161-0/+4
| | | | | | Previously we encoded it as 0x48 0x90. llvm-svn: 322531
* Avoid Wparentheses warning.Simon Pilgrim2018-01-151-2/+2
| | | | llvm-svn: 322526
* [X86][MMX] Add support for MMX zero vector creationSimon Pilgrim2018-01-153-1/+26
| | | | | | | | | | As mentioned on PR35869, (and came up recently on D41517) we don't create a MMX zero register via the PXOR but instead perform a spill to stack from a XMM zero register. This patch adds support for direct MMX zero vector creation and should make it easier to add better constant vector creation in the future as well. Differential Revision: https://reviews.llvm.org/D41908 llvm-svn: 322525
* [X86][SSE] Add custom execution domain fixing for ↵Simon Pilgrim2018-01-152-3/+192
| | | | | | | | | | BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) Add support for custom execution domain fixing and implement support for BLENDPD/BLENDPS/PBLENDD/PBLENDW. Differential Revision: https://reviews.llvm.org/D42042 llvm-svn: 322524
* [X86] Use MVT::getVectorVT instead of EVT::getVectorVT when splitting ↵Craig Topper2018-01-151-2/+2
| | | | | | | | 256/512 bit build_vectors. NFC We must be creating a legal type here which means it can be an MVT. llvm-svn: 322512
* [X86] Generalize some code in LowerBUILD_VECTOR. NFCCraig Topper2018-01-151-4/+10
| | | | llvm-svn: 322511
* [X86] Remove unnecessary if statement from LowerBUILD_VECTOR. NFCICraig Topper2018-01-151-1/+1
| | | | | | We were checking for 128, 256, or 512 bit vectors, but those are the only types that can get here. llvm-svn: 322510
* [WebAssembly] Update README.txt.Dan Gohman2018-01-151-13/+41
| | | | | | | Describe more of the current status, mention Rust as another easy way to use this backend, and add more documentation links. llvm-svn: 322508
* [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32Stanislav Mekhanoshin2018-01-154-4/+19
| | | | | | Differential Revision: https://reviews.llvm.org/D41617 llvm-svn: 322500
* [Hexagon] Implement signed and unsigned multiply-high for vectorsKrzysztof Parzyszek2018-01-154-3/+166
| | | | llvm-svn: 322499
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