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* [X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics.Craig Topper2018-01-121-6/+6
| | | | | | While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
* [X86] Disable sldtq parsing in 64-bit mode.Craig Topper2018-01-121-2/+2
| | | | llvm-svn: 322353
* [X86] Disable movsq/stosq/scasqcmpsq/lodsq parsing in 64-bit mode.Craig Topper2018-01-121-5/+10
| | | | llvm-svn: 322352
* Instead of ELFFile<ELFT>::Type, use ELFT::Type. NFC.Rui Ueyama2018-01-121-1/+1
| | | | llvm-svn: 322346
* [RISCV] Pass MCSubtargetInfo to print methods.Ana Pazos2018-01-123-9/+23
| | | | | | | | | | | | | | | | Summary: This change allows checking for ISA extensions in print methods. Reviewers: asb, niosHD Reviewed By: asb, niosHD Subscribers: llvm-commits, niosHD, asb, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal Differential Revision: https://reviews.llvm.org/D41503 llvm-svn: 322345
* [WebAssembly] Don't allow functions to be named twiceSam Clegg2018-01-121-1/+6
| | | | | | | | The spec doesn't allow this. Differential Revision: https://reviews.llvm.org/D41974 llvm-svn: 322343
* [ORC] Add a stub ExecutionSession and VModuleKey type.Lang Hames2018-01-121-0/+6
| | | | | | | | | | ExecutionSession will represent a running JIT program. VModuleKey is a unique key assigned to each module added as part of an ExecutionSession. The Layer concept will be updated in future to require a VModuleKey when a module is added. llvm-svn: 322336
* Revert r322279 due to Skylake miscompile.David L. Jones2018-01-121-11/+0
| | | | | | | | | | | | Summary: This revision causes Skylake (and apparently, only Skylake) codegen to fail in certain cases. Details: https://bugs.llvm.org/show_bug.cgi?id=35918 Subscribers: sanjoy, llvm-commits Differential Revision: https://reviews.llvm.org/D41972 llvm-svn: 322335
* [WebAssembly] MC: Remove SetUsed argument when calling MCSymbol::isDefined et alSam Clegg2018-01-111-7/+7
| | | | | | | | | | | | | Summary: This argument (the isUsed flag) seems to only be relevant when parsing. Other calls sites such as these don't seem to ever use it. Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish Differential Revision: https://reviews.llvm.org/D41970 llvm-svn: 322332
* [InstSimplify] fold implied cmp with zero (PR35790)Sanjay Patel2018-01-111-0/+42
| | | | | | | | | This doesn't handle the more complicated case in the bug report yet: https://bugs.llvm.org/show_bug.cgi?id=35790 For that, we have to match / look through a cast. llvm-svn: 322327
* PeepholeOpt cleanup/refactor; NFCMatthias Braun2018-01-111-440/+370
| | | | | | | | | | | | | | | | | | - Less unnecessary use of `auto` - Add early `using RegSubRegPair(AndIdx) =` to avoid countless `TargetInstrInfo::` qualifications. - Use references instead of pointers where possible. - Remove unused parameters. - Rewrite the CopyRewriter class hierarchy: - Pull out uncoalescable copy rewriting functionality into PeepholeOptimizer class. - Use an abstract base class to make it clear that rewriters are independent. - Remove unnecessary \brief in doxygen comments. - Remove unused constructor and method from ValueTracker. - Replace UseAdvancedTracking of ValueTracker with DisableAdvCopyOpt use. llvm-svn: 322325
* [hwasan] Stack instrumentation.Evgeniy Stepanov2018-01-112-3/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Very basic stack instrumentation using tagged pointers. Tag for N'th alloca in a function is built as XOR of: * base tag for the function, which is just some bits of SP (poor man's random) * small constant which is a function of N. Allocas are aligned to 16 bytes. On every ReturnInst allocas are re-tagged to catch use-after-return. This implementation has a bunch of issues that will be taken care of later: 1. lifetime intrinsics referring to tagged pointers are not recognized in SDAG. This effectively disables stack coloring. 2. Generated code is quite inefficient. There is one extra instruction at each memory access that adds the base tag to the untagged alloca address. It would be better to keep tagged SP in a callee-saved register and address allocas as an offset of that XOR retag, but that needs better coordination between hwasan instrumentation pass and prologue/epilogue insertion. 3. Lifetime instrinsics are ignored and use-after-scope is not implemented. This would be harder to do than in ASan, because we need to use a differently tagged pointer depending on which lifetime.start / lifetime.end the current instruction is dominated / post-dominated. Reviewers: kcc, alekseyshl Subscribers: srhines, kubamracek, javed.absar, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D41602 llvm-svn: 322324
* PeepholeOptimizer: Fix for vregs without defsMatthias Braun2018-01-113-7/+32
| | | | | | | | | | The PeepholeOptimizer would fail for vregs without a definition. If this was caused by an undef operand abort to keep the code simple (so we don't need to add logic everywhere to replicate the undef flag). Differential Revision: https://reviews.llvm.org/D40763 llvm-svn: 322319
* Make internal/private GVs implicitly dso_local.Rafael Espindola2018-01-116-9/+25
| | | | | | | | | | | | | | | | While updating clang tests for having clang set dso_local I noticed that: - There are *a lot* of tests to update. - Many of the updates are redundant. They are redundant because a GV is "obviously dso_local". This patch starts formalizing that a bit by requiring that internal and private GVs be dso_local too. Since they all are, we don't have to print dso_local to the textual representation, making it a bit more compact and easier to read. llvm-svn: 322317
* Tighten up DIFile verifier for checksumsPaul Robinson2018-01-111-2/+18
| | | | | | Differential Revision: https://reviews.llvm.org/D41965 llvm-svn: 322314
* PeepholeOptimizer: Do not form PHI with subreg argumentsMatthias Braun2018-01-111-22/+19
| | | | | | | | | | | | | | | | | | | | | When replacing a PHI the PeepholeOptimizer currently takes the register class of the register at the first operand. This however is not correct if this argument has a subregister index. As there is currently no API to query the register class resulting from applying a subregister index to all registers in a class, we can only abort in these cases and not perform the transformation. This changes findNextSource() to require the end of all copy chains to not use a subregister if there is any PHI in the chain. I had to rewrite the overly complicated inner loop there to have a good place to insert the new check. This fixes https://llvm.org/PR33071 (aka rdar://32262041) Differential Revision: https://reviews.llvm.org/D40758 llvm-svn: 322313
* [arm] Implement Target Operand Flag MIR serialization.Evgeniy Stepanov2018-01-112-0/+35
| | | | | | | | | | Reviewers: efriedma, pcc Subscribers: aemerson, javed.absar, kristof.beyls, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D39975 llvm-svn: 322312
* [Sink] Really really fix predicate in legality checkFiona Glaser2018-01-111-1/+1
| | | | | | | | | | | LoadInst isn't enough; we need to include intrinsics that perform loads too. All side-effecting intrinsics and such are already covered by the isSafe check, so we just need to care about things that read from memory. D41960, originally from D33179. llvm-svn: 322311
* [WebAssemlby] MC: Don't write COMDAT symbols as global importsSam Clegg2018-01-112-2/+5
| | | | | | | | This was causing undefined references at link time in lld. Differential Revision: https://reviews.llvm.org/D41959 llvm-svn: 322309
* [X86] Legalize 128/256 gathers/scatters on KNL by using widening rather than ↵Craig Topper2018-01-111-75/+38
| | | | | | | | sign extending the index. We can just widen the vectors with undef and zero extend the mask. llvm-svn: 322308
* dag-combine: Transfer debug information when folding (zext (truncate x))Adrian Prantl2018-01-111-1/+4
| | | | | | | | | | | -> (zext (truncate x)) This patch adds debug info support to the dagcombine rule (zext (truncate x)) -> (zext (truncate x)). Differential Revision: https://reviews.llvm.org/D41924 llvm-svn: 322304
* [Hexagon] Fix building 64-bit vector from constant valuesKrzysztof Parzyszek2018-01-111-1/+1
| | | | | | The constants were aggregated in a reverse order. llvm-svn: 322303
* [Hexagon] Cast elements to correct type when creating constant vectorKrzysztof Parzyszek2018-01-111-1/+2
| | | | llvm-svn: 322301
* DAGCombine: Let truncates negate extension through extract-subvectorZvi Rackover2018-01-111-0/+16
| | | | | | | | | | | | | | | | | | | | | | Summary: Fold cases such as: (v8i8 truncate (v8i32 extract_subvector (v16i32 sext (v16i8 V), Idx))) -> (v8i8 extract_subvector (v16i8 V), Idx) This can be generalized to cases where the truncate and extend do not fully cancel each other out, but it may require querying the target about profitability. Reviewers: RKSimon, craig.topper, spatel, efriedma Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41927 llvm-svn: 322300
* [Hexagon] Impose limits on container sizes in HexagonGenInsertKrzysztof Parzyszek2018-01-111-3/+20
| | | | | | | With over 300k virtual registers, the size of the data exceeded 12GB. Impose limits on how much information is collected. llvm-svn: 322299
* [Hexagon] Use SetVector when queuing nodes to scan in selectVectorConstantsKrzysztof Parzyszek2018-01-111-3/+4
| | | | llvm-svn: 322298
* X86: Refactor type-splitting to target-legal size vector to a helper functionZvi Rackover2018-01-111-32/+58
| | | | | | | | | | | | | | Summary: This is a preparatory step for D41811: refactoring code for breaking vector operands of binary operation to legal-types. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41925 llvm-svn: 322296
* [AArch64] Remove Unsupported = 1 flag for the WriteAtomic WriteRes.Joel Jones2018-01-111-1/+1
| | | | | | | | | | | | | In practice, this patch has no effect on scheduling. There is no test case as there already exists a comprehensive test case for LSE Atomics. Patch by Stefan Teleman Differential Revision: https://reviews.llvm.org/D40694 llvm-svn: 322291
* [InstCombine] Apply the fix from r322284 for sin / cos -> tan tooBenjamin Kramer2018-01-111-2/+3
| | | | llvm-svn: 322285
* [InstCombine] For cos/sin -> tan copy attributes from cos instead of theBenjamin Kramer2018-01-111-2/+3
| | | | | | | | | | | parent function Ideally we should merge the attributes from the functions somehow, but this is obviously an improvement over taking random attributes from the caller which will trip up the verifier if they're nonsensical for an unary intrinsic call. llvm-svn: 322284
* [ValueTracking] recognize min/max-of-min/max with notted ops (PR35875)Sanjay Patel2018-01-111-12/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was originally planned as the fix for: https://bugs.llvm.org/show_bug.cgi?id=35834 ...but simpler transforms handled that case, so I implemented a lesser solution. It turns out we need to handle the case with 'not' ops too because the real code example that we are trying to solve: https://bugs.llvm.org/show_bug.cgi?id=35875 ...has extra uses of the intermediate values, so we can't rely on smaller canonicalizations to get us to the goal. As with rL321672, I've tried to show every possibility in the codegen tests because that's the simplest way to prove we're doing the right thing in the wide variety of permutations of this pattern. We can also show an InstCombine win because we added a fold for this case in: rL321998 / D41603 An Alive proof for one variant of the pattern to show that the InstCombine and codegen results are correct: https://rise4fun.com/Alive/vd1 Name: min3_nots %nx = xor i8 %x, -1 %ny = xor i8 %y, -1 %nz = xor i8 %z, -1 %cmpxz = icmp slt i8 %nx, %nz %minxz = select i1 %cmpxz, i8 %nx, i8 %nz %cmpyz = icmp slt i8 %ny, %nz %minyz = select i1 %cmpyz, i8 %ny, i8 %nz %cmpyx = icmp slt i8 %y, %x %r = select i1 %cmpyx, i8 %minxz, i8 %minyz => %cmpxyz = icmp slt i8 %minxz, %ny %r = select i1 %cmpxyz, i8 %minxz, i8 %ny Name: min3_nots_alt %nx = xor i8 %x, -1 %ny = xor i8 %y, -1 %nz = xor i8 %z, -1 %cmpxz = icmp slt i8 %nx, %nz %minxz = select i1 %cmpxz, i8 %nx, i8 %nz %cmpyz = icmp slt i8 %ny, %nz %minyz = select i1 %cmpyz, i8 %ny, i8 %nz %cmpyx = icmp slt i8 %y, %x %r = select i1 %cmpyx, i8 %minxz, i8 %minyz => %xz = icmp sgt i8 %x, %z %maxxz = select i1 %xz, i8 %x, i8 %z %xyz = icmp sgt i8 %maxxz, %y %maxxyz = select i1 %xyz, i8 %maxxz, i8 %y %r = xor i8 %maxxyz, -1 llvm-svn: 322283
* [X86][SSE] Add ISD::VECTOR_SHUFFLE to faux shuffle decodingSimon Pilgrim2018-01-111-0/+11
| | | | | | Primarily, this allows us to use the aggressive extraction mechanisms in combineExtractWithShuffle earlier and make use of UNDEF elements that may be lost during lowering. llvm-svn: 322279
* [VectorLegalizer] Remove broken code in ExpandStore.Jonas Paulsson2018-01-111-28/+0
| | | | | | | | | | | | | | The code that is supposed to "Round odd types to the next pow of two" seems broken and as well completely unused (untested). It also seems that ExpandStore really shouldn't ever change the memory VT, which this in fact does. As a first step in fixing the broken handling of vector stores (of irregular types, e.g. an i1 vector), this code is removed. For discussion, see https://bugs.llvm.org/show_bug.cgi?id=35520. Review: Eli Friedman llvm-svn: 322275
* X86: Fix LowerBUILD_VECTORAsVariablePermute for case Src is smaller than IndicesZvi Rackover2018-01-111-0/+5
| | | | | | | | | | | | | | | | | | Summary: As RKSimon suggested in pr35820, in the case that Src is smaller in bit-size than Indices, need to widen Src to avoid type mismatch. Fixes pr35820 Reviewers: RKSimon, craig.topper Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41865 llvm-svn: 322272
* [RISCV] Reserve an emergency spill slot for the register scavenger when ↵Alex Bradbury2018-01-112-0/+22
| | | | | | | | | | | necessary Although the register scavenger can often find a spare register, an emergency spill slot is needed to guarantee success. Reserve this slot in cases where the function is known to have a large stack (meaning the scavenger may be needed when forming stack addresses). llvm-svn: 322269
* Implementation of X86Operand::print.Andrew V. Tischenko2018-01-111-2/+48
| | | | | | Differential Revision: https://reviews.llvm.org/D41610 llvm-svn: 322267
* [Mips] Handle one byte unsupported relocationsStefan Maksimovic2018-01-111-0/+2
| | | | | | | | | Fail gracefully instead of crashing upon encountering this type of relocation. Differential revision: https://reviews.llvm.org/D41857 llvm-svn: 322266
* [X86] Fix unused variable in release builds.Craig Topper2018-01-111-2/+2
| | | | llvm-svn: 322262
* [CodeView] Fix the type for a variadic argumentAaron Smith2018-01-111-0/+12
| | | | | | | | | | | | | | Summary: - MSVC uses the none type for a variadic argument in CodeView - Add a unit test Reviewers: zturner, llvm-commits Reviewed By: zturner Differential Revision: https://reviews.llvm.org/D41931 llvm-svn: 322257
* [InstCombine] Missed optimization in math expression: sin(x) / cos(x) => tan(x)Dmitry Venikov2018-01-113-15/+48
| | | | | | | | | | | | | | Summary: This patch enables folding sin(x) / cos(x) -> tan(x), cos(x) / sin(x) -> 1 / tan(x) under -ffast-math flag Reviewers: hfinkel, spatel Reviewed By: spatel Subscribers: andrew.w.kaylor, efriedma, scanon, llvm-commits Differential Revision: https://reviews.llvm.org/D41286 llvm-svn: 322255
* [X86] Optimize v2i32/v2f32 scatters.Craig Topper2018-01-112-30/+58
| | | | | | | | If the index is v2i64 we can use the scatter instruction that has v4i32/v4f32 data register, v2i64 index, and v2i1 mask. Similar was already done for gather. Implement custom widening for v2i32 data to remove the code that reverses type legalization during lowering. llvm-svn: 322254
* [DWARF][NFC] Overload AsmPrinter::emitDwarfStringOffsets() to take a ↵Wolfgang Pieb2018-01-111-3/+4
| | | | | | | | | | DwarfStringPoolEntry record. Differential Revision: https://reviews.llvm.org/D41920 llvm-svn: 322250
* [NFC] Commit to mention that r322248 is actually made by AndrewScheideckerMarcello Maggioni2018-01-111-1/+1
| | | | llvm-svn: 322249
* [SimplifyCFG] Add cut-off for InitializeUniqueCases.Marcello Maggioni2018-01-111-13/+25
| | | | | | | | | | | | | The function can take a significant amount of time on some complicated test cases, but for the currently only use of the function we can stop the initialization much earlier when we find out we are going to discard the result anyway in the caller of the function. Adding configurable cut-off points so that we avoid wasting time. NFCI. llvm-svn: 322248
* Revert "AArch64: Fix emergency spillslot being out of reach for large ↵Matthias Braun2018-01-108-57/+11
| | | | | | | | | | | | callframes" Revert for now as the testcase is hitting a pre-existing verifier error that manifest as a failure when expensive checks are enabled (or -verify-machineinstrs) is used. This reverts commit r322200. llvm-svn: 322231
* LiveRangeEdit: Inline markDeadRemat() into only user; NFCMatthias Braun2018-01-101-1/+1
| | | | | | | This function was only called from a single place in which we didn't even need the `if (DeadRemats)` check. llvm-svn: 322230
* [X86] Move HasNOPL to a subtarget feature bit. Plumb MCSubtargetInfo through ↵Craig Topper2018-01-104-57/+79
| | | | | | | | | | the MCAsmBackend constructor After D41349, we can no get a MCSubtargetInfo into the MCAsmBackend constructor. This allows us to get NOPL from a subtarget feature rather than a CPU name blacklist. Differential Revision: https://reviews.llvm.org/D41721 llvm-svn: 322227
* LiveRangeEdit: Simplify code; NFCMatthias Braun2018-01-101-12/+14
| | | | | | | | Simplify the code slightly: Instead of creating empty subranges in one case and immediately removing them, do not create them in the first place. llvm-svn: 322226
* [RISCV] Implement support for the BranchRelaxation passAlex Bradbury2018-01-105-9/+133
| | | | | | | | | Branch relaxation is needed to support branch displacements that overflow the instruction's immediate field. Differential Revision: https://reviews.llvm.org/D40830 llvm-svn: 322224
* TargetLoweringBase: The ios simulator has no bzero function.Matthias Braun2018-01-101-3/+12
| | | | | | | | Make sure I really get back to the beahvior before my rewrite in r321035 which turned out not to be completely NFC as I changed the behavior for the ios simulator environment. llvm-svn: 322223
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