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* Cosmetic change, better reflects actual valuesNate Begeman2005-12-011-6/+5
| | | | llvm-svn: 24562
* Fix a regression caused by a patch earlier todayChris Lattner2005-12-011-1/+2
| | | | llvm-svn: 24561
* Flags where I think I need them, quick, before the nightly tester startsAndrew Lenharth2005-12-011-23/+42
| | | | llvm-svn: 24560
* Proper support for shifts with register shift value.Evan Cheng2005-12-012-44/+24
| | | | llvm-svn: 24559
* Use a getCopyToReg() variant to generate a flaggy CopyToReg node.Evan Cheng2005-12-011-8/+2
| | | | llvm-svn: 24558
* SelectNodeTo now returns its result, we must pay attention to it.Chris Lattner2005-11-301-40/+29
| | | | llvm-svn: 24552
* Pay attn to the node returned by SelectNodeToChris Lattner2005-11-301-37/+28
| | | | llvm-svn: 24551
* SelectNodeTo now returns its result, we must pay attention to it.Chris Lattner2005-11-301-20/+18
| | | | llvm-svn: 24550
* SelectNodeTo now returns N. Use it instead of return N directly.Chris Lattner2005-11-301-108/+81
| | | | llvm-svn: 24549
* Make SelectNodeTo return NChris Lattner2005-11-301-35/+49
| | | | llvm-svn: 24548
* Fix Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.llChris Lattner2005-11-301-2/+6
| | | | llvm-svn: 24547
* Fix a bug where we didn't realize that vaarg reads memory. This fixesChris Lattner2005-11-301-0/+7
| | | | | | Transforms/DeadStoreElimination/2005-11-30-vaarg.ll llvm-svn: 24545
* Fix a typo in my latest changeNate Begeman2005-11-301-2/+2
| | | | llvm-svn: 24542
* No longer track value types for asm printer operands, and remove them asNate Begeman2005-11-308-89/+92
| | | | | | | an argument to every operand printing function. Requires some slight tweaks to x86, the only user. llvm-svn: 24541
* CALLSEQ_START/END nodes don't get memoized, do not add them in whenChris Lattner2005-11-301-0/+4
| | | | | | replaceAllUses'ing. llvm-svn: 24539
* remove redundant codeAndrew Lenharth2005-11-301-14/+2
| | | | llvm-svn: 24538
* At long last, you can say that f32 isn't supported for setccAndrew Lenharth2005-11-301-1/+28
| | | | llvm-svn: 24537
* Make typesafe that which isn't: FCMOVxxAndrew Lenharth2005-11-304-26/+52
| | | | llvm-svn: 24536
* FPSelect and more custom loweringAndrew Lenharth2005-11-305-25/+69
| | | | llvm-svn: 24535
* First chunk of actually generating vector code for packed types. TheseNate Begeman2005-11-302-13/+63
| | | | | | | | | | | | | | | | | | | | | | | changes allow us to generate the following code: _foo: li r2, 0 lvx v0, r2, r3 vaddfp v0, v0, v0 stvx v0, r2, r3 blr for this llvm: void %foo(<4 x float>* %a) { entry: %tmp1 = load <4 x float>* %a %tmp2 = add <4 x float> %tmp1, %tmp1 store <4 x float> %tmp2, <4 x float>* %a ret void } llvm-svn: 24534
* All sorts of stuff.Andrew Lenharth2005-11-307-32/+203
| | | | | | | | | | | | | Getting in on the custom lowering thing, yay evilness with fp setcc, yuck trivial int select, hmmm in memory args for functions, yay DIV and REM, always handy. They should be custom lowered though. Lots more stuff compiles now (go go single source!). Of course, none of it probably works, but that is what the nightly tester can find out :) llvm-svn: 24533
* add support for custom lowering SINT_TO_FPAndrew Lenharth2005-11-301-0/+13
| | | | llvm-svn: 24531
* Fix a problem with llvm-ranlib that (on some platforms) caused the archiveReid Spencer2005-11-303-36/+102
| | | | | | | | | | file to become corrupted due to interactions between mmap'd memory segments and file descriptors closing. The problem is completely avoiding by using a third temporary file. Patch provided by Evan Jones llvm-svn: 24527
* Fix a bug in a recent patch that broke shiftsChris Lattner2005-11-301-3/+3
| | | | llvm-svn: 24526
* Added support to STORE and shifts to DAG to DAG isel.Evan Cheng2005-11-301-8/+88
| | | | llvm-svn: 24525
* Fixed a bug introduced by my last commit: TargetGlobalValues should key onEvan Cheng2005-11-301-7/+13
| | | | | | GlobalValue * and index pair. Update getGlobalAddress() for symmetry. llvm-svn: 24524
* Added an index field to GlobalAddressSDNode so it can represent X+12, etc.Evan Cheng2005-11-303-3/+23
| | | | llvm-svn: 24523
* Fixed a minor bug: - -offset != offset iff offset == MININTEvan Cheng2005-11-301-1/+1
| | | | llvm-svn: 24522
* Represent the encoding of the SPR instructions as they actually are, soNate Begeman2005-11-292-8/+18
| | | | | | | that we can use the correct SPR numbers in the InstrInfo.td file. This is necessary to support VRsave. llvm-svn: 24521
* Add more X86 ISel patterns.Evan Cheng2005-11-291-407/+463
| | | | llvm-svn: 24520
* Hook up one type, v4f32, to the VR RegisterClass for now.Nate Begeman2005-11-291-0/+6
| | | | llvm-svn: 24517
* Add the remainder of the AltiVec 4 x float instructions. FurtherNate Begeman2005-11-292-14/+61
| | | | | | | enhancements will be necessary to teach the code generator that since there is no fmul, it will have to do vmaddfp, adding +0.0. llvm-svn: 24516
* Add support for a new STRING and LOCATION node for line number support, patchChris Lattner2005-11-294-2/+113
| | | | | | contributed by Daniel Berlin, with a few cleanups here and there by me. llvm-svn: 24515
* No targets support line number info yet.Chris Lattner2005-11-294-0/+12
| | | | llvm-svn: 24513
* Add the majority of the vector machien value types we expect to support,Nate Begeman2005-11-295-7/+19
| | | | | | | and make a few changes to the legalization machinery to support more than 16 types. llvm-svn: 24511
* Fixed a comment bug:Evan Cheng2005-11-291-1/+1
| | | | | | createPPCPatternInstructionSelector -> createPPCISelPattern llvm-svn: 24510
* refix typoChris Lattner2005-11-291-1/+1
| | | | llvm-svn: 24505
* don't say this is i128, because it isn't yet. Hopefully nate will changeChris Lattner2005-11-291-1/+1
| | | | | | | this to be something sane, but in the mean time it is unused, so safe to make something bogus. llvm-svn: 24504
* revert my change for the time being, which broke the buildChris Lattner2005-11-291-1/+1
| | | | llvm-svn: 24503
* fix a typo :)Chris Lattner2005-11-281-1/+1
| | | | llvm-svn: 24501
* a few more comments on the interfaces and functionsAndrew Lenharth2005-11-281-3/+20
| | | | llvm-svn: 24500
* Added documented rsprofiler interface. Also remove new profiler passes, theAndrew Lenharth2005-11-283-135/+63
| | | | | | old ones have been updated to implement the interface. llvm-svn: 24499
* Fix VC++ warning.Jeff Cohen2005-11-281-0/+1
| | | | llvm-svn: 24496
* Add a missed optimizationChris Lattner2005-11-281-0/+9
| | | | llvm-svn: 24495
* Random sampling (aka Arnold and Ryder) profiling. This is still ↵Andrew Lenharth2005-11-282-0/+730
| | | | | | | | | | | | | | | | | preliminary, but it works on spec on x86 and alpha. The idea is to allow profiling passes to remember what profiling they inserted, then a random sampling framework is inserted which consists of duplicated basic blocks (without profiling), such that at each backedge in the program and entry into every function, the framework chooses whether to use the instrumented code or the instrumentation free code. The goal of such a framework is to make it reasonably cheap to do random sampling of very expensive profiling products (such as load-value profiling). The code is organized into 3 parts (2 passes) 1) a linked set of profiling passes, which implement an analysis group (linked, like alias analysis are). These insert profiling into the program, and remember what they inserted, so that at a later time they can be queried about any instruction. 2) a pass that handles inserting the random sampling framework. This also has options to control how random samples are choosen. Currently implemented are Global counters, register allocated global counters, and read cycle counter (see? there was a reason for it). The profiling passes are almost identical to the existing ones (block, function, and null profiling is supported right now), and they are valid passes without the sampling framework (hence the existing passes can be unified with the new ones, not done yet). Some things are a bit ugly still, but that should be fixed up soon enough. Other todo? making the counter values not "magic 2^16 -1" values, but dynamically choosable. llvm-svn: 24493
* Small tweaks noticed while on the plane.Nate Begeman2005-11-263-5/+10
| | | | llvm-svn: 24492
* since reg2mem requires it, might as well mention that it preserves itAndrew Lenharth2005-11-251-0/+1
| | | | llvm-svn: 24491
* add support for dynamic_stackalloc to the dag isel (thanks andrew ;)Duraid Madina2005-11-251-3/+31
| | | | | | next up: support argument passing in memory, not just registers llvm-svn: 24490
* Some first bits of AltiVec stuff: Instruction Formats, Encodings, andNate Begeman2005-11-233-1/+123
| | | | | | | | | | Registers. Apologies to Jim if the scheduling info so far isn't accurate. There's a few more things like VRsave support that need to be finished up in my local tree before I can commit code that Does The Right Thing for turning 4 x float into the various altivec packed float instructions. llvm-svn: 24489
* Reg2Mem is something a pass may depend on, so allow thatAndrew Lenharth2005-11-221-0/+1
| | | | llvm-svn: 24488
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