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* fConversion: Attempt #2 at fixing the MSVC build.Benjamin Kramer2013-10-111-2/+2
| | | | llvm-svn: 192492
* IfConversion: Try to unbreak the MSVC build.Benjamin Kramer2013-10-111-1/+1
| | | | llvm-svn: 192487
* Mips: Disassemble sign-extended 64 bit immediates properly.Benjamin Kramer2013-10-111-1/+3
| | | | | | This doesn't change the meaning of the output, but makes look right. PR17539. llvm-svn: 192483
* Remove kill flags after if conversion if necessaryMatthias Braun2013-10-111-66/+89
| | | | | | | | | | | | | | | | | | | When if converting something like: true: ... = R0<kill> false: ... = R0<kill> then the instructions of the true block must not have a <kill> flag anymore, as the instruction of the false block follow and do still read the R0 value. Specifically this patch determines the set of register live-in in the false block (possibly after simulating the liveness changes of the duplicated instructions). Each of these live-in registers mustn't be killed. llvm-svn: 192482
* [DAGCombiner] Reapply load slicing (192471) with a test that explicitly set ↵Quentin Colombet2013-10-111-2/+574
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sse4.2 support. This should fix the buildbots. Original commit message: [DAGCombiner] Slice a big load in two loads when the element are next to each other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> llvm-svn: 192476
* [DAGCombiner] Revert load slicing (r192471), until I figure out why it fails ↵Quentin Colombet2013-10-111-574/+2
| | | | | | on ubuntu. llvm-svn: 192474
* [DAGCombiner] Slice a big load in two loads when the element are next to eachQuentin Colombet2013-10-111-2/+574
| | | | | | | | | | | | | | | | | | | | | | | | other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> llvm-svn: 192471
* Better info when debugging vectorizerRenato Golin2013-10-111-6/+5
| | | | llvm-svn: 192460
* [ARM] Fix FP ABI attributes with no VFP enabled.Amara Emerson2013-10-111-14/+12
| | | | llvm-svn: 192458
* fix typo in commentMatthias Braun2013-10-111-1/+1
| | | | llvm-svn: 192455
* This reverts 192447 because of compiler warning generated on darwin build.Matheus Almeida2013-10-113-174/+14
| | | | llvm-svn: 192451
* This reverts r192449 because of compiler warning generated on darwin build.Matheus Almeida2013-10-112-109/+31
| | | | llvm-svn: 192450
* [mips][msa] Direct Object Emission for the majority of the ELM instructions.Matheus Almeida2013-10-112-31/+109
| | | | llvm-svn: 192449
* [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.Matheus Almeida2013-10-113-14/+174
| | | | | | | | INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192447
* [NVPTX] Switch from StrongPHIElimination to PHIElimination in ↵Justin Holewinski2013-10-111-2/+22
| | | | | | | | NVPTXTargetMachine, and add some missing optimization passes to addOptimizedRegAlloc Fixes PR17529 llvm-svn: 192445
* Make AsmPrinter::emitImplicitDef a virtual method so targets can emit custom ↵Justin Holewinski2013-10-113-20/+41
| | | | | | | | | | | | | comments for implicit defs For NVPTX, this fixes a crash where the emitImplicitDef implementation was expecting physical registers, while NVPTX uses virtual registers (with a couple of exceptions). Now, the implicit def comment will be emitted as a true PTX register name. Other targets can use this to customize the output of implicit def comments. Fixes PR17519 llvm-svn: 192444
* [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from ↵Daniel Sanders2013-10-112-16/+33
| | | | | | normal IR (i.e. not intrinsics) llvm-svn: 192438
* [mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not ↵Daniel Sanders2013-10-112-4/+11
| | | | | | intrinsics) llvm-svn: 192435
* XCore target fix bug in emitArrayBound() causing segmentation faultRobert Lytton2013-10-111-6/+5
| | | | llvm-svn: 192434
* XCore target does not emit '.hidden' or '.protected' attributesRobert Lytton2013-10-111-0/+4
| | | | llvm-svn: 192433
* XCore target: fix bug in XCoreLowerThreadLocal.cppRobert Lytton2013-10-111-10/+21
| | | | | | | | | When a ConstantExpr which uses a thread local is part of a PHI node instruction, the insruction that replaces the ConstantExpr must be inserted in the predecessor block, in front of the terminator instruction. If the predecessor block has multiple successors, the edge is first split. llvm-svn: 192432
* XCore target: add XCoreTargetLowering::isZExtFree()Robert Lytton2013-10-112-0/+22
| | | | llvm-svn: 192431
* [mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not ↵Daniel Sanders2013-10-112-4/+7
| | | | | | intrinsics) llvm-svn: 192430
* [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] ↵Daniel Sanders2013-10-112-12/+31
| | | | | | from normal IR (i.e. not intrinsics) llvm-svn: 192429
* LiveRangeCalc.h: Update a description corresponding to r192396. ↵NAKAMURA Takumi2013-10-111-1/+1
| | | | | | [-Wdocumentation] llvm-svn: 192421
* Implement aarch64 neon instruction set AdvSIMD (copy).Kevin Qin2013-10-113-56/+464
| | | | llvm-svn: 192410
* Fix typoMatt Arsenault2013-10-101-2/+2
| | | | llvm-svn: 192406
* Print register in LiveInterval::print()Matthias Braun2013-10-106-23/+23
| | | | llvm-svn: 192398
* Represent RegUnit liveness with LiveRange instanceMatthias Braun2013-10-1011-113/+116
| | | | | | | Previously LiveInterval has been used, but having a spill weight and register number is unnecessary for a register unit. llvm-svn: 192397
* Work on LiveRange instead of LiveInterval where possibleMatthias Braun2013-10-105-64/+58
| | | | | | | Also change some pointer arguments to references at some places where 0-pointers are not allowed. llvm-svn: 192396
* Change MachineVerifier to work on LiveRange + LiveIntervalMatthias Braun2013-10-101-92/+117
| | | | llvm-svn: 192395
* Pass LiveQueryResult by valueMatthias Braun2013-10-109-21/+24
| | | | | | | This makes the API a bit more natural to use and makes it easier to make LiveRanges implementation details private. llvm-svn: 192394
* Refactor LiveInterval: introduce new LiveRange classMatthias Braun2013-10-102-116/+109
| | | | | | | | | | LiveRange just manages a list of segments and a list of value numbers now as LiveInterval did previously, but without having details like spill weight or a fixed register number. LiveInterval is now a subclass of LiveRange and simply adds the spill weight and the register number. llvm-svn: 192393
* Rename LiveRange to LiveInterval::SegmentMatthias Braun2013-10-1013-240/+242
| | | | | | | | The Segment struct contains a single interval; multiple instances of this struct are used to construct a live range, but the struct is not a live range by itself. llvm-svn: 192392
* Rename parameter: defined regs are not incoming.Matthias Braun2013-10-101-15/+15
| | | | llvm-svn: 192391
* Use getPointerSizeInBits() rather than 8 * getPointerSize()Matt Arsenault2013-10-101-2/+3
| | | | llvm-svn: 192386
* Debug Info: In DIBuilder, the context field of subprogram is updated to useManman Ren2013-10-104-9/+32
| | | | | | | | DIScopeRef. A paired commit at clang is required due to changes to DIBuilder. llvm-svn: 192378
* R600: Fix trunc i64 to i32 on SIMatt Arsenault2013-10-101-0/+5
| | | | llvm-svn: 192375
* R600/SI: Implement SIInstrInfo::verifyInstruction() for VOP*Tom Stellard2013-10-105-4/+142
| | | | | | | The function is used by the machine verifier and checks that VOP* instructions have legal operands. llvm-svn: 192367
* R600/SI: Define a separate MIMG instruction for each possible output value typeTom Stellard2013-10-105-35/+90
| | | | | | | | | | | | | During instruction selection, we rewrite the destination register class for MIMG instructions based on their writemasks. This creates machine verifier errors since the new register class does not match the register class in the MIMG instruction definition. We can avoid this by defining different MIMG instructions for each possible destination type and then switching to the correct instruction when we change the register class. llvm-svn: 192365
* R600/SI: Mark the EXEC register as reservedTom Stellard2013-10-101-0/+1
| | | | | | | | This prevents the machine verifier from complaining about uses of an undefined physical register. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192364
* R600: Use StructurizeCFGPass for non SI targetsTom Stellard2013-10-106-2/+18
| | | | | | | | | | | | | | StructurizeCFG pass allows to make complex cfg reducible ; it allows a lot of shader from shadertoy (which exhibits complex control flow constructs) to works correctly with respect to CFG handling (and allow us to detect potential bug in other part of the backend). We provide a cmd line argument to disable the pass for debug purpose. Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 192363
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-1011-2/+914
| | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). llvm-svn: 192361
* Revert "Implement AArch64 vector load/store multiple N-element structure ↵Rafael Espindola2013-10-1011-895/+2
| | | | | | | | class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." This reverts commit r192352. It broke the build. llvm-svn: 192354
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-1011-2/+895
| | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). llvm-svn: 192352
* ARM: Put isV8EligibleForIT into the llvm namespace. While there make it inline.Benjamin Kramer2013-10-101-2/+4
| | | | llvm-svn: 192350
* ARM: correct liveness flags during ARMLoadStoreOptTim Northover2013-10-101-0/+77
| | | | | | | | | | | | | | | | | | | | | | When we had a sequence like: s1 = VLDRS [r0, 1], Q0<imp-def> s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def> s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def> s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def> we were gathering the {s0, s1} loads below the s3 load. This is fine, but confused the verifier since now the s3 load had Q0<imp-use> with no definition above it. This should mark such uses <undef> as well. The liveness structure at the beginning and end of the block is unaffected, and the true sN definitions should prevent any dodgy reorderings being introduced elsewhere. rdar://problem/15124449 llvm-svn: 192344
* Allow non-AVX form of pmovmskb to take a GR64 operand.Craig Topper2013-10-101-0/+2
| | | | llvm-svn: 192341
* Remove duplicate instructions.Craig Topper2013-10-101-16/+0
| | | | llvm-svn: 192340
* [mips] Do not generate INS/EXT nodes if target does not have support forAkira Hatanaka2013-10-092-14/+19
| | | | | | ins/ext. llvm-svn: 192330
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