summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* Fix an ancient bug in removeCopyByCommutingDef().Jakob Stoklund Olesen2012-05-191-2/+5
| | | | | | | | | | | | | | | Before rewriting uses of one value in A to register B, check that there are no tied uses. That would require multiple A values to be rewritten. This bug can't bite in the current version of the code for a fairly subtle reason: A tied use would have caused 2-addr to insert a copy before the use. If the copy has been coalesced, it will be found by the same loop changed by this patch, and the optimization is aborted. This was exposed by 400.perlbench and lua after applying a patch that deletes joined copies aggressively. llvm-svn: 157130
* On Haswell, perfer storing YMM registers using a single instruction.Nadav Rotem2012-05-191-5/+4
| | | | llvm-svn: 157129
* Add support for additional in-reg vbroadcast patternsNadav Rotem2012-05-191-3/+9
| | | | llvm-svn: 157127
* Collect inflatable virtual registers on the fly.Jakob Stoklund Olesen2012-05-191-16/+11
| | | | | | | There is no reason to defer the collection of virtual registers whose register class may be replaced with a larger class. llvm-svn: 157125
* Move CallbackVHs dtor inline, it can be devirtualized in many cases. Move ↵Benjamin Kramer2012-05-191-3/+6
| | | | | | the other virtual methods out of line as they are only called from within Value.cpp anyway. llvm-svn: 157123
* Tidy up some spacing and inconsistent use of pre/post increment. No ↵Craig Topper2012-05-192-28/+28
| | | | | | functional change intended. llvm-svn: 157122
* Ordinary PR1255 patch: DifferenceEngine and CPPBackend adopted to the new ↵Stepan Dyatkovskiy2012-05-191-1/+1
| | | | | | SwitchInst methods. llvm-svn: 157112
* Copy some AVX support from MCJIT to JIT. Maybe will fix PR12748.Craig Topper2012-05-191-17/+29
| | | | llvm-svn: 157109
* Eliminate dead code after remat.Jakob Stoklund Olesen2012-05-191-1/+3
| | | | | | This will remove the original def once it has no more uses. llvm-svn: 157104
* Don't remat during updateRegDefsUses().Jakob Stoklund Olesen2012-05-191-22/+5
| | | | | | | | | | | Remaining virtreg->physreg copies were rematerialized during updateRegDefsUses(), but we already do the same thing in joinCopy() when visiting the physreg copy instruction. Eliminate the preserveSrcInt argument to reMaterializeTrivialDef(). It is now always true. llvm-svn: 157103
* Immediately erase trivially useless copies.Jakob Stoklund Olesen2012-05-191-2/+4
| | | | | | | There is no need for these instructions to stick around since they are known to be not dead. llvm-svn: 157102
* Run proper recursive dead code elimination during coalescing.Jakob Stoklund Olesen2012-05-192-21/+63
| | | | | | | | | | | | | | | Dead copies cause problems because they are trivial to coalesce, but removing them gived the live range a dangling end point. This patch enables full dead code elimination which trims live ranges to their uses so end points don't dangle. DCE may erase multiple instructions. Put the pointers in an ErasedInstrs set so we never risk visiting erased instructions in the work list. There isn't supposed to be any dead copies entering RegisterCoalescer, but they do slip by as evidenced by test/CodeGen/X86/coalescer-dce.ll. llvm-svn: 157101
* Allow LiveRangeEdit to be created with a NULL parent.Jakob Stoklund Olesen2012-05-194-9/+9
| | | | | | The dead code elimination with callbacks is still useful. llvm-svn: 157100
* Actually support DW_TAG_rvalue_reference_type that we were tryingEric Christopher2012-05-192-9/+14
| | | | | | | | to generate out of the front end. rdar://11479676 llvm-svn: 157094
* Add support for the 'd' mips inline asm output modifier.Eric Christopher2012-05-191-12/+17
| | | | | | Patch by Jack Carter. llvm-svn: 157093
* SCEV: Add MarkPendingLoopPredicates to avoid recursive isImpliedCond.Andrew Trick2012-05-191-0/+24
| | | | | | | | | | getUDivExpr attempts to simplify by checking for overflow. isLoopEntryGuardedByCond then evaluates the loop predicate which may lead to the same getUDivExpr causing endless recursion. Fixes PR12868: clang 3.2 segmentation fault. llvm-svn: 157092
* Fix replacing all the users of objc weak runtime routinesDan Gohman2012-05-181-2/+12
| | | | | | when deleting them. rdar://11434915. llvm-svn: 157080
* Modernize naming convention for class members.Jakob Stoklund Olesen2012-05-181-20/+20
| | | | | | No functional change. llvm-svn: 157079
* Move all work list processing to copyCoalesceWorkList().Jakob Stoklund Olesen2012-05-181-39/+42
| | | | | | This will make it possible to filter out erased instructions later. llvm-svn: 157073
* allow LazyValueInfo::getEdgeValue() to reason about multiple edges from the ↵Nuno Lopes2012-05-181-11/+6
| | | | | | same switch instruction by doing union of ranges (which may still be conservative, but it's more aggressive than before) llvm-svn: 157071
* Refactor data-in-code annotations.Jim Grosbach2012-05-1815-140/+212
| | | | | | | | | | | | | | | | | | | | | | Use a dedicated MachO load command to annotate data-in-code regions. This is the same format the linker produces for final executable images, allowing consistency of representation and use of introspection tools for both object and executable files. Data-in-code regions are annotated via ".data_region"/".end_data_region" directive pairs, with an optional region type. data_region_directive := ".data_region" { region_type } region_type := "jt8" | "jt16" | "jt32" | "jta32" end_data_region_directive := ".end_data_region" The previous handling of ARM-style "$d.*" labels was broken and has been removed. Specifically, it didn't handle ARM vs. Thumb mode when marking the end of the section. rdar://11459456 llvm-svn: 157062
* Remove duplicate code that we could just fallthrough to.Eric Christopher2012-05-181-1/+0
| | | | llvm-svn: 157060
* Simplify RegisterCoalescer::copyCoalesceInMBB().Jakob Stoklund Olesen2012-05-181-48/+15
| | | | | | | | | It is no longer necessary to separate VirtCopies, PhysCopies, and ImpDefCopies. Implicitly defined copies are extremely rare after we added the ProcessImplicitDefs pass, and physical register copies are not joined any longer. llvm-svn: 157059
* Add support for the mips 'x' inline asm modifier.Eric Christopher2012-05-181-0/+5
| | | | | | Patch by Jack Carter. llvm-svn: 157057
* Remove support for PhysReg joining.Jakob Stoklund Olesen2012-05-181-136/+14
| | | | | | | | | | | | | | | | | | | | | | | | This has been disabled for a while, and it is not a feature we want to support. Copies between physical and virtual registers are eliminated by good hinting support in the register allocator. Joining virtual and physical registers is really a form of register allocation, and the coalescer is not properly equipped to do that. In particular, it cannot backtrack coalescing decisions, and sometimes that would cause it to create programs that were impossible to register allocate, by exhausting a small register class. It was also very difficult to keep track of the live ranges of aliasing registers when extending the live range of a physreg. By disabling physreg joining, we can let fixed physreg live ranges remain constant throughout the register allocator super-pass. One type of physreg joining remains: A virtual register that has a single value which is a copy of a reserved register can be merged into the reserved physreg. This always lowers register pressure, and since we don't compute live ranges for reserved registers, there are no problems with aliases. llvm-svn: 157055
* Recommited reworked r156804:Stepan Dyatkovskiy2012-05-182-53/+29
| | | | | | SelectionDAGBuilder::Clusterify : main functinality was replaced with CRSBuilder::optimize, so big part of Clusterify's code was reduced. llvm-svn: 157046
* Simplify code a bit. No functional change intended.Craig Topper2012-05-181-14/+8
| | | | llvm-svn: 157044
* Simplify handling of v16i8 shuffles and fix a missed optimization.Craig Topper2012-05-181-30/+8
| | | | llvm-svn: 157043
* Teach two-address pass to update the "source" map so it doesn't perform aEvan Cheng2012-05-181-1/+7
| | | | | | | | | non-profitable commute using outdated info. The test case would still fail because of poor pre-RA schedule. That will be fixed by MI scheduler. rdar://11472010 llvm-svn: 157038
* Clarify comment.Eric Christopher2012-05-181-1/+1
| | | | llvm-svn: 157033
* fix corner case in ConstantRange::intersectWith().Nuno Lopes2012-05-181-1/+1
| | | | | | this fixes the missed optimization I was seeing in the CorrelatedValuePropagation pass llvm-svn: 157032
* minor simplification in the call to ConstantRange constructorNuno Lopes2012-05-171-1/+1
| | | | llvm-svn: 157024
* commentsAndrew Trick2012-05-171-2/+3
| | | | llvm-svn: 157020
* Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missingKevin Enderby2012-05-173-11/+54
| | | | | | | | | | the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 llvm-svn: 157019
* Remove extraneous ';'.Bill Wendling2012-05-171-1/+1
| | | | llvm-svn: 157011
* misched: trace ReadyQ.Andrew Trick2012-05-171-0/+8
| | | | llvm-svn: 157007
* misched: Added 3-level regpressure back-off.Andrew Trick2012-05-173-75/+288
| | | | | | | | | | | | | | | | | | Introduce the basic strategy for register pressure scheduling. 1) Respect target limits at all times. 2) Indentify critical register classes (pressure sets). Track pressure within the scheduled region. Avoid increasing scheduled pressure for critical registers. 3) Avoid exceeding the max pressure of the region prior to scheduling. Added logic for picking between the top and bottom ready Q's based on regpressure heuristics. Status: functional but needs to be asjusted to achieve good results. llvm-svn: 157006
* commentAndrew Trick2012-05-172-3/+1
| | | | llvm-svn: 157005
* regpressure: Fix getMaxUpwardPressureDelta.Andrew Trick2012-05-171-2/+6
| | | | llvm-svn: 157004
* misched: fix liveness iteratorsAndrew Trick2012-05-171-10/+16
| | | | llvm-svn: 157003
* whitespaceAndrew Trick2012-05-172-2/+3
| | | | llvm-svn: 157002
* Never clear <undef> flags on already joined copies.Jakob Stoklund Olesen2012-05-171-4/+6
| | | | | | | | | | | | | | | | | | | | | RegisterCoalescer set <undef> flags on all operands of copy instructions that are scheduled to be removed. This is so they won't affect shrinkToUses() by introducing false register reads. Make sure those <undef> flags are never cleared, or shrinkToUses() could cause live intervals to end at instructions about to be deleted. This would be a lot simpler if RegisterCoalescer could just erase joined copies immediately instead of keeping all the to-be-deleted instructions around. This fixes PR12862. Unfortunately, bugpoint can't create a sane test case for this. Like many other coalescer problems, this failure depends of a very fragile series of events. <rdar://problem/11474428> llvm-svn: 157001
* Fix a verifier bug.Jakob Stoklund Olesen2012-05-171-1/+1
| | | | | | Make sure useless (def-only) intervals also get verified. llvm-svn: 157000
* Relax the requirement that the exception object must be an instruction. DuringBill Wendling2012-05-171-6/+6
| | | | | | bugpoint-ing, it may turn into something else. llvm-svn: 156998
* enhance the intrinsic info stuff to emit encodings that don't fit in 32-bits ↵Chris Lattner2012-05-171-17/+20
| | | | | | | | | into a separate side table, using the handy SequenceToOffsetTable class. This encodes all these weird things into another 256 bytes, allowing all intrinsics to be encoded this way. llvm-svn: 156995
* Remove incorrect pattern for ARM SMML instruction.Tim Northover2012-05-171-2/+1
| | | | | | Patch by Meador Inge. llvm-svn: 156989
* Fix compile error.Manuel Klimek2012-05-171-1/+1
| | | | llvm-svn: 156986
* SelectionDAGBuilder: CaseBlock, CaseRanges and CaseCmp changed ↵Stepan Dyatkovskiy2012-05-172-10/+11
| | | | | | representation of Low and High from signed to unsigned. Since unsigned ints usually simpler, faster and allows to reduce some extra signed bit checks needed before <,>,<=,>= comparisons. llvm-svn: 156985
* Genericize the intrinsics descriptor decoding a bit to make room Chris Lattner2012-05-171-20/+25
| | | | | | for future expansion, no functionality change yet though. llvm-svn: 156979
* finish encoding all of the interesting details of intrinsics. Now intrinsicsChris Lattner2012-05-171-3/+25
| | | | | | | are only rejected because they can't be encoded into a 32-bit unit, not because they contain an unencodable feature. llvm-svn: 156978
OpenPOWER on IntegriCloud