summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* DebugInfo: Push header handling down into CompileUnitDavid Blaikie2013-10-303-18/+29
| | | | | | | This is a preliminary step to handling type units by abstracting over all (type or compile) units. llvm-svn: 193714
* Fix GVN creating bitcast between address spacesMatt Arsenault2013-10-301-5/+7
| | | | llvm-svn: 193710
* This commit adds some (but not all) of the x86-64 relocations that are notTom Roeder2013-10-301-0/+6
| | | | | | currently supported in the ELF object writer, along with a simple test case. llvm-svn: 193709
* Add {start,end}with_lower methods to StringRef.Rui Ueyama2013-10-301-5/+24
| | | | | | | | | startswith_lower is ocassionally useful and I think worth adding. endwith_lower is added for completeness. Differential Revision: http://llvm-reviews.chandlerc.com/D2041 llvm-svn: 193706
* [ARM] NEON instructions were erroneously decoded from certain invalid encodingsArtyom Skrobov2013-10-301-20/+20
| | | | llvm-svn: 193705
* R600: Custom lower f32 = uint_to_fp i64Tom Stellard2013-10-302-0/+23
| | | | llvm-svn: 193701
* DwarfDebug: Change Abbreviations member from pointer to referenceDavid Blaikie2013-10-302-10/+10
| | | | llvm-svn: 193699
* Add #include of raw_ostream.h to MipsSEISelLowering.cppHans Wennborg2013-10-301-0/+1
| | | | | | | | Fixing this Windows build error: ..\lib\Target\Mips\MipsSEISelLowering.cpp(997) : error C2027: use of undefined type 'llvm::raw_ostream' llvm-svn: 193696
* [mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related testsDaniel Sanders2013-10-301-8/+29
| | | | llvm-svn: 193695
* make ConstantRange::signExtend() optimalNuno Lopes2013-10-301-0/+5
| | | | | | the case [x, INT_MIN) was not handled optimally llvm-svn: 193694
* [mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from ↵Daniel Sanders2013-10-303-10/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | normal IR (i.e. not intrinsics) Also corrected the definition of the intrinsics for these instructions (the result register is also the first operand), and added intrinsics for bsel and bseli to clang (they already existed in the backend). These four operations are mostly equivalent to bsel, and bseli (the difference is which operand is tied to the result). As a result some of the tests changed as described below. bitwise.ll: - bsel.v test adapted so that the mask is unknown at compile-time. This stops it emitting bmnzi.b instead of the intended bsel.v. - The bseli.b test now tests the right thing. Namely the case when one of the values is an uimm8, rather than when the condition is a uimm8 (which is covered by bmnzi.b) compare.ll: - bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this is the same operation (see MSA.txt). i8.ll - CHECK-DAG-ized test. - bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands because this is the same operation (see MSA.txt). - bseli.b still emits bseli.b though because the immediate makes it distinguishable from bmnzi.b. vec.ll: - CHECK-DAG-ized test. - bmz.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). - bsel.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). llvm-svn: 193693
* [AArch64] Add support for NEON scalar floating-point compare instructions.Chad Rosier2013-10-303-5/+102
| | | | llvm-svn: 193691
* [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. ↵Daniel Sanders2013-10-307-27/+163
| | | | | | | | | | | | | | | | | not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. llvm-svn: 193687
* [mips][msa] Combine binsri-like DAG of AND and OR into equivalent VSELECTDaniel Sanders2013-10-301-0/+108
| | | | | | | | | | | | | | | (or (and $a, $mask), (and $b, $inverse_mask)) => (vselect $mask, $a, $b). where $mask is a constant splat. This allows bitwise operations to make use of bsel. It's also a stepping stone towards matching bins[lr], and bins[lr]i from normal IR. Two sets of similar tests have been added in this commit. The bsel_* functions test the case where binsri cannot be used. The binsr_*_i functions will start to use the binsri instruction in the next commit. llvm-svn: 193682
* [mips] MipsSETargetLowering now reports DAGCombiner changes when using ↵Daniel Sanders2013-10-301-1/+9
| | | | | | | | -debug-only=mips-isel No test since -debug output is intended for developers and not end-users. llvm-svn: 193681
* [mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not ↵Daniel Sanders2013-10-303-26/+57
| | | | | | | | | | intrinsics) splat.d is implemented but this subtest is currently disabled. This is because it is difficult to match the appropriate IR on MIPS32. There is a patch under review that should help with this so I hope to enable the subtest soon. llvm-svn: 193680
* Revert "SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs ↵Juergen Ributzka2013-10-303-45/+9
| | | | | | | | splitting too." Now Hexagon and SystemZ are not happy with it :-( llvm-svn: 193677
* SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.Juergen Ributzka2013-10-303-9/+45
| | | | | | | | | | | | | | | | | | | | The Type Legalizer recognizes that VSELECT needs to be split, because the type is to wide for the given target. The same does not always apply to SETCC, because less space is required to encode the result of a comparison. As a result VSELECT is split and SETCC is unrolled into scalar comparisons. This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG Combiner. If a matching pattern is found, then the result mask of SETCC is promoted to the expected vector mask type for the given target. This mask has usually the same size as the VSELECT return type (except for Intel KNL). Now the type legalizer will split both VSELECT and SETCC. This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>. Reviewed by Nadav llvm-svn: 193676
* Reformat Makefile. No other changes.Bill Wendling2013-10-301-4/+3
| | | | llvm-svn: 193675
* [mips] Compute stack alignment on the fly.Akira Hatanaka2013-10-303-7/+3
| | | | llvm-svn: 193673
* Reformat code with clang-format.Josh Magee2013-10-301-37/+40
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D2057 llvm-svn: 193672
* Debug Info: code clean up.Manman Ren2013-10-292-3/+5
| | | | | | | | | | Use EmitLabelOffsetDifference for handling on darwin platform when non-darwin platforms use EmitLabelPlusOffset. Also fix a bug in EmitLabelOffsetDifference where the size is hard-coded to 4 even though Size is passed in as an argument. llvm-svn: 193660
* Debug Info: support for DW_FORM_ref_addr.Manman Ren2013-10-296-3/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support ref_addr, we calculate the section offset of a DIE (i.e. offset of a DIE from beginning of the debug info section). The Offset field in DIE is currently CU-relative. To calculate the section offset, we add a DebugInfoOffset field in CompileUnit to store the offset of a CU from beginning of the debug info section. We set the value in DwarfUnits::computeSizeAndOffset for each CompileUnit. A helper function DIE::getCompileUnit is added to return the CU DIE that the input DIE belongs to. We also add a map CUDieMap in DwarfDebug to help finding the CU for a given CU DIE. For a cross-referenced DIE, we first find the CU DIE it belongs to with getCompileUnit, then we use CUDieMap to get the corresponding CU for the CU DIE. Adding the section offset of the CU with the CU-relative offset of a DIE gives us the seciton offset of the DIE. We correctly emit ref_addr with relocation using EmitLabelPlusOffset when doesDwarfUseRelocationsAcrossSections is true. This commit handles the emission of DW_FORM_ref_addr when we have an attribute with FORM_ref_addr. A follow-on patch will start using ref_addr when adding a DIEEntry. This commit will be tested and verified in the follow-on patch. Reviewed off-list by Eric, Thanks. llvm-svn: 193658
* Debug Info: instead of calling addToContextOwner which constructs the contextManman Ren2013-10-292-21/+9
| | | | | | | | | | | | | | | after the DIE creation, we construct the context first. Ensure that we create the context before we create a type so that we can add the newly created type to the parent. Remove last use of addToContextOwner now that it's not needed. We use createAndAddDIE to wrap around "new DIE(". Now all shareable DIEs should be added to their parents right after the creation. Reviewed off-list by Eric, Thanks. llvm-svn: 193657
* Struct byval cleanup: add helper functions to reduce code duplication.Manman Ren2013-10-291-180/+117
| | | | | | | | | | Helper functions are added: emitPostLd: emit a post-increment load operation with given size. emitPostSt: emit a post-increment store operation with given size. No functionality change. llvm-svn: 193656
* [stackprotector] Update the StackProtector pass to perform datalayout analysis.Josh Magee2013-10-291-27/+60
| | | | | | | | | | | | | | | This modifies the pass to classify every SSP-triggering AllocaInst according to an SSPLayoutKind (LargeArray, SmallArray, AddrOf). This analysis is collected by the pass and made available for use, but no other pass uses it yet. The next patch will make use of this analysis in PEI and StackSlot passes. The end goal is to support ssp-strong stack layout rules. WIP. Differential Revision: http://llvm-reviews.chandlerc.com/D1789 llvm-svn: 193653
* Removing a switch statement that contains only a default label. This ↵Aaron Ballman2013-10-291-28/+25
| | | | | | resolves an MSVC warning. No functional change intended. llvm-svn: 193649
* [mips] Align the stack to 16-bytes for mfp64.Akira Hatanaka2013-10-295-4/+11
| | | | llvm-svn: 193641
* Move getSymbol to TargetLoweringObjectFile.Rafael Espindola2013-10-2910-31/+30
| | | | | | This allows constructing a Mangler with just a TargetMachine. llvm-svn: 193630
* Add a helper getSymbol to AsmPrinter.Rafael Espindola2013-10-2925-84/+87
| | | | llvm-svn: 193627
* [AArch64] Implement FrameAddr and ReturnAddrWeiming Zhao2013-10-292-0/+43
| | | | | | Fixes PR17690 llvm-svn: 193625
* [ARM] Make sure HasCRC is initialized to false in Subtarget.Amara Emerson2013-10-291-0/+1
| | | | llvm-svn: 193624
* Support for microMIPS jump instructionsZoran Jovanovic2013-10-2912-21/+139
| | | | llvm-svn: 193623
* R600/SI: Add compute support for CI v2Tom Stellard2013-10-296-9/+24
| | | | | | | | v2: - Fix LDS size calculation Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 193621
* R600: Expand vector FSQRT opsTom Stellard2013-10-291-0/+1
| | | | llvm-svn: 193620
* DWARF parser: propery handle DW_FORM_ref_sig8 and fix Windows build.Alexey Samsonov2013-10-291-43/+41
| | | | | | Based on D2050 by Timur Iskhodzhanov. llvm-svn: 193619
* The asm printer has a mangler. Use it.Rafael Espindola2013-10-293-7/+4
| | | | llvm-svn: 193618
* The AsmPrinter has a Mangler. Use it.Rafael Espindola2013-10-293-8/+6
| | | | llvm-svn: 193617
* The asm printer has a mangler. Don't keep a second pointer to it.Rafael Espindola2013-10-291-10/+11
| | | | llvm-svn: 193616
* Quick-fix DebugInfo build on WindowsTimur Iskhodzhanov2013-10-291-1/+3
| | | | | | | | | | | | | | | MSVC can't comprehend template<typename T, size_t N> ArrayRef<T> makeArrayRef(const T (&Arr)[N]) { return ArrayRef<T>(Arr); } if Arr is static const uint8_t sizes[]; declared in a templated and defined a few lines later. I'll send a proper fix (i.e. get rid of unnecessary templates) for review soon. llvm-svn: 193604
* ARM: Add subtarget feature for CRCBernard Ogden2013-10-295-6/+14
| | | | | | | | Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend. Differential Revision: http://llvm-reviews.chandlerc.com/D2036 llvm-svn: 193599
* Fix misapplied patch in r193597Anders Waldenborg2013-10-291-2/+2
| | | | | | Sorry Peter Zotov, entirely my fault. llvm-svn: 193598
* llvm-c: Make LLVM{Get,Set}Alignment work on {Load,Store}Inst tooAnders Waldenborg2013-10-291-4/+22
| | | | | | | | Patch by Peter Zotov Differential Revision: http://llvm-reviews.chandlerc.com/D1910 llvm-svn: 193597
* AArch64: add 'a' inline asm operand modifierTim Northover2013-10-291-0/+2
| | | | | | | This is used in the Linux kernel, and effectively just means "print an address". llvm-svn: 193593
* Debug Info: instead of calling addToContextOwner which constructs the contextManman Ren2013-10-291-7/+17
| | | | | | | | | | | | after the DIE creation, we construct the context first. This touches creation of namespaces and global variables. The purpose is to handle all DIE creations similarly: constructs the context first, then creates the DIE and immediately adds the DIE to its parent. We use createAndAddDIE to wrap around "new DIE(". llvm-svn: 193589
* Fix "existant" typosAlp Toker2013-10-291-1/+1
| | | | llvm-svn: 193579
* Clean up.Richard Smith2013-10-291-4/+4
| | | | llvm-svn: 193576
* DWARFFormValue.cpp: Appease gcc to give explicit constructors.NAKAMURA Takumi2013-10-291-4/+4
| | | | | | error: conversion from `const uint8_t*' to non-scalar type `llvm::ArrayRef<unsigned char>' requested llvm-svn: 193575
* ARM cost model: Unaligned vectorized double stores are expensiveArnold Schwaighofer2013-10-291-0/+15
| | | | | | | | | Updated a test case that assumed that <2 x double> would vectorize to use <4 x float>. radar://15338229 llvm-svn: 193574
* ARM cost model: Account for zero cost scalar SROA instructionsArnold Schwaighofer2013-10-292-6/+33
| | | | | | | | | By vectorizing a series of srl, or, ... instructions we have obfuscated the intention so much that the backend does not know how to fold this code away. radar://15336950 llvm-svn: 193573
OpenPOWER on IntegriCloud