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* Revert "[safestack] Fast access to the unsafe stack pointer on AArch64/Android."Evgeniy Stepanov2015-10-156-66/+65
| | | | | | Breaks the hexagon buildbot. llvm-svn: 250461
* Replace a forward declaration with an #include.Adrian Prantl2015-10-151-1/+2
| | | | | | | When building with modules the forward-declared inner class DebugLocStream::ListBuilder causes clang to fall over. llvm-svn: 250459
* [safestack] Fast access to the unsafe stack pointer on AArch64/Android.Evgeniy Stepanov2015-10-156-65/+66
| | | | | | | | | | | | | | | | Android libc provides a fixed TLS slot for the unsafe stack pointer, and this change implements direct access to that slot on AArch64 via __builtin_thread_pointer() + offset. This change also moves more code into TargetLowering and its target-specific subclasses to get rid of target-specific codegen in SafeStackPass. This change does not touch the ARM backend because ARM lowers builting_thread_pointer as aeabi_read_tp, which is not available on Android. llvm-svn: 250456
* Add a missing include of cstddef needed for size_t.Adrian Prantl2015-10-151-0/+1
| | | | llvm-svn: 250446
* x86: preserve flags when folding atomic operationsJF Bastien2015-10-151-15/+20
| | | | | | | | | | D4796 taught LLVM to fold some atomic integer operations into a single instruction. The pattern was unaware that the instructions clobbered flags. I fixed some of this issue in D13680 but had missed INC/DEC. This patch adds the missing EFLAGS definition. llvm-svn: 250438
* [SelectionDAG] Remove dead code. NFC.Benjamin Kramer2015-10-156-139/+1
| | | | | | Carefully selected parts without deleting graph stuff and dumping methods. llvm-svn: 250434
* [AsmPrinter] Prune dead code. NFC.Benjamin Kramer2015-10-156-111/+0
| | | | | | I left all (dead) print and dump methods in place. llvm-svn: 250433
* Revert 250343 and 250344Philip Reames2015-10-151-117/+0
| | | | | | | | | | | | | | | | | | | | | | | | Turns out this approach is buggy. In discussion about follow on work, Sanjoy pointed out that we could be subject to circular logic problems. Consider: if (i u< L) leave() if ((i + 1) u< L) leave() print(a[i] + a[i+1]) If we know that L is less than UINT_MAX, we could possible prove (in a control dependent way) that i + 1 does not overflow. This gives us: if (i u< L) leave() if ((i +nuw 1) u< L) leave() print(a[i] + a[i+1]) If we now do the transform this patch proposed, we end up with: if ((i +nuw 1) u< L) leave_appropriately() print(a[i] + a[i+1]) That would be a miscompile when i==-1. The problem here is that the control dependent nuw bits got used to prove something about the first condition. That's obviously invalid. This won't happen today, but since I plan to enhance LVI/CVP with exactly that transform at some point in the not too distant future... llvm-svn: 250430
* x86 FP atomic codegen: don't drop globals, stackJF Bastien2015-10-151-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: x86 codegen is clever about generating good code for relaxed floating-point operations, but it was being silly when globals and immediates were involved, forgetting where the global was and loading/storing from/to the wrong place. The same applied to hard-coded address immediates. Don't let it forget about the displacement. This fixes https://llvm.org/bugs/show_bug.cgi?id=25171 A very similar bug when doing floating-points atomics to the stack is also fixed by this patch. This fixes https://llvm.org/bugs/show_bug.cgi?id=25144 Reviewers: pete Subscribers: llvm-commits, majnemer, rsmith Differential Revision: http://reviews.llvm.org/D13749 llvm-svn: 250429
* Sample Profiles - Adjust integer types. Mostly NFC.Diego Novillo2015-10-153-47/+54
| | | | | | | | | | | | | | This adjusts all integers in the reader/writer to reflect the types stored on profile files. They should all be unsigned 32-bit or 64-bit values. Changed all associated internal types to be uint32_t or uint64_t. The only place that needed some adjustments is in the sample profile transformation. Altough the weight read from the profile are 64-bit values, the internal API for branch weights only accepts 32-bit values. The pass now saturates weights that overflow uint32_t. llvm-svn: 250427
* Prevent assertion with "llc -debug" and anonymous symbols.Tim Northover2015-10-151-1/+1
| | | | llvm-svn: 250425
* [ScalarOpts] Remove dead code.Benjamin Kramer2015-10-155-53/+9
| | | | | | Does not touch debug dumpers. NFC. llvm-svn: 250417
* Recommit r250345, it was reverted in r250366 to investigate a bot failure.Manman Ren2015-10-153-5/+129
| | | | | | Our internal bot is still red after r250366. llvm-svn: 250415
* [mips][ias] Implement ulh macro.Daniel Sanders2015-10-152-7/+13
| | | | | | | | | | | | | | Summary: This macro is needed to prevent test/CodeGen/Mips/2008-08-01-AsmInline.ll from failing after the integrated assembler is enabled by default. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13654 llvm-svn: 250414
* Require Windows API of version 6.1 (Windows 7).Pawel Bylica2015-10-151-3/+3
| | | | llvm-svn: 250413
* [NVPTX] Remove dead code.Benjamin Kramer2015-10-159-222/+0
| | | | | | I left helpers that look useful for debugging alone. NFC. llvm-svn: 250410
* [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE.Daniel Sanders2015-10-152-2/+0
| | | | | | | | | | | | | | | | Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 llvm-svn: 250407
* [X86] Rip out orphaned method declarations and other dead code. NFC.Benjamin Kramer2015-10-157-53/+0
| | | | llvm-svn: 250406
* Silencing a -Wtype-limits warning; an unsigned value will always be >= 0; NFC.Aaron Ballman2015-10-151-1/+1
| | | | llvm-svn: 250404
* AVX512: Implemented DAG lowering for shuff62x2/shufi62x2 instructions ( ↵Igor Breger2015-10-154-1/+133
| | | | | | | | shuffle packed values at 128-bit granularity ) Differential Revision: http://reviews.llvm.org/D13648 llvm-svn: 250400
* AVX512: Implemented encoding and intrinsics for vpternlogd/q.Igor Breger2015-10-155-4/+98
| | | | | | Differential Revision: http://reviews.llvm.org/D13768 llvm-svn: 250396
* AVX-512: Fixed a bug in shuffle lowering 32-bit modeElena Demikhovsky2015-10-151-6/+35
| | | | | | | | | AVX-512 bit shuffle fails on 32 bit since we create a vector of 64-bit constants. I split 8x64-bit const vector to 16x32 on 32-bit mode. Differential Revision: http://reviews.llvm.org/D13644 llvm-svn: 250390
* Don't pretend AMDGPU backend knows how to custom-lower UDIVREM for vector ↵Artyom Skrobov2015-10-151-1/+1
| | | | | | | | | | | | types; it can't Reviewers: arsenm, jvesely, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D13734 llvm-svn: 250384
* [mips][microMIPS] Implement DPA.W.PH, DPAQ_S.W.PH, DPAQ_SA.L.W, ↵Zlatko Buljan2015-10-154-12/+51
| | | | | | | | DPAQX_S.W.PH, DPAQX_SA.W.PH, DPAU.H.QBL, DPAU.H.QBR and DPAX.W.PH instructions Differential Revision: http://reviews.llvm.org/D13376 llvm-svn: 250382
* [mips][microMIPS] Implement BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 ↵Hrvoje Varga2015-10-153-13/+68
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D11292#inline-103143 llvm-svn: 250381
* [mips][microMIPS] Implement LLE and SCE instructionsHrvoje Varga2015-10-153-0/+37
| | | | | | Differential Revision: http://reviews.llvm.org/D11630 llvm-svn: 250379
* [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructionsHrvoje Varga2015-10-152-0/+26
| | | | | | Differential Revision: http://reviews.llvm.org/D11631 llvm-svn: 250377
* Remove DIFile from createSubroutineType.Eric Christopher2015-10-151-2/+1
| | | | | | Patch by Amaury Sechet with a small modification by me. llvm-svn: 250374
* [RuntimeDyld] Don't try to get the contents of sections that don't have anyLang Hames2015-10-151-7/+7
| | | | | | | | | | | (e.g. bss sections). MachO and ELF have been silently letting this pass, but COFFObjectFile contains an assertion to catch this kind of (ab)use of the getSectionContents, and this was causing the JIT to crash on COFF objects with BSS sections. This patch should fix that. llvm-svn: 250371
* [MachO] Stop generating *coal* sections.Akira Hatanaka2015-10-152-13/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recommit r250342: move coal-sections-powerpc.s to subdirectory for powerpc. Some background on why we don't have to use *coal* sections anymore: Long ago when C++ was new and "weak" had not been standardized, an attempt was made in cctools to support C++ inlines that can be coalesced by putting them into their own section (TEXT/textcoal_nt instead of TEXT/text). The current macho linker supports the weak-def bit on any symbol to allow it to be coalesced, but the compiler still puts weak-def functions/data into alternate section names, which the linker must map back to the base section name. This patch makes changes that are necessary to prevent the compiler from using the "coal" sections and have it use the non-coal sections instead when the target architecture is not powerpc: TEXT/textcoal_nt instead use TEXT/text TEXT/const_coal instead use TEXT/const DATA/datacoal_nt instead use DATA/data If the target is powerpc, we continue to use the *coal* sections since anyone targeting powerpc is probably using an old linker that doesn't have support for the weak-def bits. Also, have the assembler issue a warning if it encounters a *coal* section in the assembly file and inform the users to use the non-coal sections instead. rdar://problem/14265330 Differential Revision: http://reviews.llvm.org/D13188 llvm-svn: 250370
* Test commit.Hrvoje Varga2015-10-151-1/+0
| | | | llvm-svn: 250367
* Temporarily revert r250345 to sort out bot failure.Manman Ren2015-10-153-129/+5
| | | | | | | | | | | | | | With r250345 and r250343, we start to observe the following failure when bootstrap clang with lto and pgo: PHI node entries do not match predecessors! %.sroa.029.3.i = phi %"class.llvm::SDNode.13298"* [ null, %30953 ], [ null, %31017 ], [ null, %30998 ], [ null, %_ZN4llvm8dyn_castINS_14ConstantSDNodeENS_7SDValueEEENS_10cast_rettyIT_T0_E8ret_typeERS5_.exit.i.1804 ], [ null, %30975 ], [ null, %30991 ], [ null, %_ZNK4llvm3EVT13getScalarTypeEv.exit.i.1812 ], [ %..sroa.029.0.i, %_ZN4llvm11SmallVectorIiLj8EED1Ev.exit.i.1826 ], !dbg !451895 label %30998 label %_ZNK4llvm3EVTeqES0_.exit19.thread.i LLVM ERROR: Broken function found, compilation aborted! I will re-commit this if the bot does not recover. llvm-svn: 250366
* Add XSAVE/XSAVEOPT to KNL processor.Craig Topper2015-10-151-0/+2
| | | | llvm-svn: 250362
* [llvm-pdbdump] Provide a mechanism to dump the raw contents of a PDBDavid Majnemer2015-10-151-2/+3
| | | | | | | | | A PDB can be thought of as a very simple file system. It is occasionally illuminating to see the contents of the underlying files. Differential Revision: http://reviews.llvm.org/D13674 llvm-svn: 250356
* Fix -Wmismatched-tags error in modules build by removing unused forward ↵Richard Smith2015-10-151-1/+0
| | | | | | declaration. llvm-svn: 250355
* [ARM] Make sure we do not dereference the end iterator when accessing debugQuentin Colombet2015-10-151-2/+2
| | | | | | | | | | information. Although the problem was always here, it would only be exposed when shrink-wrapping is enable. rdar://problem/23110493 llvm-svn: 250352
* Revert r250349.Akira Hatanaka2015-10-152-53/+13
| | | | | | Test case coal-sections-powerpc.s is still failing on some buildbots. llvm-svn: 250351
* [MachO] Stop generating *coal* sections.Akira Hatanaka2015-10-142-13/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recommit r250342: add -arch=ppc32 to the RUN lines of powerpc tests. Some background on why we don't have to use *coal* sections anymore: Long ago when C++ was new and "weak" had not been standardized, an attempt was made in cctools to support C++ inlines that can be coalesced by putting them into their own section (TEXT/textcoal_nt instead of TEXT/text). The current macho linker supports the weak-def bit on any symbol to allow it to be coalesced, but the compiler still puts weak-def functions/data into alternate section names, which the linker must map back to the base section name. This patch makes changes that are necessary to prevent the compiler from using the "coal" sections and have it use the non-coal sections instead when the target architecture is not powerpc: TEXT/textcoal_nt instead use TEXT/text TEXT/const_coal instead use TEXT/const DATA/datacoal_nt instead use DATA/data If the target is powerpc, we continue to use the *coal* sections since anyone targeting powerpc is probably using an old linker that doesn't have support for the weak-def bits. Also, have the assembler issue a warning if it encounters a *coal* section in the assembly file and inform the users to use the non-coal sections instead. rdar://problem/14265330 Differential Revision: http://reviews.llvm.org/D13188 llvm-svn: 250349
* Revert r250342.Akira Hatanaka2015-10-142-53/+13
| | | | | | Investigate why coal-sections-powerpc.s is failing on some buildbots. llvm-svn: 250346
* Update the branch weight metadata in JumpThreading pass.Cong Hou2015-10-143-5/+129
| | | | | | | | | | Currently in JumpThreading pass, the branch weight metadata is not updated after CFG modification. Consider the jump threading on PredBB, BB, and SuccBB. After jump threading, the weight on BB->SuccBB should be adjusted as some of it is contributed by the edge PredBB->BB, which doesn't exist anymore. This patch tries to update the edge weight in metadata on BB->SuccBB by scaling it by 1 - Freq(PredBB->BB) / Freq(BB->SuccBB). This is the third attempt to submit this patch, while the first two led to failures in some FDO tests. After investigation, it is the edge weight normalization that caused those failures. In this patch the edge weight normalization is fixed so that there is no zero weight in the output and the sum of all weights can fit in 32-bit integer. Several unit tests are added. Differential revision: http://reviews.llvm.org/D10979 llvm-svn: 250345
* [SimplifyCFG] Speculatively flatten CFG based on profiling metadataPhilip Reames2015-10-141-7/+124
| | | | | | | | | | If we have a series of branches which are all unlikely to fail, we can possibly combine them into a single check on the fastpath combined with a bit of dispatch logic on the slowpath. We don't want to do this unconditionally since it requires speculating instructions past a branch, but if the profiling metadata on the branch indicates profitability, this can reduce the number of checks needed along the fast path. The canonical example this is trying to handle is removing the second bounds check implied by the Java code: a[i] + a[i+1]. Note that it can currently only do so for really simple conditions and the values of a[i] can't be used anywhere except in the addition. (i.e. the load has to have been sunk already and not prevent speculation.) I plan on extending this transform over the next few days to handle alternate sequences. Differential Revision: http://reviews.llvm.org/D13070 llvm-svn: 250343
* [MachO] Stop generating *coal* sections.Akira Hatanaka2015-10-142-13/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some background on why we don't have to use *coal* sections anymore: Long ago when C++ was new and "weak" had not been standardized, an attempt was made in cctools to support C++ inlines that can be coalesced by putting them into their own section (TEXT/textcoal_nt instead of TEXT/text). The current macho linker supports the weak-def bit on any symbol to allow it to be coalesced, but the compiler still puts weak-def functions/data into alternate section names, which the linker must map back to the base section name. This patch makes changes that are necessary to prevent the compiler from using the "coal" sections and have it use the non-coal sections instead when the target architecture is not powerpc: TEXT/textcoal_nt instead use TEXT/text TEXT/const_coal instead use TEXT/const DATA/datacoal_nt instead use DATA/data If the target is powerpc, we continue to use the *coal* sections since anyone targeting powerpc is probably using an old linker that doesn't have support for the weak-def bits. Also, have the assembler issue a warning if it encounters a *coal* section in the assembly file and inform the users to use the non-coal sections instead. rdar://problem/14265330 Differential Revision: http://reviews.llvm.org/D13188 llvm-svn: 250342
* Tighten known bits for ctpop based on zero input bitsPhilip Reames2015-10-141-2/+12
| | | | | | | | | | This is a cleaned up patch from the one written by John Regehr based on the findings of the Souper superoptimizer. The basic idea here is that input bits that are known zero reduce the maximum count that the intrinsic could return. We know that the number of bits required to represent a particular count is at most log2(N)+1. Differential Revision: http://reviews.llvm.org/D13253 llvm-svn: 250338
* [PowerPC] Fix invalid lxvdsx optimization (PR25157)Bill Schmidt2015-10-141-0/+2
| | | | | | | | | | | | PR25157 identifies a bug where a load plus a vector shuffle is incorrectly converted into an LXVDSX instruction. That optimization is only valid if the load is of a doubleword, and in the noted case, it was not. This corrects that problem. Joint patch with Eric Schweitz, who provided the bugpoint-reduced test case. llvm-svn: 250324
* [LoopUnswitch] Correct misleading comments.Chen Li2015-10-141-2/+1
| | | | | | | | | | Reviewers: reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13738 llvm-svn: 250317
* Sample profiles - Add documentation for binary profile encoding. NFC.Diego Novillo2015-10-141-103/+6
| | | | | | | | This adds documentation for the binary profile encoding and moves the documentation for the text encoding into the header file SampleProfReader.h. llvm-svn: 250309
* A doccomment for CombineTo, and some NFC refactoringsArtyom Skrobov2015-10-141-39/+34
| | | | | | | | | | | | | | Summary: Caching SDLoc(N), instead of recreating it in every single function call, keeps the code denser, and allows to unwrap long lines. Reviewers: sunfish, atrick, sdmitrouk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13726 llvm-svn: 250305
* Merge DAGCombiner::visitSREM and DAGCombiner::visitUREM (NFC)Artyom Skrobov2015-10-141-66/+34
| | | | | | | | | | | | Summary: The two implementations had more code in common than not. Reviewers: sunfish, MatzeB, sdmitrouk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13724 llvm-svn: 250302
* [x86][FastISel] Teach how to select nontemporal stores.Andrea Di Biagio2015-10-141-16/+34
| | | | | | | | | | | | | | | | | | | | | | This patch teaches x86 fast-isel how to select nontemporal stores. On x86, we can use MOVNTI for nontemporal stores of doublewords/quadwords. Instructions (V)MOVNTPS/PD/DQ can be used for SSE2/AVX aligned nontemporal vector stores. Before this patch, fast-isel always selected 'movd/movq' instead of 'movnti' for doubleword/quadword nontemporal stores. In the case of nontemporal stores of aligned vectors, fast-isel always selected movaps/movapd/movdqa instead of movntps/movntpd/movntdq. With this patch, if we use SSE2/AVX intrinsics for nontemporal stores we now always get the expected (V)MOVNT instructions. The lack of fast-isel support for nontemporal stores was spotted when analyzing the -O0 codegen for nontemporal stores. Differential Revision: http://reviews.llvm.org/D13698 llvm-svn: 250285
* [X86] Update CPU detection to only enable XSAVE features if the OS has ↵Craig Topper2015-10-141-14/+16
| | | | | | enabled them and the saving of YMM state. This seems to be consistent with gcc behavior. llvm-svn: 250269
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