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* Make calls to getVectorShuffle more consistent. Use shuffle VT for calls to ↵Craig Topper2012-04-221-8/+7
| | | | | | getUNDEF instead of requerying. Use &Mask[0] instead of Mask.data(). llvm-svn: 155320
* Tidy up. 80 columns and argument alignment.Craig Topper2012-04-221-18/+17
| | | | llvm-svn: 155319
* Simplify code by converting multiple places that were manually concatenating ↵Craig Topper2012-04-221-20/+18
| | | | | | 128-bit vectors to use either CONCAT_VECTORS or a helper function. CONCAT_VECTORS will itself be lowered to the same pattern as before. The helper function is needed for concats of BUILD_VECTORs since getNode(CONCAT_VECTORS) will just return a large BUILD_VECTOR and we may be trying to lower large BUILD_VECTORS when this occurs. llvm-svn: 155318
* ARM: Initialize the HasRAS bit.Benjamin Kramer2012-04-221-0/+1
| | | | | | Found by valgrind. llvm-svn: 155313
* ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2Elena Demikhovsky2012-04-224-14/+90
| | | | llvm-svn: 155309
* Remove some potential warnings about variables used uninitialized.Bill Wendling2012-04-222-4/+4
| | | | llvm-svn: 155307
* Add a flag to the struct type finder to collect only those types which haveBill Wendling2012-04-212-7/+10
| | | | | | names. This saves collecting types we normally don't care about. llvm-svn: 155300
* No need for "else if" after a return. Autosense "0o123" as octal inChris Lattner2012-04-211-4/+12
| | | | | | StringRef::getAsInteger llvm-svn: 155298
* Teach getVectorTypeBreakdown about promotion of vectors in addition to ↵Nadav Rotem2012-04-211-3/+6
| | | | | | widening of vectors. llvm-svn: 155296
* Make some fixed arrays const. Use array_lengthof in a couple places instead ↵Craig Topper2012-04-211-8/+8
| | | | | | of a hardcoded number. llvm-svn: 155294
* Tidy up. 80 columns and some other spacing issues.Craig Topper2012-04-211-7/+9
| | | | llvm-svn: 155291
* llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build ↵NAKAMURA Takumi2012-04-212-0/+3
| | | | | | | | on MSVC. Thanks to Andy Gibbs, to report the issue. llvm-svn: 155287
* HexagonISelLowering.cpp: Reorder #includes.NAKAMURA Takumi2012-04-211-1/+2
| | | | llvm-svn: 155286
* move Signals to .rodataNuno Lopes2012-04-211-1/+1
| | | | llvm-svn: 155283
* HexagonInstPrinter.cpp: Suppress -Wunused-variable warnings with -Asserts.NAKAMURA Takumi2012-04-211-6/+3
| | | | llvm-svn: 155281
* YAMLParser: silence warning about tautological comparison on unsigned-char ↵Benjamin Kramer2012-04-211-1/+1
| | | | | | | | platforms. No functionality change. llvm-svn: 155280
* ARM: tblgen'erate more NEON two-operand aliases.Jim Grosbach2012-04-201-39/+12
| | | | | | VMUL and VEXT. llvm-svn: 155258
* Fix PR12599.Jakob Stoklund Olesen2012-04-201-1/+6
| | | | | | | | The X86 target is editing the selection DAG while isel is selecting nodes following a topological ordering. When the DAG hacking triggers CSE, nodes can be deleted and bad things happen. llvm-svn: 155257
* ARM: tblgen'erate more NEON two-operand aliases.Jim Grosbach2012-04-201-153/+4
| | | | llvm-svn: 155254
* Revert r155241, which is causing some breakage.Bill Wendling2012-04-202-69/+20
| | | | llvm-svn: 155253
* Make ISelPosition a local variable.Jakob Stoklund Olesen2012-04-201-8/+25
| | | | | | | | | Now that multiple DAGUpdateListeners can be active at the same time, ISelPosition can become a local variable in DoInstructionSelection. We simply register an ISelUpdater with CurDAG while ISelPosition exists. llvm-svn: 155249
* Register DAGUpdateListeners with SelectionDAG.Jakob Stoklund Olesen2012-04-206-119/+87
| | | | | | | | | | | | | | | Instead of passing listener pointers to RAUW, let SelectionDAG itself keep a linked list of interested listeners. This makes it possible to have multiple listeners active at once, like RAUWUpdateListener was already doing. It also makes it possible to register listeners up the call stack without controlling all RAUW calls below. DAGUpdateListener uses an RAII pattern to add itself to the SelectionDAG list of active listeners. llvm-svn: 155248
* If we discover all of the named structs in a module, then don't bother toBill Wendling2012-04-202-20/+69
| | | | | | process any more Values. llvm-svn: 155241
* Print <def,read-undef> to avoid confusion.Jakob Stoklund Olesen2012-04-201-1/+5
| | | | | | | | The <undef> flag on a def operand only applies to partial register redefinitions. Only print the flag when relevant, and print it as <def,read-undef> to make it clearer what it means. llvm-svn: 155239
* New and improved comment.Andrew Trick2012-04-201-1/+1
| | | | llvm-svn: 155229
* SparseSet: Add support for key-derived indexes and arbitrary key types.Andrew Trick2012-04-202-3/+3
| | | | | | | | | | | | | | | | | | | This nicely handles the most common case of virtual register sets, but also handles anticipated cases where we will map pointers to IDs. The goal is not to develop a completely generic SparseSet template. Instead we want to handle the expected uses within llvm without any template antics in the client code. I'm adding a bit of template nastiness here, and some assumption about expected usage in order to make the client code very clean. The expected common uses cases I'm designing for: - integer keys that need to be reindexed, and may map to additional data - densely numbered objects where we want pointer keys because no number->object map exists. llvm-svn: 155227
* misched: initialize BBAndrew Trick2012-04-201-2/+4
| | | | llvm-svn: 155226
* ARM: Update NEON assembly two-operand aliases.Jim Grosbach2012-04-202-305/+14
| | | | | | | | Use the new TwoOperandAliasConstraint to handle lots of the two-operand aliases for NEON instructions. There's still more to go, but this is a good chunk of them. llvm-svn: 155210
* effectively back out my last change (r155190)Gabor Greif2012-04-201-2/+2
| | | | llvm-svn: 155195
* fix obviously bogus (IMO) operand index of the load in assertsGabor Greif2012-04-201-3/+3
| | | | | | | | | (load only has one operand) and smuggle in some whitespace changes too NB: I am obviously testing the water here, and believe that the unguarded cast is still wrong, but why is the getZExtValue of the load's operand tested against zero here? Any review is appreciated. llvm-svn: 155190
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-2031-296/+292
| | | | | | since they are equivalent. llvm-svn: 155188
* Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-2012-245/+244
| | | | | | since they are equivalent. llvm-svn: 155186
* Revert r155136 "Defer some shl transforms to DAGCombine."Jakob Stoklund Olesen2012-04-201-35/+39
| | | | | | | | | While the patch was perfect and defect free, it exposed a really nasty bug in X86 SelectionDAG that caused an llc crash when compiling lencod. I'll put the patch back in after fixing the SelectionDAG problem. llvm-svn: 155181
* ARM some VFP tblgen'erated two-operand aliases.Jim Grosbach2012-04-201-16/+8
| | | | llvm-svn: 155178
* ARM let TableGen handle a few two-operand aliases.Jim Grosbach2012-04-191-121/+9
| | | | | | No need for these explicit aliases anymore. Nuke 'em. llvm-svn: 155173
* Put this expensive check below the less expensive ones.Bill Wendling2012-04-191-9/+9
| | | | llvm-svn: 155166
* Avoid a bug in the path count computation, preventing an infiniteDan Gohman2012-04-191-1/+1
| | | | | | loop repeatedlt making the same change. This is for rdar://11256239. llvm-svn: 155160
* Defer some shl transforms to DAGCombine.Jakob Stoklund Olesen2012-04-191-39/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The shl instruction is used to represent multiplication by a constant power of two as well as bitwise left shifts. Some InstCombine transformations would turn an shl instruction into a bit mask operation, making it difficult for later analysis passes to recognize the constsnt multiplication. Disable those shl transformations, deferring them to DAGCombine time. An 'shl X, C' instruction is now treated mostly the same was as 'mul X, C'. These transformations are deferred: (X >>? C) << C --> X & (-1 << C) (When X >> C has multiple uses) (X >>? C1) << C2 --> X << (C2-C1) & (-1 << C2) (When C2 > C1) (X >>? C1) << C2 --> X >>? (C1-C2) & (-1 << C2) (When C1 > C2) The corresponding exact transformations are preserved, just like div-exact + mul: (X >>?,exact C) << C --> X (X >>?,exact C1) << C2 --> X << (C2-C1) (X >>?,exact C1) << C2 --> X >>?,exact (C1-C2) The disabled transformations could also prevent the instruction selector from recognizing rotate patterns in hash functions and cryptographic primitives. I have a test case for that, but it is too fragile. llvm-svn: 155136
* zap tabsGabor Greif2012-04-191-7/+7
| | | | llvm-svn: 155128
* Allow targets to select the default scheduler by name.Andrew Trick2012-04-191-0/+13
| | | | llvm-svn: 155090
* Fixed the llvm-mv X86 disassembler so the 'C' API gets jumps properlyKevin Enderby2012-04-181-2/+5
| | | | | | | symbolicated. These have and operand type of TYPE_RELv which was not handled as isBranch in translateImmediate() in X86Disassembler.cpp. rdar://11268426 llvm-svn: 155074
* Don't crash on code where the user put __attribute__((constructor)) onDan Gohman2012-04-181-1/+5
| | | | | | a function with arguments. This fixes rdar://11265785. llvm-svn: 155073
* This reverts a long string of commits to the Hexagon backend. TheseChandler Carruth2012-04-1837-12093/+2017
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commits have had several major issues pointed out in review, and those issues are not being addressed in a timely fashion. Furthermore, this was all committed leading up to the v3.1 branch, and we don't need piles of code with outstanding issues in the branch. It is possible that not all of these commits were necessary to revert to get us back to a green state, but I'm going to let the Hexagon maintainer sort that out. They can recommit, in order, after addressing the feedback. Reverted commits, with some notes: Primary commit r154616: HexagonPacketizer - There are lots of review comments here. This is the primary reason for reverting. In particular, it introduced large amount of warnings due to a bad construct in tablegen. - Follow-up commits that should be folded back into this when reposting: - r154622: CMake fixes - r154660: Fix numerous build warnings in release builds. - Please don't resubmit this until the three commits above are included, and the issues in review addressed. Primary commit r154695: Pass to replace transfer/copy ... - Reverted to minimize merge conflicts. I'm not aware of specific issues with this patch. Primary commit r154703: New Value Jump. - Primarily reverted due to merge conflicts. - Follow-up commits that should be folded back into this when reposting: - r154703: Remove iostream usage - r154758: Fix CMake builds - r154759: Fix build warnings in release builds - Please incorporate these fixes and and review feedback before resubmitting. Primary commit r154829: Hexagon V5 (floating point) support. - Primarily reverted due to merge conflicts. - Follow-up commits that should be folded back into this when reposting: - r154841: Remove unused variable (fixing build warnings) There are also accompanying Clang commits that will be reverted for consistency. llvm-svn: 155047
* LiveIntervalUpdate validators weren't recorded after the calls to ↵Pete Cooper2012-04-181-6/+6
| | | | | | std::for_each. Turns out std::for_each doesn't update the variable passed in for the functor but instead copy constructs a new one. llvm-svn: 155041
* SourceMgr: Colorize diagnostics.Benjamin Kramer2012-04-181-7/+41
| | | | | | Same color scheme as clang uses. The colors are only enabled if the output is a tty. llvm-svn: 155035
* Mark instruction classes ArithLogicR, ArithLogicI and LoadUpper as ↵Akira Hatanaka2012-04-181-1/+5
| | | | | | isRematerializable. llvm-svn: 155031
* Delete blank line.Akira Hatanaka2012-04-181-1/+0
| | | | llvm-svn: 155030
* Fix copy/paste-o.Jim Grosbach2012-04-181-1/+1
| | | | llvm-svn: 155016
* TableGen add warning diagnostic helper functions.Jim Grosbach2012-04-181-0/+16
| | | | llvm-svn: 155012
* Added support for disassembling unpredictable swp/swpb ARM instructions.Silviu Baranga2012-04-183-2/+7
| | | | llvm-svn: 155004
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