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* Remove extra whitespace. NFC. (test commit)David Spickett2018-09-281-1/+1
| | | | llvm-svn: 343301
* [ARM][v8.5A] Add speculation barriers SSBB and PSSBBOliver Stannard2018-09-284-1/+45
| | | | | | | | | | | This adds two new barrier instructions which can be used to restrict speculative execution of load instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52484 llvm-svn: 343300
* [X86][BtVer2] Fix PHMINPOS schedule resources typoSimon Pilgrim2018-09-281-1/+1
| | | | | | PHMINPOS can run on either JFPU pipe llvm-svn: 343299
* [CodeGen] fix broken successor probability in MBB dumpHiroshi Inoue2018-09-281-1/+1
| | | | | | | | | | When printing successor probabilities for a MBB, a human readable value is sometimes shown as 200.0%. The human readable output is based on getProbabilityIterator, which returns 0xFFFFFFFF for getNumerator() and 0x80000000 for getDenominator() for unknown BranchProbability. By using getSuccProbability as we do for the non-human readable part, we can avoid this problem. Differential Revision: https://reviews.llvm.org/D52605 llvm-svn: 343297
* [ScalarizeMaskedMemIntrin] Use MinAlign to calculate alignment for the ↵Craig Topper2018-09-281-2/+2
| | | | | | | | scalar load/stores to handle element types that are byte-sized but not powers of 2. This pass doesn't handle non-byte sized types correctly at all, but at least we can make byte sized types work. llvm-svn: 343294
* [pdb] Simplify the code by replacing a few string conversions with calls to ↵Aaron Smith2018-09-285-51/+11
| | | | | | | | | | | | invokeBstrMethod() Reviewers: aleksandr.urakov, zturner, llvm-commits Reviewed By: zturner Differential Revision: https://reviews.llvm.org/D52624 llvm-svn: 343291
* [ORC] clang-format the ThreadSafeModule code.Lang Hames2018-09-281-4/+4
| | | | | | Evidently I forgot to do this before committing r343055. llvm-svn: 343288
* [ScalarizeMaskedMemIntrin] Fix the alignment calculation for the scalar ↵Craig Topper2018-09-281-1/+1
| | | | | | | | stores of a masked store expansion. It should be the minimum of the original alignment and the scalar size. llvm-svn: 343284
* [ScalarizeMaskedMemIntrin] Ensure the mask is a vector of ConstantInts ↵Craig Topper2018-09-271-4/+19
| | | | | | | | before generating the expansion without control flow. Its possible the mask itself or one of the elements is a ConstantExpr and we shouldn't optimize in that case. llvm-svn: 343278
* [ScalarizeMaskedMemIntrin] Use cast instead of dyn_cast checked by an ↵Craig Topper2018-09-271-10/+6
| | | | | | | | assert. Consistently make use of the element type variable we already have. NFCI cast will take care of asserting internally. llvm-svn: 343277
* WebAssembly: Rename GetSignature to GetLibcallSignature [NFC]Derek Schuff2018-09-273-16/+19
| | | | llvm-svn: 343275
* [ScalarizeMaskedMemIntrin] When expanding masked gathers, start with the ↵Craig Topper2018-09-271-22/+11
| | | | | | | | passthru vector and insert the new load results into it. Previously we started with undef and did a final merge with the passthru at the end. llvm-svn: 343273
* [ScalarizeMaskedMemIntrin] When expanding masked loads, start with the ↵Craig Topper2018-09-271-22/+12
| | | | | | | | passthru value and insert each conditional load result over their element. Previously we started with undef and did one final merge at the end with a select. llvm-svn: 343271
* [ScalarizeMaskedMemIntrin] Handle the case where the mask is an all zero vector.Craig Topper2018-09-271-8/+8
| | | | | | | | This shouldn't really happen in practice I hope, but we tried to handle other constant cases. We missed this one because we checked for ConstantVector without realizing that zero becomes ConstantAggregateZero instead. So instead just check for Constant and use getAggregateElement which will do the dirty work for us. llvm-svn: 343270
* [ScalarizeMaskedMemIntrin] Remove some temporary variables that are only ↵Craig Topper2018-09-271-14/+5
| | | | | | used by a single if condition. llvm-svn: 343268
* [ScalarizeMaskedMemIntrin] Cleanup comments. NFCCraig Topper2018-09-271-58/+49
| | | | llvm-svn: 343267
* [ORC] Add definition for IRLayer::setCloneToNewContextOnEmit, use it to set theLang Hames2018-09-271-18/+24
| | | | | | | | | | | flag to true in LLJIT when running in multithreaded mode. The IRLayer::setCloneToNewContextOnEmit method sets a flag within the IRLayer that causes modules added to that layer to be moved to a new context (by serializing to/from a memory buffer) when they are emitted. This allows modules that were all loaded on the same context to be compiled in parallel. llvm-svn: 343266
* AMDGPU: Split HasExt into HasExtDPP/SDWA/SDWA9Konstantin Zhuravlyov2018-09-274-21/+43
| | | | llvm-svn: 343264
* AMDGPU: Split VOP2Inst into VOP2Inst_e32/e64/sdwaKonstantin Zhuravlyov2018-09-271-10/+32
| | | | llvm-svn: 343259
* [ORC] Coalesce all of ORC's symbol renaming / linkage-promotion utilities intoLang Hames2018-09-272-50/+16
| | | | | | | | | | | | one SymbolLinkagePromoter utility. SymbolLinkagePromoter renames anonymous and private symbols, and bumps all linkages to at least global/hidden-visibility. Modules whose symbols have been promoted by this utility can be decomposed into sub-modules without introducing link errors. This is used by the CompileOnDemandLayer to extract single-function modules for lazy compilation. llvm-svn: 343257
* AMDGPU/NFC: Simplify VOP_MAC_F16/F32Konstantin Zhuravlyov2018-09-271-11/+2
| | | | llvm-svn: 343254
* [AMDGPU] Fold copy (copy vgpr)Stanislav Mekhanoshin2018-09-271-0/+14
| | | | | | | | This allows to reduce a number of used VGPRs in some cases. Differential Revision: https://reviews.llvm.org/D52577 llvm-svn: 343249
* [ScalarizeMaskedMemIntrin] Don't emit 'icmp eq i1 %x, 1' to check mask ↵Craig Topper2018-09-271-23/+9
| | | | | | | | values. That's just %x so use that directly. Had we emitted this IR earlier, InstCombine would have removed icmp so I'm going to assume using the i1 directly would be considered canonical. llvm-svn: 343244
* [X86] Remove BT/BTC/BTR/BTS rr/ri overridesSimon Pilgrim2018-09-271-4/+3
| | | | llvm-svn: 343241
* [X86][Btver2] (V)MPSADBW instructions take 3uops not 1Simon Pilgrim2018-09-271-1/+1
| | | | llvm-svn: 343238
* Revert r343192 as an ubsan build is currently failingLuke Cheeseman2018-09-2714-82/+10
| | | | llvm-svn: 343235
* [X86][Btver2] BTC/BTR/BTS instructions take 2uops not 1Simon Pilgrim2018-09-271-1/+1
| | | | llvm-svn: 343234
* [X86] Split BT and BTC/BTR/BTS scheduler classesSimon Pilgrim2018-09-2711-28/+33
| | | | llvm-svn: 343233
* [Sparc] EXPENSIVE_CHECKS now passes all machine verifier errors (PR27461)Simon Pilgrim2018-09-271-4/+0
| | | | | | | | Now that D51487 has landed, the last machine verifier tests that failed EXPENSIVE_CHECKS builds have now been fixed/removed, so we can remove @MatzeB 's isMachineVerifierClean() hack for sparc targets. Differential Revision: https://reviews.llvm.org/D52612 llvm-svn: 343232
* [AArch64] Refactor immediate details out of add/sub tblgen class (NFCI)Oliver Stannard2018-09-271-13/+19
| | | | | | | | | | | | | | Bits [23-22] are used in Add and Sub to specify the shift. The value of the shift field must be 0x; values of 1x are unallocated. MTE adds some instructions that use such encodings, and this patch refactors the Add/Sub class so that another class could derive from this one to implement other encodings and other formats of bitfields. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52489 llvm-svn: 343231
* [AArch64][v8.5A] Add speculation barriers SSBB and PSSBBOliver Stannard2018-09-271-0/+2
| | | | | | | | | | | This adds two new barrier instructions which can be used to restrict speculative execution of load instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52483 llvm-svn: 343229
* [InstCombine] Without infinites, fold (C / X) < 0.0 --> (X < 0)Sanjay Patel2018-09-271-0/+55
| | | | | | | | | | | | | | | | | | | | When C is not zero and infinites are not allowed (C / X) > 0 is a sign test. Depending on the sign of C, the predicate must be swapped. E.g.: foo(double X) { if ((-2.0 / X) <= 0) ... } => foo(double X) { if (X >= 0) ... } Patch by: @marels (Martin Elshuber) Differential Revision: https://reviews.llvm.org/D51942 llvm-svn: 343228
* [X86][Btver2] BLSI/BLSMSK/BLSR instructions take 2uops not 1 (same as TZCNT)Simon Pilgrim2018-09-271-1/+1
| | | | llvm-svn: 343227
* [WPD] Fix incorrect devirtualization after indirect call promotionTeresa Johnson2018-09-273-46/+80
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a dominance check to ensure that the possible devirtualizable call is actually dominated by the type test/checked load intrinsic being analyzed. With PGO, after indirect call promotion is performed during the compile step, followed by inlining, we may have a type test in the promoted and inlined sequence that allows an indirect call in that sequence to be devirtualized. That indirect call (inserted by inlining after promotion) will share the same vtable pointer as the fallback indirect call that cannot be devirtualized. Before this patch the code was incorrectly devirtualizing the fallback indirect call. See the new test and the example described there for more details. Reviewers: pcc, vitalybuka Subscribers: mehdi_amini, Prazek, eraman, steven_wu, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D52514 llvm-svn: 343226
* [AArch64][v8.5A] Add Branch Target Identification instructionsOliver Stannard2018-09-2710-1/+139
| | | | | | | | | | | | This adds new instructions used by the Branch Target Identification feature. When this is enabled, these are the only instructions which can be targeted by indirect branch instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52485 llvm-svn: 343225
* [AArch64][v8.5A] Add speculation restriction system registersOliver Stannard2018-09-276-5/+32
| | | | | | | | | | | This adds some new system registers which can be used to restrict certain types of speculative execution. Patch by Pablo Barrio and David Spickett! Differential revision: https://reviews.llvm.org/D52482 llvm-svn: 343218
* [AArch64][v8.5A] Add Armv8.5-A random number instructionsOliver Stannard2018-09-273-0/+12
| | | | | | | | | | | | | This adds two new system registers, used to generate random numbers. This is an optional extension to v8.5-A, and will be controlled by the "+rng" modifier of the -march= and -mcpu= options. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52481 llvm-svn: 343217
* [AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instructionOliver Stannard2018-09-276-2/+13
| | | | | | | | | | | This adds a new variant of the DC system instruction for persistent memory. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52480 llvm-svn: 343216
* [AArch64][v8.5A] Add prediction invalidation instructions to AArch64Oliver Stannard2018-09-278-4/+89
| | | | | | | | | | | | This adds new system instructions which act as barriers to speculative execution based on earlier execution within a particular execution context. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52479 llvm-svn: 343214
* [ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction setsOliver Stannard2018-09-275-2/+32
| | | | | | | | | | | This is a new barrier which limits speculative execution of the instructions following it. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52477 llvm-svn: 343213
* [AArch64][v8.5A] Add speculation barrier to AArch64 instruction setOliver Stannard2018-09-273-2/+17
| | | | | | | | | | | This is a new barrier which limits speculative execution of the instructions following it. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52476 llvm-svn: 343211
* [Sparc] Remove the support for builtin setjmp/longjmpDaniel Cederman2018-09-273-270/+0
| | | | | | | | | | | | | | | | Summary: It is currently broken and for Sparc there is not much benefit in using a builtin version compared to a library version. Both versions needs to store the same four values in setjmp and flush the register windows in longjmp. If the need for a builtin setjmp/longjmp arises there is an improved implementation available at https://reviews.llvm.org/D50969. Reviewers: jyknight, joerg, venkatra Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D51487 llvm-svn: 343210
* [AArch64][v8.5A] Add FRINT[32,64][Z,X] instructionsOliver Stannard2018-09-274-3/+63
| | | | | | | | | | | | These are some new variants of the "Floating-point Round to Integral" family of instructions, which round to the nearest floating-point value which fits in a 32- or 64-bit integer. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52475 llvm-svn: 343209
* [Sparc] Add unimp aliasDaniel Cederman2018-09-271-0/+3
| | | | | | | | | | | | | Summary: Use 0 as the default immediate for the UNIMP instruction. This matches the behavior in gas. Reviewers: jyknight, venkatra Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D51526 llvm-svn: 343203
* [Sparc] Add support for the partial write PSR instructionDaniel Cederman2018-09-275-1/+26
| | | | | | | | | | | | | | | Summary: Partial write %PSR (WRPSR) is a SPARC V8e option that allows WRPSR instructions to only affect the %PSR.ET field. It is supported by the GR740 and GR716. Reviewers: jyknight, venkatra Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48644 llvm-svn: 343202
* [X86][Btver2] TZCNT instructions take 2uops not 1Simon Pilgrim2018-09-271-1/+1
| | | | llvm-svn: 343200
* [PowerPC] [NFC] Refactor code for printing register operandsNemanja Ivanovic2018-09-276-77/+72
| | | | | | | | | | | | | | | | | | | | | | | We have an unfortunate situation in our back end where we have to keep pairs of functions synchronized. Needless to say that this is not an ideal situation as it is very difficult to enforce. Even without bugs, it's annoying to have to do the same thing in two places. This patch just refactors the code so that the two pairs of those functions that pertain to printing register operands are unified: - stripRegisterPrefix() - this just removes the letter prefixes from registers for the InstrPrinter and AsmPrinter. This patch provides this as a static member of PPCRegisterInfo - Handling of PPCII::UseVSXReg - there are 3 places where we do something special for instructions with that flag set. Each of those places does its own checking of this flag and implements code customization. Any changes to how we print/encode VSX/VMX registers require modifying all 3 places. This patch unifies this into a static function in PPCInstrInfo that returns the register number adjusted as needed. Differential revision: https://reviews.llvm.org/D52467 llvm-svn: 343195
* [X86][Btver2] Add uops counter for exegesis reportsSimon Pilgrim2018-09-271-0/+1
| | | | llvm-svn: 343194
* Reapply changes reverted in r343114, lldb patch to follow shortlyLuke Cheeseman2018-09-2714-10/+82
| | | | llvm-svn: 343192
* Revert r342942 "[MachineCopyPropagation] Reimplement CopyTracker in terms of ↵Hans Wennborg2018-09-271-58/+54
| | | | | | | | | | | | | | | | register units" It seems to have broken several targets, see comments on the llvm-commits thread. > Change the copy tracker to keep a single map of register units instead > of 3 maps of registers. This gives a very significant compile time > performance improvement to the pass. I measured a 30-40% decrease in > time spent in MCP on x86 and AArch64 and much more significant > improvements on out of tree targets with more registers. > > Differential Revision: https://reviews.llvm.org/D52374 llvm-svn: 343189
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