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* fix typos; NFCSanjay Patel2015-06-251-4/+4
| | | | llvm-svn: 240699
* Use foreach loop over constant operands. NFC.Pete Cooper2015-06-255-14/+9
| | | | | | | A number of places had explicit loops over Constant::operands(). Just use foreach loops where possible. llvm-svn: 240694
* [InstCombine] call SimplifyICmpInst with correct contextJingyue Wu2015-06-251-2/+4
| | | | | | | | | | | | | | | | | | | | | Summary: Fixes PR23809. Without passing the context to SimplifyICmpInst, we would use the assume to prove that the condition feeding the assume is trivially true (see isValidAssumeForContext in ValueTracking.cpp), causing the removal of the assume which may be useful for later optimizations. Test Plan: pr23800.ll Reviewers: hfinkel, majnemer Reviewed By: hfinkel Subscribers: henryhu, llvm-commits, wengxt, broune, meheff, eliben Differential Revision: http://reviews.llvm.org/D10695 llvm-svn: 240683
* Diagnose undefined temporary symbols.Rafael Espindola2015-06-251-0/+5
| | | | | | | | | | | | We already disallowed .global .Lfoo so this is reasonable. This is a small cherry pick from r240130. llvm-svn: 240681
* Rangify for loop in Inliner.cpp. NFC.Yaron Keren2015-06-251-8/+5
| | | | llvm-svn: 240678
* DAGCombiner: Remove redundant checkMatt Arsenault2015-06-251-1/+1
| | | | | | | MemIntrinsicSDNode is already a subclass of MemSDNode, so the MemSDNode check is sufficient. llvm-svn: 240672
* GVN: If a branch has two identical successors, we cannot declare either dead.Peter Collingbourne2015-06-251-0/+4
| | | | | | | | | This previously caused miscompilations as a result of phi nodes receiving undef incoming values from blocks dominated by such successors. Differential Revision: http://reviews.llvm.org/D10726 llvm-svn: 240670
* [PPC] Implement vmrgew and vmrgow instructionsKit Barton2015-06-253-2/+154
| | | | | | | | | This patch adds support for the vector merge even word and vector merge odd word instructions introduced in POWER8. Phabricator review: http://reviews.llvm.org/D10704 llvm-svn: 240650
* [AsmPrinter] Fix crash in handleIndirectSymViaGOTPCRelBruno Cardoso Lopes2015-06-251-2/+9
| | | | | | | | | | | Check for symbols in MCValue before using them. Bail out early in case they are null. This fixes PR23779. Differential Revision: http://reviews.llvm.org/D10712 rdar://problem/21532830 llvm-svn: 240649
* Use computeSymbolSizes in llvm-symbolize.Rafael Espindola2015-06-251-1/+4
| | | | llvm-svn: 240646
* [PPC] Replace debug value skipping with getLastNonDebugInstr.Benjamin Kramer2015-06-251-16/+7
| | | | | | No functionality change intended. llvm-svn: 240641
* Replace copy-pasted debug value skipping with MBB::getLastNonDebugInstrBenjamin Kramer2015-06-254-48/+20
| | | | | | No functional change intended. llvm-svn: 240639
* [mips] [IAS] Refactor the emitDirectiveModuleFP() functions. NFC.Toma Tabacu2015-06-253-28/+25
| | | | | | | | | | | | | | | | | | | | Summary: Simplify emitDirectiveModuleFP() by having it just print the current information from MipsABIFlagsSection and doing an updateABIInfo() before such calls. This prevents us from forgetting to update the STI.FeatureBits, because updateABIInfo() uses those to update the MipsABIFlagsSection object, and also makes sure we use the update mechanism from MipsABIFlagsSection. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D10642 llvm-svn: 240637
* Take alignment into account in isSafeToLoadUnconditionallyArtur Pilipenko2015-06-251-6/+20
| | | | | | | | Reviewed By: hfinkel Differential Revision: http://reviews.llvm.org/D10475 llvm-svn: 240636
* [SystemZ] Only attempt RxSBG optimization for integer typesUlrich Weigand2015-06-251-2/+7
| | | | | | | | | | | | As pointed out by Justin Bogner (see r240520), SystemZDAGToDAGISel::Select currently attempts to convert boolean operations into RxSBG even on some non-integer types (in particular, vector types). This would not work in any case, and it happened to trigger undefined behaviour in allOnes. This patch verifies that we have a (<= 64-bit) integer type before attempting to perform this optimization. llvm-svn: 240634
* [mips] [IAS] Refactor the emitDirectiveModuleOddSPReg() functions. NFC.Toma Tabacu2015-06-254-22/+26
| | | | | | | | | | | | | | | | | | | Summary: We can simplify emitDirectiveModuleOddSPReg() by having it print the current OddSPReg information from MipsABIFlagsSection and doing an updateABIInfo() before such calls. This prevents us from forgetting to update the STI.FeatureBits, because updateABIInfo() uses those to update the MipsABIFlagsSection object, and also makes sure we use the update mechanism from MipsABIFlagsSection. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D10641 llvm-svn: 240630
* Teach LLVM about the PPC64 memory sanitizer implementation.Jay Foad2015-06-251-0/+17
| | | | | | | | | | | | | | | | Summary: This is the LLVM part of the PPC memory sanitizer implementation in D10648. Reviewers: kcc, samsonov, willschm, wschmidt, eugenis Reviewed By: eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10649 llvm-svn: 240627
* [mips] [IAS] Fix parsing of memory offset expressions with parenthesis depth >1.Toma Tabacu2015-06-252-2/+28
| | | | | | | | | | | | | | | | | | | Summary: In an expression such as "(((a+b)+c)+d)", parseParenExpression() would only parse the "a+b)+c", which would result in an error later on in the parser. This means that we can only parse one level of inner parentheses. In order to fix this, I added a new function called parseParenExprOfDepth(), which parses a specified number of trailing parenthesis expressions (except for the outermost parenthesis), and changed MipsAsmParser to use it in parseMemOffset instead of parseParenExpression(). Reviewers: dsanders, rafael Reviewed By: dsanders, rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9742 llvm-svn: 240625
* [X86] Accept hasAVX512() as well as hasFMA() when generating FMA.Ahmed Bougacha2015-06-251-3/+5
| | | | | | | | | | We don't always have FMA, for example when using 'clang -mavx512f' without an explicit CPU. Also check for an explicit +avx512f instead of CPUs in a couple related tests. llvm-svn: 240616
* Enable StackMap Serialization for COFFSwaroop Sridhar2015-06-252-0/+7
| | | | | | | | | | | | | | | | | | Summary This change turns on the emission of __LLVM_Stackmaps section when generating COFF binaries. Test Plan Added a scenario to the test case: test\CodeGen\X86\statepoint-stackmap-format.ll. Code Review: http://reviews.llvm.org/D10680 llvm-svn: 240613
* libObject/COFF: Add a function to get pointers to relocation entries.Rui Ueyama2015-06-251-0/+10
| | | | llvm-svn: 240610
* Add simplify_type<const WeakVH>; simplify IndVarSimplifyDuncan P. N. Exon Smith2015-06-241-4/+3
| | | | | | | | r240214 fixed some UB in IndVarSimplify, and it needed a temporary `WeakVH` to do it. Add `simplify_type<const WeakVH>` so that this temporary isn't necessary. llvm-svn: 240599
* [X86] Simplify some stuff in X86DisassemblerDecoder. NFCDouglas Katzman2015-06-241-22/+17
| | | | | | | | | | | | | | - Deciding that insn->sibIndex is SIB_INDEX_NONE does not require another check beyond the fully decoded bits being equal to 0x4. The expression insn->sibIndex == SIB_INDEX_sib could not have been true unless index were 0x4, because SIB_INDEX_sib is merely the range base (SIB_INDEX_EAX) plus 4. Respectively SIB_INDEX_sib64. - Don't use a switch statement to perform left-shift. Differential Revision: http://reviews.llvm.org/D9762 llvm-svn: 240598
* [GVN] Intersect the IR flags when CSE'ing two instructionsDavid Majnemer2015-06-241-7/+3
| | | | | | | | | We performed a simple, but incomplete, intersection when it came time to CSE instructions. It didn't handle, for example, the 'exact' flag. This fixes PR23922. llvm-svn: 240595
* [Reassociate] Don't propogate flags when creating negationsDavid Majnemer2015-06-241-0/+10
| | | | | | | | | Reassociate mutated existing instructions in order to form negations which would create additional reassociate opportunities. This fixes PR23926. llvm-svn: 240593
* fix typos; NFCSanjay Patel2015-06-241-3/+2
| | | | llvm-svn: 240592
* don't repeat function names in comments; NFCSanjay Patel2015-06-242-106/+91
| | | | llvm-svn: 240591
* [If Converter] Convert recursion to iteration.Akira Hatanaka2015-06-241-126/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit makes changes to IfConverter::AnalyzeBlock to use iteration instead of recursion. Previously, this function would get called recursively a large number of times and eventually segfault when a function with the following CFG was compiled: BB0: if (condition0) goto BB1 goto BB2 BB1: goto BB2 BB2: if (condition1) goto BB3 goto BB4 BB3: ... (repeat until BB7488) rdar://problem/21386145 Differential Revision: http://reviews.llvm.org/D10587 llvm-svn: 240589
* Devirtualize Instruction::clone_implPete Cooper2015-06-242-49/+57
| | | | llvm-svn: 240588
* Add NVPTXPeephole pass to reduce unnecessary address castJingyue Wu2015-06-246-16/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch first change the register that holds local address for stack frame to %SPL. Then the new NVPTXPeephole pass will try to scan the following pattern %vreg0<def> = LEA_ADDRi64 <fi#0>, 4 %vreg1<def> = cvta_to_local %vreg0 and transform it into %vreg1<def> = LEA_ADDRi64 %VRFrameLocal, 4 Patched by Xuetian Weng Test Plan: test/CodeGen/NVPTX/local-stack-frame.ll Reviewers: jholewinski, jingyue Reviewed By: jingyue Subscribers: eliben, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D10549 llvm-svn: 240587
* fix typos; NFCSanjay Patel2015-06-241-2/+2
| | | | llvm-svn: 240585
* ARMLoadStoreOptimizer: Fix errata 602117 handling and make testcase actually ↵Matthias Braun2015-06-241-107/+112
| | | | | | | | | | test for it This fixes PR23912 Differential Revision: http://reviews.llvm.org/D10620 llvm-svn: 240582
* Make computeSymbolSizes never fail.Rafael Espindola2015-06-243-15/+45
| | | | | | | | | | | On ELF that was already the case since getting the size of a symbol never fails. On MachO and COFF we could fail trying to get the section of a symbol. But we don't really need the section, just the section number to know if two symbols are in the same section or not. llvm-svn: 240580
* MIR Serialization: Serialize simple MachineRegisterInfo attributes.Alex Lorenz2015-06-242-0/+29
| | | | | | | | | | | | | This commit serializes the 3 scalar boolean attributes from the MachineRegisterInfo class: IsSSA, TracksRegLiveness, and TracksSubRegLiveness. These attributes are serialized as part of the machine function YAML mapping. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10618 llvm-svn: 240579
* Use Symbol::getValue to simplify object::computeSymbolSizes. NFC.Rafael Espindola2015-06-241-4/+2
| | | | llvm-svn: 240575
* [LSR] canonicalize Prod*(1<<C) to Prod<<CJingyue Wu2015-06-241-5/+12
| | | | | | | | | | | | | | | | | | | | | Summary: Because LSR happens at a late stage where mul of a power of 2 is typically canonicalized to shl, this canonicalization emits code that can be better CSE'ed. Test Plan: Transforms/LoopStrengthReduce/shl.ll shows how this change makes GVN more powerful. Fixes some existing tests due to this change. Reviewers: sanjoy, majnemer, atrick Reviewed By: majnemer, atrick Subscribers: majnemer, llvm-commits Differential Revision: http://reviews.llvm.org/D10448 llvm-svn: 240573
* Use Symbol.getValue to simplify RuntimeDyldCOFF::getSymbolOffset. NFC.Rafael Espindola2015-06-241-17/+2
| | | | llvm-svn: 240572
* Add a SymbolRef::getValue.Rafael Espindola2015-06-242-17/+24
| | | | | | | | | This returns either the symbol offset or address. Since it is not defined which one, it never has to lookup the section and so never fails. I will add users in the next commit. llvm-svn: 240569
* Devirtualize Constant::replaceUsesOfWithOnConstant.Pete Cooper2015-06-243-60/+85
| | | | | | | | | | | | | | | | | | | | This is part of the work to devirtualize Value. The old pattern was to call replaceUsesOfWithOnConstant which was overridden by subclasses. Those could then call replaceUsesOfWithOnConstantImpl on Constant to handle deleting the current value. To be consistent with other parts of the code, this has been changed so that we call the method on Constant, and that dispatches to an Impl on subclasses. As part of this, it made sense to rename the methods to be more descriptive. The new name is Constant::handleOperandChange, and it requires that all subclasses of Constant implement handleOperandChangeImpl, even if they just throw an error if they shouldn't be called. Reviewed by Duncan Exon Smith. llvm-svn: 240567
* AsmPrinter: Cleanup DIEValue::EmitValue() API, NFCDuncan P. N. Exon Smith2015-06-243-14/+13
| | | | | | | | | Stop taking a `dwarf::Form` in `DIEValue::EmitValue()` and `DIEValue::SizeOf()`, since they're always passed `DIEValue::getForm()` anyway. This is just left over from when `DIEValue` didn't know its own form. llvm-svn: 240566
* Refactor duplicated code. NFC.Rafael Espindola2015-06-241-27/+19
| | | | llvm-svn: 240563
* [CaptureTracking] Avoid long compilation time on large basic blocksBruno Cardoso Lopes2015-06-242-25/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CaptureTracking becomes very expensive in large basic blocks while calling PointerMayBeCaptured. PointerMayBeCaptured scans the BB the number of times equal to the number of uses of 'BeforeHere', which is currently capped at 20 and bails out with Tracker->tooManyUses(). The bottleneck here is the number of calls to PointerMayBeCaptured * the basic block scan. In a testcase with a 82k instruction BB, PointerMayBeCaptured is called 130k times, leading to 'shouldExplore' taking 527k runs, this currently takes ~12min. To fix this we locally (within PointerMayBeCaptured) number the instructions in the basic block using a DenseMap to cache instruction positions/numbers. We build the cache incrementally every time we need to scan an unexplored part of the BB, improving compile time to only take ~2min. This triggers in the flow: DeadStoreElimination -> MepDepAnalysis -> CaptureTracking. Side note: after multiple runs in the test-suite I've seen no performance nor compile time regressions, but could note a couple of compile time improvements: Performance Improvements - Compile Time Delta Previous Current StdDev SingleSource/Benchmarks/Misc-C++/bigfib -4.48% 0.8547 0.8164 0.0022 MultiSource/Benchmarks/TSVC/LoopRerolling-dbl/LoopRerolling-dbl -1.47% 1.3912 1.3707 0.0056 Differential Revision: http://reviews.llvm.org/D7010 llvm-svn: 240560
* MIR Serialization: Serialize the null register operands.Alex Lorenz2015-06-244-4/+16
| | | | | | | | | | | | This commit serializes the null register machine operands. It uses the '_' keyword to represent them, but the parser also allows the '%noreg' named register syntax. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10580 llvm-svn: 240558
* [LoopVectorizer] Fix bailing-out condition for OptForSize case.Michael Zolotukhin2015-06-241-4/+3
| | | | | | | | | | With option OptForSize enabled, the Loop Vectorizer is not supposed to create tail loop. The condition checking that was invalid and was not matching to the comment above. Patch by Marianne Mailhot-Sarrasin. llvm-svn: 240556
* Simplify the logic, NFC.Rafael Espindola2015-06-241-12/+8
| | | | llvm-svn: 240554
* Eliminate additional redundant copies of Triple objects. NFC.Daniel Sanders2015-06-242-2/+2
| | | | | | | | Subscribers: rafael, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10654 llvm-svn: 240540
* Fix instruction scheduling live register trackingPawel Bylica2015-06-241-8/+17
| | | | | | | | | | | | | | | | | | | Summary: This patch fixes PR23405 (https://llvm.org/bugs/show_bug.cgi?id=23405). During a node unscheduling an entry in LiveRegGens can be replaced with a new value. That corrupts the live reg tracking and LiveReg* structure is not cleared as should be during unscheduling. Problematic condition that enforces Gen replacement is `I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight()`. This condition should be checked only if LiveRegGen was set in current node unscheduling. Test Plan: Regression test included. Reviewers: hfinkel, atrick Reviewed By: atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9993 llvm-svn: 240538
* [mips][microMIPS] Implement BREAK, EHB and EI instructionsZoran Jovanovic2015-06-244-2/+63
| | | | | | http://reviews.llvm.org/D10090 llvm-svn: 240531
* Change how symbol sizes are handled in lib/Object.Rafael Espindola2015-06-247-32/+25
| | | | | | | | | | | | | | COFF and MachO only define symbol sizes for common symbols. Reflect that in the class hierarchy by having a method for common symbols only in the base and a general one in ELF. This avoids the need of using a magic value for the size, which had a few problems * Most callers didn't check for it. * The ones that did could not tell the magic value from a file actually having that value. llvm-svn: 240529
* Hexagon: Paper over the undefined behaviour introduced by r238692Justin Bogner2015-06-242-1/+3
| | | | | | | | | | | | | | | | This stops shifting a 32-bit value by such absurd amounts as 96 and 120. We do this by dropping a call to the function that was doing this entirely, which rather surprisingly doesn't break *any* tests. I've also added an assert in the misbehaving function to prove that it's no longer being called with completely invalid arguments. This change looks pretty bogus and we should probably be reverting r238692 instead, but this is hard to do with the number of follow ups that have happened since. It can't be any worse than the undefined behaviour that was happening before though. llvm-svn: 240526
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