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* Be more forgiving when calculating alias interference for physreg coalescing.Jakob Stoklund Olesen2010-07-063-105/+59
| | | | | | | | | | | | It is OK for an alias live range to overlap if there is a copy to or from the physical register. CoalescerPair can work out if the copy is coalescable independently of the alias. This means that we can join with the actual destination interval instead of using the getOrigDstReg() hack. It is no longer necessary to merge clobber ranges into subregisters. llvm-svn: 107695
* Reapply r107655 with fixes; insert the pseudo instruction intoDan Gohman2010-07-0614-212/+275
| | | | | | | the block before calling the expansion hook. And don't put EFLAGS in a mbb's live-in list twice. llvm-svn: 107691
* Fix to 80-col.Eric Christopher2010-07-061-21/+21
| | | | llvm-svn: 107684
* Fix PR7545 crash.Devang Patel2010-07-061-3/+3
| | | | llvm-svn: 107678
* Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversionRafael Espindola2010-07-061-4/+6
| | | | | | if profitable. llvm-svn: 107673
* tighten up this code.Chris Lattner2010-07-061-12/+7
| | | | llvm-svn: 107670
* Revert r107655.Dan Gohman2010-07-0613-269/+209
| | | | llvm-svn: 107668
* Add versions of OutputArgReg, AnalyzeReturn, and AnalyzeCallOperandsDan Gohman2010-07-061-0/+35
| | | | | | which do not depend on SelectionDAG. llvm-svn: 107666
* Make getMinimalPhysRegClass' comment mention what makes it differentDan Gohman2010-07-061-1/+2
| | | | | | from getPhysicalRegisterRegClass. llvm-svn: 107660
* Fix a major regression on COFF targets introduced by r103267: 'discardable' ↵Anton Korobeynikov2010-07-061-1/+1
| | | | | | | | section means that it is used only during the program load and can be discarded afterwards. This way *only* debug sections can be discarded, but not the opposite. Seems like the copy-and-pasto from ELF code, since there it contains the reverse flag ('alloc'). llvm-svn: 107658
* Add some more TODO comments.Dan Gohman2010-07-061-0/+6
| | | | llvm-svn: 107657
* Add a comment.Dan Gohman2010-07-061-1/+2
| | | | llvm-svn: 107656
* Fix a bunch of custom-inserter functions to handle the case whereDan Gohman2010-07-0613-209/+269
| | | | | | the pseudo instruction is not at the end of the block. llvm-svn: 107655
* Fix up -fstack-protector on linux to use the segmentEric Christopher2010-07-063-2/+42
| | | | | | | | | registers. Split out testcases per architecture and os now. Patch from Nelson Elhage. llvm-svn: 107640
* Detabify this file.Nick Lewycky2010-07-061-7/+7
| | | | llvm-svn: 107637
* Have the X86 backend use Triple instead of a string and some enums.Eric Christopher2010-07-053-64/+38
| | | | llvm-svn: 107625
* Remove some unused/redundant code.Kalle Raiskila2010-07-052-20/+0
| | | | llvm-svn: 107622
* more tidying.Chris Lattner2010-07-052-10/+5
| | | | llvm-svn: 107615
* some notes about suboptimal insertps'sChris Lattner2010-07-051-0/+31
| | | | llvm-svn: 107613
* random tidyingChris Lattner2010-07-052-41/+43
| | | | llvm-svn: 107612
* rip out even more sporadic v2f32 support.Chris Lattner2010-07-053-19/+1
| | | | llvm-svn: 107610
* rip out the various v2f32 "mmx" handling logic, now that Chris Lattner2010-07-051-6/+6
| | | | | | v2f32 is illegal on x86. llvm-svn: 107609
* Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG.Jakob Stoklund Olesen2010-07-041-0/+2
| | | | llvm-svn: 107602
* Just rip v2f32 support completely out of the X86 backend. InChris Lattner2010-07-041-23/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the example in the testcase, we now generate: _test1: ## @test1 movss 4(%esp), %xmm0 addss 8(%esp), %xmm0 movl 12(%esp), %eax movss %xmm0, (%eax) ret instead of: _test1: ## @test1 subl $20, %esp movl 24(%esp), %eax movq %mm0, (%esp) movq %mm0, 8(%esp) movss (%esp), %xmm0 addss 12(%esp), %xmm0 movss %xmm0, (%eax) addl $20, %esp ret v2f32 support did not work reliably because most of the X86 backend didn't know it was legal. It was apparently only added to support returning source-level v2f32 values in MMX registers in x86-32 mode. If ABI compatibility is important on this GCC-extended-vector type for some reason, then the frontend should generate IR that returns v2i32 instead of v2f32. However, we generally don't try very hard to be abi compatible on gcc extended vectors. llvm-svn: 107601
* fix PR7518 - terrible codegen of <2 x float>, by only markingChris Lattner2010-07-041-6/+16
| | | | | | | | v2f32 as legal in 32-bit mode. It is just as terrible there, but I just care about x86-64 and noone claims it is valuable in 64-bit mode. llvm-svn: 107600
* indentationChris Lattner2010-07-041-2/+3
| | | | llvm-svn: 107599
* Infer alignments of fixed frame objects when they are constructed. This ↵Evan Cheng2010-07-042-18/+7
| | | | | | ensures remat'ed loads from fixed slots have the right alignments. llvm-svn: 107591
* Revert r107583. I no longer think that this is the way to solve the problem.Bill Wendling2010-07-041-2/+2
| | | | llvm-svn: 107585
* Mark sse_load_f32 and sse_load_f64 as having memory operandsBill Wendling2010-07-041-2/+2
| | | | | | | (SDNPMemOperand). This way when they're morphed the memory operands will be copied as well. llvm-svn: 107583
* Proper indentation.Bill Wendling2010-07-041-1/+1
| | | | llvm-svn: 107581
* Minor amendment to switch-lowering improvement.Eli Friedman2010-07-031-2/+10
| | | | llvm-svn: 107569
* Note switch-lowering inefficiency.Eli Friedman2010-07-031-0/+36
| | | | llvm-svn: 107565
* Add AVX SSE4.1 blend, mpsadbw and vdpBruno Cardoso Lopes2010-07-031-0/+19
| | | | llvm-svn: 107560
* Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructionsBruno Cardoso Lopes2010-07-031-0/+26
| | | | llvm-svn: 107558
* Fix typo.Eric Christopher2010-07-031-1/+1
| | | | llvm-svn: 107556
* Add AVX SSE4.1 Horizontal Minimum and Position instructionBruno Cardoso Lopes2010-07-031-0/+3
| | | | llvm-svn: 107552
* Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill ↵Evan Cheng2010-07-0318-70/+56
| | | | | | slots so it's always false. llvm-svn: 107550
* Add AVX SSE4.1 round instructionsBruno Cardoso Lopes2010-07-031-0/+76
| | | | llvm-svn: 107549
* Detect and handle COPY in many places.Jakob Stoklund Olesen2010-07-039-40/+67
| | | | | | | This code is transitional, it will soon be possible to eliminate isExtractSubreg, isInsertSubreg, and isMoveInstr in most places. llvm-svn: 107547
* Simple refactoring of SSE4.1 instructions, making room for the AVX formsBruno Cardoso Lopes2010-07-021-151/+117
| | | | llvm-svn: 107540
* 80-col fixup.Eric Christopher2010-07-021-1/+2
| | | | llvm-svn: 107537
* Add a new target independent COPY instruction and code to lower it.Jakob Stoklund Olesen2010-07-021-0/+49
| | | | | | | | | | | The COPY instruction is intended to replace the target specific copy instructions for virtual registers as well as the EXTRACT_SUBREG and INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection DAG. COPY is lowered to native register copies by LowerSubregs. llvm-svn: 107529
* - Add support for the rest of AVX SSE3 instructionsBruno Cardoso Lopes2010-07-022-19/+89
| | | | | | | - Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M represents a REX equivalent two byte leading opcode llvm-svn: 107523
* Custom inserters (e.g., conditional moves in Thumb1 can introduceJim Grosbach2010-07-021-1/+14
| | | | | | | | | | | | new basic blocks, and if used as a function argument, that can cause call frame setup / destroy pairs to be split across a basic block boundary. That prevents us from doing a simple assertion to check that the pairs match and alloc/ dealloc the same amount of space. Modify the assertion to only check the amount allocated when there are matching pairs in the same basic block. rdar://8022442 llvm-svn: 107517
* MDString is already checked earlier.Devang Patel2010-07-021-1/+1
| | | | llvm-svn: 107516
* Remove early IT block formation. It's not used.Evan Cheng2010-07-023-213/+6
| | | | llvm-svn: 107513
* - Two-address pass should not assume unfolding is always successful.Evan Cheng2010-07-022-12/+27
| | | | | | | | | - X86 unfolding should check if the instructions being unfolded has memoperands. If there is no memoperands, then it must assume conservative alignment. If this would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand etc. should not unfold the instruction. llvm-svn: 107509
* Propagate the AlignStack bit in InlineAsm's to the Dale Johannesen2010-07-026-12/+23
| | | | | | | | | | | | | | | | | | | PrologEpilog code, and use it to determine whether the asm forces stack alignment or not. gcc consistently does not do this for GCC-style asms; Apple gcc inconsistently sometimes does it for asm blocks. There is no convenient place to put a bit in either the SDNode or the MachineInstr form, so I've added an extra operand to each; unlovely, but it does allow for expansion for more bits, should we need it. PR 5125. Some existing testcases are affected. The operand lists of the SDNode and MachineInstr forms are indexed with awesome mnemonics, like "2"; I may fix this someday, but not now. I'm not making it any worse. If anyone is inspired I think you can find all the right places from this patch. llvm-svn: 107506
* Remove invalid assertJakob Stoklund Olesen2010-07-021-1/+0
| | | | llvm-svn: 107505
* Properly handle debug values during inline spilling.Jakob Stoklund Olesen2010-07-021-13/+32
| | | | llvm-svn: 107503
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