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* [IR] andIRFlags and copyIRFlags needs to handle GEPDavid Majnemer2016-07-151-0/+8
| | | | | | | | | We didn't consider the inbounds flag on GEPs leading to downstream users introducing UB. This fixes PR28562. llvm-svn: 275532
* [Coverage] Mark a few more methods const (NFC)Vedant Kumar2016-07-151-4/+4
| | | | llvm-svn: 275514
* AMDGPU: Fix not expanding control flow after some kill blocksMatt Arsenault2016-07-151-7/+2
| | | | | | | | | | | | | Also stop trying to insert skip blocks at end_cf. This was inserting them at the end of the block which doesn't make sense. The skip should be inserted at the beginning of the block right after the end cf. Just remove this for now since no tests seem to stress this and I think this can be handled more generally later. Fixes bug 28550 llvm-svn: 275510
* AMDGPU: Fix trying to skip from a block with no successorsMatt Arsenault2016-07-151-2/+3
| | | | | | Found while reducing bug 28550 llvm-svn: 275509
* AMDGPU: Fix splitting kill blocks with defs before killMatt Arsenault2016-07-151-13/+3
| | | | llvm-svn: 275508
* [AArch64] Set COPY ZR isAsCheapAsAMove when needed.Haicheng Wu2016-07-151-2/+6
| | | | | | | | | If a subtarget has both ZCZeroing and CustomCheapAsMoveHandling features (now only Kryo has both), set COPY (W|X)ZR isAsCheapAsAMove. Differential Revision: http://reviews.llvm.org/D22360 llvm-svn: 275503
* [codeview] Shrink inlined call site line info tablesReid Kleckner2016-07-142-5/+14
| | | | | | | | | | | For a fully inlined call chain like a -> b -> c -> d, we were emitting line info for 'd' 3 separate times: once for d's actual InlineSite line table, and twice for 'b' and 'c'. This is particularly inefficient when all these functions are in different headers, because now we need to encode the file change. Windbg was coping with our suboptimal output, so this should not be noticeable from the debugger. llvm-svn: 275502
* [X86][AVX2] Allow VPERMPD/VPERMQ shuffles to call combineShuffle (reapplied)Simon Pilgrim2016-07-141-0/+1
| | | | | | | | This improves the situation discussed in D19228 where we were forcing VPERMPD/VPERMQ where VPERM2F128/VPERM2I128 would have been better. This was incorrectly reverted in rL275421 during triage of PR28552. llvm-svn: 275497
* [LoopDist] Fix typo in diagnosticAdam Nemet2016-07-141-1/+1
| | | | llvm-svn: 275495
* [GVN] Fold constant expression in GVN.Ekaterina Romanova2016-07-141-22/+33
| | | | | | | | | | | Fix for PR 28418. opt never finishes compiling a test when -gvn option is passed. The problem is caused by the fact that GVN fails to fold a constant expression. Differential Revision: https://reviews.llvm.org/D22185 llvm-svn: 275483
* Move legacy LTO interface headers to legacy/ directory.Peter Collingbourne2016-07-144-6/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D22173 llvm-svn: 275476
* [LV] Rename StrideAccesses to AccessStrideInfo (NFC)Matthew Simpson2016-07-141-12/+12
| | | | | | | We now collect all accesses with a constant stride, not just the ones with a stride greater than one. This change was requested in the review of D19984. llvm-svn: 275473
* [LV] Allow interleaved accesses in loops with predicated blocksMatthew Simpson2016-07-141-34/+30
| | | | | | | | | | This patch allows the formation of interleaved access groups in loops containing predicated blocks. However, the predicated accesses are prevented from forming groups. Differential Revision: https://reviews.llvm.org/D19694 llvm-svn: 275471
* don't repeat function names in comments; NFCSanjay Patel2016-07-141-29/+28
| | | | llvm-svn: 275470
* [Object] Change Archive::findSym to return an Expected<Optional<Child>>.Lang Hames2016-07-143-21/+18
| | | | | | | As suggested by Rafael in review of D22079 - this was accidentally left out of the final commit (r275316). llvm-svn: 275469
* [SCCP] Pass the Solver by reference, copies are expensive ...Davide Italiano2016-07-141-2/+2
| | | | | | | | .. enough to cause LTO compile time to regress insanely. Thanks *a lot* to Rafael for reporting the problem and testing the fix! llvm-svn: 275468
* [ValueTracking] Use Instruction::getFunction; NFCSanjoy Das2016-07-141-4/+2
| | | | llvm-svn: 275465
* s/constexpr/LLVM_CONSTEXPR in AArch64InstrInfo.cpp.Justin Lebar2016-07-141-1/+1
| | | | | | Yet again. llvm-svn: 275463
* [Hexagon] Packetize function call arguments with tail call instructionsKrzysztof Parzyszek2016-07-143-1/+13
| | | | | | | | On Hexagon is it legal to packetize the instructions setting up call arguments with the call instruction itself. This was already done, except for tail calls. Make sure tail calls are handled as well. llvm-svn: 275458
* [AArch64] Adjust the scheduling model for Exynos-M1.Evandro Menezes2016-07-141-0/+1
| | | | | | Enable use-postra-scheduler. (NFC) llvm-svn: 275457
* [JumpThreading] PRE unordered loadsSanjoy Das2016-07-141-5/+6
| | | | | | | | | | | | Summary: Extend JumpThreading's PRE to unordered atomic loads. Reviewers: hfinkel, reames Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D22326 llvm-svn: 275456
* Add debugging code to the packetizerKrzysztof Parzyszek2016-07-141-0/+25
| | | | llvm-svn: 275455
* [PM] Port Dead Loop Deletion Pass to the new PMJun Bum Lim2016-07-144-58/+75
| | | | | | | | | | | | Summary: Port Dead Loop Deletion Pass to the new pass manager. Reviewers: silvas, davide Subscribers: llvm-commits, sanjoy, mcrosier Differential Revision: https://reviews.llvm.org/D21483 llvm-svn: 275453
* [CodeGen] Refactor MachineMemOperand::Flags's target-specific flags.Justin Lebar2016-07-143-23/+7
| | | | | | | | | | | | | | | | | Summary: Make the target-specific flags in MachineMemOperand::Flags real, bona fide enum values. This simplifies users, prevents various constants from going out of sync, and avoids the false sense of security provided by declaring static members in classes and then forgetting to define them inside of cpp files. Reviewers: MatzeB Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22372 llvm-svn: 275451
* [sanitizer-coverage] make sure that calls to __sanitizer_cov_trace_pc are ↵Kostya Serebryany2016-07-141-1/+2
| | | | | | not merged (otherwise different calls get the same PC and confuse fuzzers) llvm-svn: 275449
* [X86][MC] Fix bracket expression parsing in intel-style assembly.Nirav Dave2016-07-141-2/+5
| | | | | | | | | | | | | | Only perform struct field check on Identifier tokens. Fixes PR28547. Reviewers: rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22361 llvm-svn: 275445
* X86: handle external tail calls in Windows JITSaleem Abdulrasool2016-07-141-2/+4
| | | | | | | | | | If there was a tail call, we would incorrectly handle the relocation. It would end up indexing into the array with an incorrect section id. The symbol was external to the module, so the Section ID was UNDEFINED (-1). We would then index the SmallVector with this ID, triggering an assertion. Use the Value rather than the section load address in this case. llvm-svn: 275442
* [CodeGen] Refactor MachineMemOperand's Flags enum.Justin Lebar2016-07-143-10/+15
| | | | | | | | | | | | | | | | | | | | | | | | Summary: - Give it a shorter name (because we're going to refer to it often from SelectionDAG and friends). - Split the flags and alignment into separate variables. - Specialize FlagsEnumTraits for it, so we can do bitwise ops on it without losing type information. - Make some enum values constants in MachineMemOperand instead. MOMaxBits should not be a valid Flag. - Simplify some of the bitwise ops for dealing with Flags. Reviewers: chandlerc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D22281 llvm-svn: 275438
* ARM: fix vmov.i64 immediate validity checkTim Northover2016-07-141-1/+1
| | | | | | Typo meant we were only checking the low byte (repeatedly). llvm-svn: 275437
* GlobalsAA: Functions with the argmemonly attribute won't read arbitrary globalsTom Stellard2016-07-141-1/+1
| | | | | | | | | | | | | | | | | Summary: In preparation for changing GlobalsAA to stop assuming that intrinsics can't read arbitrary globals, we need to make sure GlobalsAA is querying function attributes rather than relying on this assumption. This patch was inspired by: http://reviews.llvm.org/D20206 Reviewers: jmolloy, hfinkel Subscribers: eli.friedman, llvm-commits Differential Revision: https://reviews.llvm.org/D21318 llvm-svn: 275433
* Don't optimize movs to pushes in -O0 builds.Nico Weber2016-07-141-1/+1
| | | | | | https://reviews.llvm.org/D22362 llvm-svn: 275431
* Delete some trailing whitespace.Nico Weber2016-07-141-2/+2
| | | | llvm-svn: 275429
* [X86] Decode MPX BND registers.Ahmed Bougacha2016-07-142-4/+15
| | | | | | | | | | | | | We were able to assemble, but not disassemble. Note that fixupRMValue was truncating EA_REG_BND0-3 because we hit the uint8_t max. The control registers were already squarely above it, but I don't think they ever go in .r/m, only in .reg. I also did notice an extra REX.W in our encoding, but I think that's fine. llvm-svn: 275427
* [X86] Don't mark addressing mode operands as "outs". NFC-ish.Ahmed Bougacha2016-07-141-12/+12
| | | | | | | Nothing in-tree can tell the difference, but it's incorrect: the addressing mode registers aren't what's defined. llvm-svn: 275426
* [TableGen] Autobrief-ize Record. NFC.Ahmed Bougacha2016-07-141-2/+2
| | | | llvm-svn: 275425
* [TableGen] Cleanup Record comments. NFC.Ahmed Bougacha2016-07-141-65/+1
| | | | | | | LLVM doesn't use exceptions anymore. Also remove the implementation comments. Some of them diverged. llvm-svn: 275424
* [GlobalISel] Fix #include ordering/spacing. NFC.Ahmed Bougacha2016-07-142-3/+2
| | | | llvm-svn: 275423
* [AMDGPU] Assembler: fix row_bcast parsingSam Kolton2016-07-141-0/+2
| | | | | | | | | | | | Summary: This change fix bug 28538 Reviewers: tstellarAMD, vpykhtin Subscribers: arsenm, kzhuravl Differential Revision: https://reviews.llvm.org/D22355 llvm-svn: 275422
* Revert r275411, it cause PR28552.Nico Weber2016-07-141-1/+0
| | | | llvm-svn: 275421
* Revert r275401, it caused PR28551.Nico Weber2016-07-145-828/+0
| | | | llvm-svn: 275420
* [LV] Avoid unnecessary IV scalar-to-vector-to-scalar conversionsMatthew Simpson2016-07-141-45/+69
| | | | | | | | | | | | This patch prevents increases in the number of instructions, pre-instcombine, due to induction variable scalarization. An increase in instructions can lead to an increase in the compile-time required to simplify the induction variables. We now maintain a new map for scalarized induction variables to prevent us from converting between the scalar and vector forms. This patch should resolve compile-time regressions seen after r274627. llvm-svn: 275419
* Teach fast isel calls and rets about stdcall.Nico Weber2016-07-141-0/+2
| | | | | | | stdcall is callee-pop like thiscall, so the thiscall changes already did most of the work for this. This change only opts stdcall in and adds tests. llvm-svn: 275414
* Remove trailing whitespace.Simon Pilgrim2016-07-141-1/+1
| | | | llvm-svn: 275412
* [X86][AVX2] Allow VPERMPD/VPERMQ shuffles to call combineShuffleSimon Pilgrim2016-07-141-0/+1
| | | | | | This improves the situation discussed in D19228 where we were forcing VPERMPD/VPERMQ where VPERM2F128/VPERM2I128 would have been better. llvm-svn: 275411
* [mips] SelectionDAGISel subclasses now follow the optimization level.Daniel Sanders2016-07-146-13/+18
| | | | | | | | | | | | | | | | Summary: It was recently discovered that, for Mips's SelectionDAGISel subclasses, all optimization levels caused SelectionDAGISel to behave like -O2. This change adds the necessary plumbing to initialize the optimization level. Reviewers: andrew.w.kaylor Subscribers: andrew.w.kaylor, sdardis, dean, llvm-commits, vradosavljevic, petarj, qcolombet, probinson, dsanders Differential Revision: https://reviews.llvm.org/D14900 llvm-svn: 275410
* [X86][AVX] Add support for narrowing 128-bit+ shuffle mask elements to ↵Simon Pilgrim2016-07-141-14/+25
| | | | | | | | 64-bits to allow combining Primarily this is to allow blend with zero instead of having to use vperm2f128, but we can use this in the future to deal with AVX512 cases where we need to keep the original element size to correctly fold masked operations. llvm-svn: 275406
* This converts a signed remainder instruction to unsigned remainder, whichSjoerd Meijer2016-07-141-15/+38
| | | | | | | | | | enables the code size optimisation to fold a rem and div into a single aeabi_uidivmod call. This was not happening before because sdiv was converted but srem not, and instructions with different signedness are not combined. Differential Revision: http://reviews.llvm.org/D22214 llvm-svn: 275403
* code hoisting pass based on GVNSebastian Pop2016-07-145-0/+828
| | | | | | | | | | | | | This pass hoists duplicated computations in the program. The primary goal of gvn-hoist is to reduce the size of functions before inline heuristics to reduce the total cost of function inlining. Pass written by Sebastian Pop, Aditya Kumar, Xiaoyu Hu, and Brian Rzycki. Important algorithmic contributions by Daniel Berlin under the form of reviews. Differential Revision: http://reviews.llvm.org/D19338 llvm-svn: 275401
* [X86][AVX] Add VBROADCASTF128/VBROADCASTI128 shuffle comments supportSimon Pilgrim2016-07-143-0/+23
| | | | llvm-svn: 275400
* Remove extra ';' to appease -WpedanticDean Michael Berris2016-07-141-1/+1
| | | | | | | | | Summary: Reviewers: dok Subscribers: llvm-commits llvm-svn: 275399
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