summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* [X86][AVX512] Updated shuffle comments instruction macros to split writemask ↵Simon Pilgrim2016-05-111-40/+46
| | | | | | | | instructions. NFC This will make it easier to support the different writemask cases in shuffle comments llvm-svn: 269174
* [mips][micromips] Implement DSBH, DSHD, DSLL, DSLL32, DSLLV, DSRA, DSRA32 ↵Hrvoje Varga2016-05-113-12/+160
| | | | | | | | and DSRAV instructions Differential Revision: http://reviews.llvm.org/D16800 llvm-svn: 269169
* Replace PrintLinkage with getLinkagePrintName. NFC.Rafael Espindola2016-05-111-17/+25
| | | | llvm-svn: 269155
* [AArch64] Fix DAG selection for cmps for fp16 typeWeiming Zhao2016-05-111-0/+1
| | | | | | | | | | | | Summary: When emitting comparison for fp16, in addition to promote the LHS and RHS to fp32, we need to change the VT as well. Reviewers: t.p.northover Subscribers: t.p.northover, aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D19922 llvm-svn: 269151
* Delete mayBeOverridden.Rafael Espindola2016-05-111-1/+1
| | | | | | It is the same as isInterposable which seems to be the preferred name. llvm-svn: 269150
* AMDGPU: Make some instructions convergentMatt Arsenault2016-05-111-1/+7
| | | | llvm-svn: 269147
* [PGO] Use WeakAny linkage for __llvm_profile_raw_versionRong Xu2016-05-111-1/+1
| | | | | | | Use WeakAny linkage instead of LinkOnceAny, as the symbol can be removed with LinkOnceAny in O2 (not referenced). llvm-svn: 269146
* AMDGPU: Change private_element_size to 4Matt Arsenault2016-05-111-1/+1
| | | | llvm-svn: 269145
* SDAG: Implement Select instead of SelectImpl in X86Justin Bogner2016-05-101-31/+26
| | | | | | | This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 269144
* [libFuzzer] add a driver file to use AFL on LLVMFuzzerTestOneInputKostya Serebryany2016-05-101-0/+82
| | | | llvm-svn: 269141
* [libfuzzer] Refactoring coverage state-management code.Mike Aizatsky2016-05-104-116/+206
| | | | | | | | | It is now less state-dependent and will allow easier comparing of coverages of different units. Differential Revision: http://reviews.llvm.org/D20085 llvm-svn: 269140
* Revert r269131Easwaran Raman2016-05-103-49/+3
| | | | llvm-svn: 269138
* Propagate branch metadata when some branch probability is missing.Dehao Chen2016-05-101-5/+13
| | | | | | | | | | | | Summary: In sample profile, some branches may have profile missing due to profile inaccuracy. We want existing branch probability still valid after propagation. Reviewers: hfinkel, davidxl, spatel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19948 llvm-svn: 269137
* SDAG: Make SelectCodeCommon return voidJustin Bogner2016-05-101-25/+41
| | | | | | | | | | | This means SelectCode unconditionally returns nullptr now. I'll follow up with a change to make that return void as well, but it seems best to keep that one very mechanical. This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 269136
* AArch64: allow vN to represent 64-bit registers in inline asm.Tim Northover2016-05-101-3/+8
| | | | | | | | Unlike xN/wN, the size of vN is genuinely ambiguous in the assembly, so we should try to infer what was intended from the type. But only down to 64-bits (vN can never represent sN, hN or bN). llvm-svn: 269132
* Reapply r266477 and r266488Easwaran Raman2016-05-103-3/+49
| | | | llvm-svn: 269131
* [PM]: port IR based profUse pass to new pass managerXinliang David Li2016-05-102-10/+33
| | | | llvm-svn: 269129
* Revert "MemCpyOpt: combine local load/store sequences into memcpy."Tim Northover2016-05-101-222/+48
| | | | | | | This reverts commit r269125. It was in my tree when I ran "git svn dcommit". It's really still under review. llvm-svn: 269127
* ARM: report an error when attempting to target a misalgined BLXTim Northover2016-05-101-3/+12
| | | | | | | The CodeGen problem was fixed in r269101, but we still miscompiled assembly that tried the same thing. llvm-svn: 269126
* MemCpyOpt: combine local load/store sequences into memcpy.Tim Northover2016-05-101-48/+222
| | | | | | | | Sort of the BB-local equivalent to idiom-recognizer: if we have a basic-block that really implements a memcpy operation, backends can benefit from seeing this. llvm-svn: 269125
* Loop unroller: set thresholds for optsize and minsize functions to zeroHans Wennborg2016-05-101-2/+2
| | | | | | | | | | | | | | | Before r268509, Clang would disable the loop unroll pass when optimizing for size. That commit enabled it to be able to support unroll pragmas in -Os builds. However, this regressed binary size in one of Chromium's DLLs with ~100 KB. This restores the original behaviour of no unrolling at -Os, but doing it in LLVM instead of Clang makes more sense, and also allows the pragmas to keep working. Differential revision: http://reviews.llvm.org/D20115 llvm-svn: 269124
* Enable loopreroll for sext of loop control only IVLawrence Hu2016-05-101-12/+33
| | | | | | | | | This patch extend loopreroll to allow the instruction chain of loop control only IV has sext. Differential Revision: http://reviews.llvm.org/D19820 llvm-svn: 269121
* SDAG: Avoid relying on the return value of SelectCode in SystemZ. NFCJustin Bogner2016-05-101-12/+20
| | | | | | | | | | This is a bit of a spot fix for now. I'll try to fix this up more comprehensively soon. This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 269120
* Revert r26084: Enable loopreroll for sext of loop control only IVLawrence Hu2016-05-101-33/+12
| | | | llvm-svn: 269119
* [X86] Properly check that EAX is dead when copying EFLAGS.Quentin Colombet2016-05-101-4/+9
| | | | | | | | | | | | This fixes a bug introduced in r267623, where we got smarter and avoided to save EAX before using it. However, we failed to check if any of the subregister of EAX were alive and thus, missed cases where we have to save EAX before using it. The problem may happen on every X86/i386/... platform. This fixes llvm.org/PR27624 llvm-svn: 269115
* [InstSimplify] use computeKnownBits on shift amount operandsSanjay Patel2016-05-101-0/+16
| | | | | | | | | | | | | | Do simplifications common to all shift instructions based on the amount shifted: 1. If the shift amount is known larger than the bitwidth, the result is undefined. 2. If the valid bits of the shift amount are all known to be 0, it's a shift by zero, so the shift operand is the result. Note that we could generalize the shift-by-zero transform into a shift-by-constant if all of the valid bits in the shift amount are known, but that would have to be done in InstCombine rather than here because it would mean we need to create a new shift instruction. Differential Revision: http://reviews.llvm.org/D19874 llvm-svn: 269114
* SDAG: Avoid relying on the return value of SelectCode in Hexagon. NFCJustin Bogner2016-05-101-3/+11
| | | | | | | | | | This is a bit of a spot fix for now. I'll try to fix this up more comprehensively soon. This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 269112
* Cloning: Clean up the interface to the CloneFunction function.Peter Collingbourne2016-05-103-33/+14
| | | | | | | | | | | | | | | | | | | | | Remove the ModuleLevelChanges argument, and the ability to create new subprograms for cloned functions. The latter was added without review in r203662, but it has no in-tree clients (all non-test callers pass false for ModuleLevelChanges [1], so it isn't reachable outside of tests). It also isn't clear that adding a duplicate subprogram to the compile unit is always the right thing to do when cloning a function within a module. If this functionality comes back it should be accompanied with a more concrete use case. Furthermore, all in-tree clients add the returned function to the module. Since that's pretty much the only sensible thing you can do with the function, just do that in CloneFunction. [1] http://llvm-cs.pcc.me.uk/lib/Transforms/Utils/CloneFunction.cpp/rCloneFunction Differential Revision: http://reviews.llvm.org/D18628 llvm-svn: 269110
* [InstCombine] Fold icmp ugt/ult (udiv i32 C2, X), C1.Chad Rosier2016-05-101-3/+21
| | | | | | | | | | This patch adds support for two optimizations: icmp ugt (udiv C2, X), C1 -> icmp ule X, C2/(C1+1) icmp ult (udiv C2, X), C1 -> icmp ugt X, C2/C1 Differential Revision: http://reviews.llvm.org/D20123 llvm-svn: 269109
* ScheduleDAGInstrs: Comment on why subreg defs are not seen as uses; NFCMatthias Braun2016-05-101-0/+4
| | | | | | | | Usually subregister definitions are consider uses of the remaining lanes that did not get defined. Add a comment why the code in ScheduleDAGInstrs does not add use dependencies regardless. llvm-svn: 269107
* [SystemZ] Add support for additional branch extended mnemonicsKit Barton2016-05-101-15/+22
| | | | | | | | | | | | | Added support for extended mnemonics for the following branch instructions and load/store-on-condition opcodes: BR, LOCR, LOCGR, LOC, LOCG, STOC, STOCG Phabricator: http://reviews.llvm.org/D19729 Committing on behalf of Zhan Liau llvm-svn: 269106
* [SCCP] Partially propagate informations when the input is not fully defined.Davide Italiano2016-05-101-0/+3
| | | | | | | | | | With this patch: %r1 = lshr i64 -1, 4294967296 -> undef Before this patch: %r1 = lshr i64 -1, 4294967296 -> 0 llvm-svn: 269105
* Debug Info: Prevent DW_AT_abstract_origin from being emitted twiceAdrian Prantl2016-05-101-7/+0
| | | | | | | | | | | | for the same subprogram. This fixes a bug where DW_AT_abstract_origin is being emitted twice for the same subprogram if a function is both inlined and emitted in the same translation unit, by restoring the pre-r266446 behavior. http://reviews.llvm.org/D20072 llvm-svn: 269103
* ARM: stop emitting blx instructions for most calls on MachO.Tim Northover2016-05-103-14/+5
| | | | | | | | | | | I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
* [AMDGPU][NFC] Rename SIInsertNops -> SIDebuggerInsertNopsKonstantin Zhuravlyov2016-05-104-19/+21
| | | | | | Differential Revision: http://reviews.llvm.org/D20117 llvm-svn: 269098
* Make "@name =" mandatory for globals in .ll files.Rafael Espindola2016-05-101-40/+0
| | | | | | | | | | | | | | | | | | | | | | | An oddity of the .ll syntax is that the "@var = " in @var = global i32 42 is optional. Writing just global i32 42 is equivalent to @0 = global i32 42 This means that there is a pretty big First set at the top level. The current implementation maintains it manually. I was trying to refactor it, but then started wondering why keep it a all. I personally find the above syntax confusing. It looks like something is missing. This patch removes the feature and simplifies the parser. llvm-svn: 269096
* Re-apply r269081 and r269082 with a fix for MSVC.Peter Collingbourne2016-05-103-51/+96
| | | | llvm-svn: 269094
* Fix PR26655: Bail out if all regs of an inst BUNDLE have the correct kill flagMandeep Singh Grang2016-05-102-27/+18
| | | | | | | | | | | | | | | | | | | | Summary: While setting kill flags on instructions inside a BUNDLE, we bail out as soon as we set kill flag on a register. But we are missing a check when all the registers already have the correct kill flag set. We need to bail out in that case as well. This patch refactors the old code and simply makes use of the addRegisterKilled function in MachineInstr.cpp in order to determine whether to set/remove kill on an instruction. Reviewers: apazos, t.p.northover, pete, MatzeB Subscribers: MatzeB, davide, llvm-commits Differential Revision: http://reviews.llvm.org/D17356 llvm-svn: 269092
* Revert r269081 and r269082 while I try to find the right incantation to fix ↵Peter Collingbourne2016-05-103-95/+51
| | | | | | MSVC build. llvm-svn: 269091
* [PGO] resubmit r268969Rong Xu2016-05-101-1/+1
| | | | | | Put the test into a target specific directory. llvm-svn: 269090
* Enable loopreroll for sext of loop control only IVLawrence Hu2016-05-101-12/+33
| | | | | | | This patch extend loopreroll to allow the instruction chain of loop control only IV has sext. llvm-svn: 269084
* [WebAssembly] Preliminary fast-isel support.Dan Gohman2016-05-101-4/+542
| | | | llvm-svn: 269083
* WholeProgramDevirt: Move logic for finding devirtualizable call sites to ↵Peter Collingbourne2016-05-103-51/+95
| | | | | | | | | | | | | Analysis. The plan is to eventually make this logic simpler, however I expect it to be a little tricky for the foreseeable future (at least until we're rid of pointee types), so move it here so that it can be reused to build a summary index for devirtualization. Differential Revision: http://reviews.llvm.org/D20005 llvm-svn: 269081
* Simplify LLParser::ParseOptionalLinkage. NFC.Rafael Espindola2016-05-101-19/+34
| | | | llvm-svn: 269080
* [ScheduleDAG] Make sure to process all def operands before any use operandsKrzysztof Parzyszek2016-05-101-8/+25
| | | | | | | | | | | | | | | | | An example from Hexagon where things went wrong: %R0<def> = L2_loadrigp <ga:@fp04> ; load function address J2_callr %R0<kill>, ..., %R0<imp-def> ; call *R0, return value in R0 ScheduleDAGInstrs::buildSchedGraph would visit all instructions going backwards, and in each instruction it would visit all operands in their order on the operand list. In the case of this call, it visited the use of R0 first, then removed it from the set Uses after it visited the def. This caused the DAG to be missing the data dependence edge on R0 between the load and the call. Differential Revision: http://reviews.llvm.org/D20102 llvm-svn: 269076
* [PR27599] [SystemZ] [SelectionDAG] Fix extension of atomic cmpxchg result.Marcin Koscielnicki2016-05-103-6/+23
| | | | | | | | | | | | Currently, SelectionDAG assumes 8/16-bit cmpxchg returns either a sign extended result, or a zero extended result. SystemZ takes a third option by returning junk in the high bits (rotated contents of the other bytes in the memory word). In that case, don't use Assert*ext, and zero-extend the result ourselves if a comparison is needed. Differential Revision: http://reviews.llvm.org/D19800 llvm-svn: 269075
* [ThinLTO] Add option to emit imports files for distributed backendsTeresa Johnson2016-05-102-0/+39
| | | | | | | | | | | | | | | | | | | | | Summary: Add support for emission of plaintext lists of the imported files for each distributed backend compilation. Used for distributed build file staging. Invoked with new gold-plugin thinlto-emit-imports-files option, which is only valid with thinlto-index-only (i.e. for distributed builds), or from llvm-lto with new -thinlto-action=emitimports value. Depends on D19556. Reviewers: joker.eph Subscribers: llvm-commits, joker.eph Differential Revision: http://reviews.llvm.org/D19636 llvm-svn: 269067
* Restore "[ThinLTO] Emit individual index files for distributed backends"Teresa Johnson2016-05-103-71/+265
| | | | | | | | | | | | | | | | | | | This restores commit r268627: Summary: When launching ThinLTO backends in a distributed build (currently supported in gold via the thinlto-index-only plugin option), emit an individual index file for each backend process as described here: http://lists.llvm.org/pipermail/llvm-dev/2016-April/098272.html ... Differential Revision: http://reviews.llvm.org/D19556 Address msan failures by avoiding std::prev on map.end(), the theory is that this is causing issues due to some known UB problems in __tree. llvm-svn: 269059
* [LAA] Use re-written SCEV expressions when computing distancesSilviu Baranga2016-05-101-7/+2
| | | | | | | | | | | | This removes a redundant stride versioning step (we already do it in getPtrStride, so it has no effect) and uses PSE to get the SCEV expressions for the source and destination (this might have changed when getPtrStride was called). I discovered this through code inspection, and couldn't produce a regression test for it. llvm-svn: 269052
* Revert "[VectorUtils] Query number of sign bits to allow more truncations"James Molloy2016-05-101-14/+4
| | | | | | | | This was a fairly simple patch but on closer inspection was seriously flawed and caused PR27690. This reverts commit r268921. llvm-svn: 269051
OpenPOWER on IntegriCloud