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* [ARM] Enable DP copy, load and store instructions for FPv4-SPOliver Stannard2014-08-217-53/+206
| | | | | | | | | | | | | | | | | The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
* Reassociate x + -0.1234 * y into x - 0.1234 * yErik Verbruggen2014-08-212-40/+49
| | | | | | | | | | | This does not require -ffast-math, and it gives CSE/GVN more options to eliminate duplicate expressions in, e.g.: return ((x + 0.1234 * y) * (x - 0.1234 * y)); Differential Revision: http://reviews.llvm.org/D4904 llvm-svn: 216169
* X86: Turn redundant if into an assertion.Benjamin Kramer2014-08-211-7/+5
| | | | | | While there remove noop casts. llvm-svn: 216168
* [x86] Added _addcarry_ and _subborrow_ intrinsicsRobert Khasanov2014-08-211-1/+9
| | | | llvm-svn: 216164
* [x86] SMAP: added HasSMAP attribute for CLAC/STAC, corrected attributesRobert Khasanov2014-08-211-1/+1
| | | | llvm-svn: 216163
* [x86] Broadwell: ADOX/ADCX. Added _addcarryx_u{32|64} intrinsics to LLVM.Robert Khasanov2014-08-212-21/+52
| | | | llvm-svn: 216162
* [x86] Enable Broadwell target.Robert Khasanov2014-08-214-0/+15
| | | | | | | | Added FeatureSMAP. Broadwell ISA includes Haswell ISA + ADX + RDSEED + SMAP llvm-svn: 216161
* [INDVARS] Extend using of widening of induction variables for the cases of ↵Zinovy Nis2014-08-211-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | "sub nsw" and "mul nsw" instructions. Currently only "add nsw" are widened. This patch eliminates tons of "sext" instructions for 64 bit code (and the corresponding target code) in cases like: int N = 100; float **A; void foo(int x0, int x1) { float * A_cur = &A[0][0]; float * A_next = &A[1][0]; for(int x = x0; x < x1; ++x). { // Currently only [x+N] case is widened. Others 2 cases lead to sext. // This patch fixes it, so all 3 cases do not need sext. const float div = A_cur[x + N] + A_cur[x - N] + A_cur[x * N]; A_next[x] = div; } } ... > clang++ test.cpp -march=core-avx2 -Ofast -fno-unroll-loops -fno-tree-vectorize -S -o - Differential Revision: http://reviews.llvm.org/D4695 llvm-svn: 216160
* IntelJITEventListener updates to fix breaks by recent changes to ↵Elena Demikhovsky2014-08-211-1/+1
| | | | | | | | EngineBuilder and DIContext. By Arch Robison. llvm-svn: 216159
* Repace SmallPtrSet with SmallPtrSetImpl in function arguments to avoid ↵Craig Topper2014-08-2141-105/+103
| | | | | | needing to mention the size. llvm-svn: 216158
* InstCombine: Fold ((A | B) & C1) ^ (B & C2) -> (A & C1) ^ B if C1^C2=-1David Majnemer2014-08-212-0/+46
| | | | | | Adapted from a patch by Richard Smith, test-case written by me. llvm-svn: 216157
* Remove custom implementations of max/min in StringRef that was originally ↵Craig Topper2014-08-211-9/+9
| | | | | | added to work an old gcc bug. I believe its been fixed by now. llvm-svn: 216156
* Fix a bug around truncating vector in const prop.Jiangning Liu2014-08-211-0/+3
| | | | | | In constant folding stage, "TRUNC" can't handle vector data type. llvm-svn: 216149
* Revert r216066, "Optimize ZERO_EXTEND and SIGN_EXTEND in both SelectionDAG ↵Jiangning Liu2014-08-212-48/+3
| | | | | | Builder and type". llvm-svn: 216147
* [PeepholeOptimizer] Take advantage of the isInsertSubreg property in theQuentin Colombet2014-08-211-32/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | advanced copy optimization. This is the final step patch toward transforming: udiv r0, r0, r2 udiv r1, r1, r3 vmov.32 d16[0], r0 vmov.32 d16[1], r1 vmov r0, r1, d16 bx lr into: udiv r0, r0, r2 udiv r1, r1, r3 bx lr Indeed, thanks to this patch, this optimization is able to look through vmov.32 d16[0], r0 vmov.32 d16[1], r1 and is able to rewrite the following sequence: vmov.32 d16[0], r0 vmov.32 d16[1], r1 vmov r0, r1, d16 into simple generic GPR copies that the coalescer managed to remove. <rdar://problem/12702965> llvm-svn: 216144
* [ARM] Mark VSETLNi32 with the InsertSubreg property and implement the relatedQuentin Colombet2014-08-213-0/+43
| | | | | | | | | | | | | target hook. This patch teaches the compiler that: dX = VSETLNi32 dY, rZ, imm is the same as: dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(imm) <rdar://problem/12702965> llvm-svn: 216143
* [LoopVectorize] Up the maximum unroll factor to 4 for AArch64James Molloy2014-08-211-1/+7
| | | | | | Only for Cortex-A57 and Cyclone for now, where it has shown wins. llvm-svn: 216141
* [LoopVectorizer] Limit unroll factor in the presence of nested reductions.James Molloy2014-08-201-0/+17
| | | | | | If we have a scalar reduction, we can increase the critical path length if the loop we're unrolling is inside another loop. Limit, by default to 2, so the critical path only gets increased by one reduction operation. llvm-svn: 216140
* Add isInsertSubreg property.Quentin Colombet2014-08-201-0/+26
| | | | | | | | | | | | | This patch adds a new property: isInsertSubreg and the related target hooks: TargetIntrInfo::getInsertSubregInputs and TargetInstrInfo::getInsertSubregLikeInputs to specify that a target specific instruction is a (kind of) INSERT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216139
* Lower thumbv4t & thumbv5 lo->lo copies through a push-pop sequenceJonathan Roelofs2014-08-201-2/+23
| | | | | | | | | | | On pre-v6 hardware, 'MOV lo, lo' gives undefined results, so such copies need to be avoided. This patch trades simplicity for implementation time at the expense of performance... As they say: correctness first, then performance. See http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-August/075998.html for a few ideas on how to make this better. llvm-svn: 216138
* [PeepholeOptimizer] Take advantage of the isExtractSubreg property in theQuentin Colombet2014-08-201-24/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | advanced copy optimization. This patch is a step toward transforming: udiv r0, r0, r2 udiv r1, r1, r3 vmov.32 d16[0], r0 vmov.32 d16[1], r1 vmov r0, r1, d16 bx lr into: udiv r0, r0, r2 udiv r1, r1, r3 bx lr Indeed, thanks to this patch, this optimization is able to look through vmov r0, r1, d16 but it does not understand yet vmov.32 d16[0], r0 vmov.32 d16[1], r1 Comming patches will fix that and update the related test case. <rdar://problem/12702965> llvm-svn: 216136
* New InstCombine pattern: (icmp ult/ule (A + C1), C3) | (icmp ult/ule (A + ↵Yi Jiang2014-08-201-0/+55
| | | | | | C2), C3) to (icmp ult/ule ((A & ~(C1 ^ C2)) + max(C1, C2)), C3) under certain condition llvm-svn: 216135
* Don't allow MCStreamer::EmitIntValue to output 0-byte integers.Alexey Samsonov2014-08-202-2/+3
| | | | | | | | It makes no sense and can hide bugs. In particular, it lead to left shift by 64 bits, which is an undefined behavior, properly reported by UBSan. llvm-svn: 216134
* [ARM] Mark VMOVRRD with the ExtractSubreg property and implement the relatedQuentin Colombet2014-08-203-0/+39
| | | | | | | | | | | | | | target hook. This patch teaches the compiler that: rX, rY = VMOVRRD dZ is the same as: rX = EXTRACT_SUBREG dZ, ssub_0 rY = EXTRACT_SUBREG dZ, ssub_1 <rdar://problem/12702965> llvm-svn: 216132
* Fix undefined behavior (left shift of negative value) in SystemZ backend.Alexey Samsonov2014-08-202-7/+3
| | | | | | This bug is reported by UBSan. llvm-svn: 216131
* Add isExtractSubreg property.Quentin Colombet2014-08-201-0/+23
| | | | | | | | | | | | | This patch adds a new property: isExtractSubreg and the related target hooks: TargetIntrInfo::getExtractSubregInputs and TargetInstrInfo::getExtractSubregLikeInputs to specify that a target specific instruction is a (kind of) EXTRACT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216130
* Fix null reference creation in SelectionDAG constructor.Alexey Samsonov2014-08-201-10/+7
| | | | | | | | | | Store TargetSelectionDAGInfo as a pointer instead of a reference: getSelectionDAGInfo() may not be implemented for certain backends (e.g. it's not currently implemented for R600). This bug is reported by UBSan. llvm-svn: 216129
* Fix undefined behavior (left shift of negative value) in Hexagon backend.Alexey Samsonov2014-08-202-6/+6
| | | | | | This bug is reported by UBSan. llvm-svn: 216125
* Cleanup: Delete seemingly unused reference to MachineDominatorTree from ↵Alexey Samsonov2014-08-205-33/+26
| | | | | | ScheduleDAGInstrs. llvm-svn: 216124
* Don't prevent a vselect of constants from becoming a single load (PR20648).Sanjay Patel2014-08-201-0/+13
| | | | | | | | | | | | | | | Fix for PR20648 - http://llvm.org/bugs/show_bug.cgi?id=20648 This patch checks the operands of a vselect to see if all values are constants. If yes, bail out of any further attempts to create a blend or shuffle because SelectionDAGLegalize knows how to turn this kind of vselect into a single load. This already happens for machines without SSE4.1, so the added checks just send more targets down that path. Differential Revision: http://reviews.llvm.org/D4934 llvm-svn: 216121
* X86: Align the stack on word boundaries in LowerFormalArguments()Duncan P. N. Exon Smith2014-08-201-0/+1
| | | | | | | | | | | | | | | The goal of the patch is to implement section 3.2.3 of the AMD64 ABI correctly. The controlling sentence is, "The size of each argument gets rounded up to eightbytes. Therefore the stack will always be eightbyte aligned." The equivalent sentence in the i386 ABI page 37 says, "At all times, the stack pointer should point to a word-aligned area." For both architectures, the stack pointer is not being rounded up to the nearest eightbyte or word between the last normal argument and the first variadic argument. Patch by Thomas Jablin! llvm-svn: 216119
* Fix null reference creation in ScheduleDAGInstrs constructor call.Alexey Samsonov2014-08-204-5/+5
| | | | | | | | | Both MachineLoopInfo and MachineDominatorTree may be null in ScheduleDAGMI constructor call. It is undefined behavior to take references to these values. This bug is reported by UBSan. llvm-svn: 216118
* Do not insert a tail call when returning multiple values on X86Keno Fischer2014-08-201-0/+7
| | | | | | | | | | | | | | | | | | | | | Summary: This fixes http://llvm.org/bugs/show_bug.cgi?id=19530. The problem is that X86ISelLowering erroneously thought the third call was eligible for tail call elimination. It would have been if it's return value was actually the one returned by the calling function, but here that is not the case and additional values are being returned. Test Plan: Test case from the original bug report is included. Reviewers: rafael Reviewed By: rafael Subscribers: rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D4968 llvm-svn: 216117
* Fix undefined behavior (left shift by 64 bits) in ScaledNumber::toString().Alexey Samsonov2014-08-201-0/+3
| | | | | | This bug is reported by UBSan. llvm-svn: 216116
* critical-anti-dependency breaker: don't use reg def info from kill insts ↵Sanjay Patel2014-08-201-2/+17
| | | | | | | | | | | | | | | | | | (PR20308) In PR20308 ( http://llvm.org/bugs/show_bug.cgi?id=20308 ), the critical-anti-dependency breaker caused a miscompile because it broke a WAR hazard using a register that it thinks is available based on info from a kill inst. Until PR18663 is solved, we shouldn't use any def/use info from a kill because they are really just nops. This patch adds guard checks for kills around calls to ScanInstruction() where the DefIndices array is set. For good measure, add an assert in ScanInstruction() so we don't hit this bug again. The test case is a reduced version of the code from the bug report. Differential Revision: http://reviews.llvm.org/D4977 llvm-svn: 216114
* [PeepholeOptimizer] Refactor the advanced copy optimization to take advantage ofQuentin Colombet2014-08-202-169/+610
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the isRegSequence property. This is a follow-up of r215394 and r215404, which respectively introduces the isRegSequence property and uses it for ARM. Thanks to the property introduced by the previous commits, this patch is able to optimize the following sequence: vmov d0, r2, r3 vmov d1, r0, r1 vmov r0, s0 vmov r1, s2 udiv r0, r1, r0 vmov r1, s1 vmov r2, s3 udiv r1, r2, r1 vmov.32 d16[0], r0 vmov.32 d16[1], r1 vmov r0, r1, d16 bx lr into: udiv r0, r0, r2 udiv r1, r1, r3 vmov.32 d16[0], r0 vmov.32 d16[1], r1 vmov r0, r1, d16 bx lr This patch refactors how the copy optimizations are done in the peephole optimizer. Prior to this patch, we had one copy-related optimization that replaced a copy or bitcast by a generic, more suitable (in terms of register file), copy. With this patch, the peephole optimizer features two copy-related optimizations: 1. One for rewriting generic copies to generic copies: PeepholeOptimizer::optimizeCoalescableCopy. 2. One for replacing non-generic copies with generic copies: PeepholeOptimizer::optimizeUncoalescableCopy. The goals of these two optimizations are slightly different: one rewrite the operand of the instruction (#1), the other kills off the non-generic instruction and replace it by a (sequence of) generic instruction(s). Both optimizations rely on the ValueTracker introduced in r212100. The ValueTracker has been refactored to use the information from the TargetInstrInfo for non-generic instruction. As part of the refactoring, we switched the tracking from the index of the definition to the actual register (virtual or physical). This one change is to provide better consistency with register related APIs and to ease the use of the TargetInstrInfo. Moreover, this patch introduces a new helper class CopyRewriter used to ease the rewriting of generic copies (i.e., #1). Finally, this patch adds a dead code elimination pass right after the peephole optimizer to get rid of dead code that may appear after rewriting. This is related to <rdar://problem/12702965>. Review: http://reviews.llvm.org/D4874 llvm-svn: 216088
* Remove unused field.Rafael Espindola2014-08-201-3/+1
| | | | llvm-svn: 216086
* [FastISel][AArch64] Don't fold the sign-/zero-extend from i1 into the compare.Juergen Ributzka2014-08-201-7/+20
| | | | | | | | | | This fixes a bug I introduced in a previous commit (r216033). Sign-/Zero- extension from i1 cannot be folded into the ADDS/SUBS instructions. Instead both operands have to be sign-/zero-extended with separate instructions. Related to <rdar://problem/17913111>. llvm-svn: 216073
* Silencing a -Wcast-qual warning. NFC.Aaron Ballman2014-08-201-1/+1
| | | | llvm-svn: 216068
* Silencing an MSVC C4334 warning ('<<' : result of 32-bit shift implicitly ↵Aaron Ballman2014-08-201-1/+1
| | | | | | converted to 64 bits (was 64-bit shift intended?)). NFC. llvm-svn: 216067
* Optimize ZERO_EXTEND and SIGN_EXTEND in both SelectionDAG Builder and typeJiangning Liu2014-08-202-3/+48
| | | | | | | | legalization stage. With those two optimizations, fewer signed/zero extension instructions can be inserted, and then we can expose more opportunities to Machine CSE pass in back-end. llvm-svn: 216066
* [x32] Fix FrameIndex check in SelectLEA64_32AddrPavel Chupin2014-08-202-1/+7
| | | | | | | | | | | | | | | | | | Summary: Fixes http://llvm.org/bugs/show_bug.cgi?id=20016 reproducible on new lea-5.ll case. Also use RSP/RBP for x32 lea to save 1 byte used for 0x67 prefix in ESP/EBP case. Test Plan: lea tests modified to include x32/nacl and new test added Reviewers: nadav, dschuff, t.p.northover Subscribers: llvm-commits, zinovy.nis Differential Revision: http://reviews.llvm.org/D4929 llvm-svn: 216065
* ARM: Fix codegen for rbit intrinsicYi Kong2014-08-201-2/+2
| | | | | | | | | | | | LLVM generates illegal `rbit r0, #352` instruction for rbit intrinsic. According to ARM ARM, rbit only takes register as argument, not immediate. The correct instruction should be rbit <Rd>, <Rm>. The bug was originally introduced in r211057. Differential Revision: http://reviews.llvm.org/D4980 llvm-svn: 216064
* InstCombine: Annotate sub with nuw when we prove it's safeDavid Majnemer2014-08-202-0/+19
| | | | | | | We can prove that a 'sub' can be a 'sub nuw' if the left-hand side is negative and the right-hand side is non-negative. llvm-svn: 216045
* Fix an off by 1 bug that prevented SmallPtrSet from using all of its 'small' ↵Craig Topper2014-08-201-6/+5
| | | | | | capacity. Then fix the early return in the move constructor that prevented 'small' moves from clearing the NumElements in the moved from object. The directed test missed this because it was always testing large moves due to the off by 1 bug. llvm-svn: 216044
* [dfsan] Treat vararg custom functions like unimplemented functions.Peter Collingbourne2014-08-201-1/+1
| | | | | | | | | Because declarations of these functions can appear in places like autoconf checks, they have to be handled somehow, even though we do not support vararg custom functions. We do so by printing a warning and calling the uninstrumented function, as we do for unimplemented functions. llvm-svn: 216042
* [FastISel][AArch64] Use the proper FMOV instruction to materialize a +0.0.Juergen Ributzka2014-08-201-1/+1
| | | | | | | | | | Use FMOVWSr/FMOVXDr instead of FMOVSr/FMOVDr, which have the proper register class to be used with the zero register. This makes the MachineInstruction verifier happy again. This is related to <rdar://problem/18027157>. llvm-svn: 216040
* InstCombine: Annotate sub with nsw when we prove it's safeDavid Majnemer2014-08-192-1/+40
| | | | | | | | | | We can prove that a 'sub' can be a 'sub nsw' under certain conditions: - The sign bits of the operands is the same. - Both operands have more than 1 sign bit. The subtraction cannot be a signed overflow in either case. llvm-svn: 216037
* [FastISel][AArch64] Factor out ADDS/SUBS instruction emission and add ↵Juergen Ributzka2014-08-191-224/+397
| | | | | | | | | | | | | support for extensions and shift folding. Factor out the ADDS/SUBS instruction emission code into helper functions and make the helper functions more clever to support most of the different ADDS/SUBS instructions the architecture support. This includes better immedediate support, shift folding, and sign-/zero-extend folding. This fixes <rdar://problem/17913111>. llvm-svn: 216033
* Split parseAssembly into parseAssembly and parseAssemblyInto.Rafael Espindola2014-08-191-6/+13
| | | | | | | This should restore the functionality of parsing new code into an existing module without the confusing interface. llvm-svn: 216031
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