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* Rename variables to avoid confusion. No functionallity change intended.Chad Rosier2011-11-111-18/+18
| | | | llvm-svn: 144377
* Add support for using immediates with select instructions.Chad Rosier2011-11-111-8/+40
| | | | | | rdar://10412592 llvm-svn: 144376
* Do not try to detect DAG combine patterns for integer multiply-add/sub if valueAkira Hatanaka2011-11-111-2/+4
| | | | | | | type is not i32. MIPS does not have 64-bit integer multiply-add/sub instructions. llvm-svn: 144373
* 64-bit atomic instructions.Akira Hatanaka2011-11-113-64/+194
| | | | llvm-svn: 144372
* Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64.Akira Hatanaka2011-11-111-1/+2
| | | | llvm-svn: 144371
* Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.Akira Hatanaka2011-11-113-12/+27
| | | | llvm-svn: 144370
* 64-bit versions of jal, jalr and bal.Akira Hatanaka2011-11-112-0/+27
| | | | llvm-svn: 144368
* Emit Mips64's sequence of instructions that set global register in prologue.Akira Hatanaka2011-11-111-1/+21
| | | | llvm-svn: 144367
* Fix printing of MCSymbolRegExpr. Needs three closing parentheses forAkira Hatanaka2011-11-111-1/+4
| | | | | | VK_Mips_GPOFF_HI/LO. llvm-svn: 144366
* Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.Eli Friedman2011-11-111-0/+1
| | | | llvm-svn: 144361
* Initialize variable.Eric Christopher2011-11-111-1/+2
| | | | llvm-svn: 144360
* When loading a value, treat an i1 as an i8.Chad Rosier2011-11-111-0/+1
| | | | llvm-svn: 144356
* If we have a DIE with an AT_specification use that instead of the normalEric Christopher2011-11-111-7/+10
| | | | | | addr DIE when adding to the dwarf accelerator tables. llvm-svn: 144354
* Get rid of an optimization in SCCP which appears to have many issues. ↵Eli Friedman2011-11-111-167/+1
| | | | | | | | | | Specifically, it doesn't handle many cases involving undef correctly, and it is missing other checks which lead to it trying to re-mark a value marked as a constant with a different value. It also appears to trigger very rarely. Fixes PR11357. llvm-svn: 144352
* Reenable compact unwinding now that <rdar://problem/10430076> is fixed.Bill Wendling2011-11-111-1/+1
| | | | llvm-svn: 144351
* If we have to reset the calculation of the compact encoding, then also reset theBill Wendling2011-11-111-0/+1
| | | | | | | "saved register" index. <rdar://problem/10430076> llvm-svn: 144350
* Add support for using MVN to materialize negative constants.Chad Rosier2011-11-111-3/+17
| | | | | | rdar://10412592 llvm-svn: 144348
* Disable compact unwind generation until I can solve the codegen problems.Bill Wendling2011-11-111-1/+2
| | | | llvm-svn: 144346
* LLVMBuild: Add explicit information on whether targets define an assembly ↵Daniel Dunbar2011-11-1110-0/+16
| | | | | | printer, assembly parser, or disassembler. llvm-svn: 144344
* Thumb2 ldm/stm updating w/ one register in the list are LDR/STR.Jim Grosbach2011-11-101-0/+32
| | | | | | rdar://10429490 llvm-svn: 144338
* ARM let processInstruction() tranforms chain.Jim Grosbach2011-11-101-15/+37
| | | | llvm-svn: 144337
* Thumb2 parsing for push/pop w/ hi registers in the reglist.Jim Grosbach2011-11-101-2/+32
| | | | | | rdar://10130228. llvm-svn: 144331
* Thumb1 diagnostics for reglist on PUSH/POP fix.Jim Grosbach2011-11-101-2/+2
| | | | | | Was not checking the first register in the register list. llvm-svn: 144329
* Check in getOrCreateSubprogramDIE if a declaration exists and if so outputRafael Espindola2011-11-102-13/+12
| | | | | | | | it first. This is a more general fix to pr11300. llvm-svn: 144324
* Thumb MUL assembly parsing for 3-operand form.Jim Grosbach2011-11-101-7/+9
| | | | | | | | | Get the source register that isn't tied to the destination register correct, even when the assembly source operand order is backwards. rdar://10428630 llvm-svn: 144322
* build/MBlazeDisassembler: Some compilers may generate an MBlaze disassemblerDaniel Dunbar2011-11-101-1/+7
| | | | | | | that depends on MBlazeCodeGen. This is a layering violation that should really be fixed. llvm-svn: 144321
* build/MCDisassembler: Fix required libraries list of MCDisassembler to useDaniel Dunbar2011-11-101-1/+3
| | | | | | all-targets instead of an explicit list. llvm-svn: 144320
* Make types and namespaces take multiple DIEs for the accelerator tablesEric Christopher2011-11-102-14/+24
| | | | | | as well. llvm-svn: 144319
* When in ARM mode, LDRH/STRH require special handling of negative offsets.Chad Rosier2011-11-101-1/+2
| | | | | | | For correctness, disable this for now. rdar://10418009 llvm-svn: 144316
* ARM .thumb_func directive for quoted symbol names.Jim Grosbach2011-11-101-3/+3
| | | | | | | | | Use the getIdentifier() method of the token, not getString(), otherwise we keep the quotes as part of the symbol name, which we don't want. rdar://10428015 llvm-svn: 144315
* Fixed bug in DeadStoreElimination commit r144239Pete Cooper2011-11-101-1/+1
| | | | | | | | Size of data being pointed to wasn't always being checked so some small writes were killing big writes Fixes <rdar://problem/10426753> llvm-svn: 144312
* Move type handling to make sure we get all created types that aren'tEric Christopher2011-11-101-7/+5
| | | | | | forward decls and have names into the dwarf accelerator types table. llvm-svn: 144306
* Rework adding function names to the dwarf accelerator tables, allowEric Christopher2011-11-103-71/+86
| | | | | | multiple dies per function and support C++ basenames. llvm-svn: 144304
* ARM assembly parsing for LSR/LSL/ROR(immediate).Jim Grosbach2011-11-102-6/+50
| | | | | | More of rdar://9704684 llvm-svn: 144301
* ARM assembly parsing for ASR(immediate).Jim Grosbach2011-11-103-7/+37
| | | | | | Start of rdar://9704684 llvm-svn: 144293
* build: Rename CBackend and CppBackend libraries to have CodeGen suffix, forDaniel Dunbar2011-11-104-6/+6
| | | | | | consistency with other targets. llvm-svn: 144292
* Use a bigger hammer to fix PR11314 by disabling the "forcing two-addressEvan Cheng2011-11-101-1/+5
| | | | | | | | | | | | | | | | instruction lower optimization" in the pre-RA scheduler. The optimization, rather the hack, was done before MI use-list was available. Now we should be able to implement it in a better way, perhaps in the two-address pass until a MI scheduler is available. Now that the scheduler has to backtrack to handle call sequences. Adding artificial scheduling constraints is just not safe. Furthermore, the hack is not taking all the other scheduling decisions into consideration so it's just as likely to pessimize code. So I view disabling this optimization goodness regardless of PR11314. llvm-svn: 144267
* AVX2: Add variable shift from memory.Nadav Rotem2011-11-101-1/+24
| | | | | | | | Note: These patterns only works in some cases because many times the load sd node is bitcasted from a load node of a different type. llvm-svn: 144266
* For immediate encodings of icmp, zero or sign extend first. ThenChad Rosier2011-11-101-5/+5
| | | | | | | determine if the value is negative and flip the sign accordingly. rdar://10422026 llvm-svn: 144258
* build/Make & CMake: Pass the appropriate --native-target and --enable-targetsDaniel Dunbar2011-11-101-2/+3
| | | | | | options to llvm-build, so the all-targets etc. components are defined properly. llvm-svn: 144255
* llvm-build: Add --native-target and --enable-targets options, and add logic toDaniel Dunbar2011-11-1013-16/+16
| | | | | | | | | | handle defining the "magic" target related components (like native, nativecodegen, and engine). - We still require these components to be in the project (currently in lib/Target) so that we have a place to document them and hopefully make it more obvious that they are "magic". llvm-svn: 144253
* llvm-build: Change CBackend and CppBackend to not use library_name. This willDaniel Dunbar2011-11-102-2/+0
| | | | | | | | | change the generated library .a file name once we fully switch over, but simplifies how we treat these targets without requiring more special casing (since their library group name and the codegen library name currently map to the same "llvm-config" style component name). llvm-svn: 144251
* llvm-build: Add an explicit component type to represent targets.Daniel Dunbar2011-11-1012-12/+16
| | | | | | - Gives us a place to hang target specific metadata (like whether the target has a JIT). llvm-svn: 144250
* Strip old implicit operands after foldMemoryOperand.Jakob Stoklund Olesen2011-11-101-2/+19
| | | | | | | | | | | | The TII.foldMemoryOperand hook preserves implicit operands from the original instruction. This is not what we want when those implicit operands refer to the register being spilled. Implicit operands referring to other registers are preserved. This fixes PR11347. llvm-svn: 144247
* Tidy up.Jim Grosbach2011-11-101-12/+0
| | | | llvm-svn: 144244
* Thumb2 assembly parsing STMDB w/ optional .w suffix.Jim Grosbach2011-11-091-0/+6
| | | | | | rdar://10422955 llvm-svn: 144242
* Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.Eli Friedman2011-11-091-1/+25
| | | | llvm-svn: 144241
* DeadStoreElimination can now trim the size of a store if the end of the ↵Pete Cooper2011-11-091-33/+110
| | | | | | | | | | | store is dead. Currently checks alignment and killing stores on a power of 2 boundary as this is likely to trim the size of the earlier store without breaking large vector stores into scalar ones. Fixes <rdar://problem/10140300> llvm-svn: 144239
* Fix typo in comment.Nick Lewycky2011-11-091-1/+1
| | | | llvm-svn: 144236
* Add check so we don't try to perform an impossible transformation. Fixes ↵Eli Friedman2011-11-091-1/+2
| | | | | | issue from PR11319. llvm-svn: 144216
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