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* [SCEV] Fix a variable name, NFC.Justin Lebar2018-06-141-6/+6
| | | | llvm-svn: 334738
* [SCEV] Simplify zext/trunc idiom that appears when handling bitmasks.Justin Lebar2018-06-141-0/+26
| | | | | | | | | | | | | | | | | | | Summary: Specifically, we transform zext(2^K * (trunc X to iN)) to iM -> 2^K * (zext(trunc X to i{N-K}) to iM)<nuw> This is helpful because pulling the 2^K out of the zext allows further optimizations. Reviewers: sanjoy Subscribers: hiraditya, llvm-commits, timshen Differential Revision: https://reviews.llvm.org/D48158 llvm-svn: 334737
* [SCEV] Simplify trunc-of-add/mul to add/mul-of-trunc under more circumstances.Justin Lebar2018-06-141-32/+22
| | | | | | | | | | | | | | | | | | | | Summary: Previously we would do this simplification only if it did not introduce any new truncs (excepting new truncs which replace other cast ops). This change weakens this condition: If the number of truncs stays the same, but we're able to transform trunc(X + Y) to X + trunc(Y), that's still simpler, and it may open up additional transformations. While we're here, also clean up some duplicated code. Reviewers: sanjoy Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D48160 llvm-svn: 334736
* [SCEV] Fix indentation and combine two if statements in getMulExpr, NFC.Justin Lebar2018-06-141-15/+14
| | | | llvm-svn: 334735
* Revert "[MC] Factor MCObjectStreamer::addFragmentAtoms out of MachO streamer."Sam Clegg2018-06-143-30/+24
| | | | | | | | | This reverts rL331412. We didn't up using fragment atoms in the wasm object writer after all. Differential Revision: https://reviews.llvm.org/D48173 llvm-svn: 334734
* Revert rL334704: "[DebugInfo] Check size of variable in ↵Bjorn Pettersson2018-06-142-45/+0
| | | | | | | | | | ConvertDebugDeclareToDebugValue" This reverts commit r334704. Buildbots detected an assertion in "test tsan in debug compiler-rt build". llvm-svn: 334732
* Avoid unused variable in non-assert builds.Nirav Dave2018-06-141-0/+1
| | | | llvm-svn: 334731
* [DAG] Avoid needing to walk out legalization tables. NFCI.Nirav Dave2018-06-142-193/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To avoid redundant work, during DAG legalization we keep tables mapping pre-legalized SDValues to post-legalized SDValues and a SDValue-to-SDValue map to enable fast node replacements. However, as the keys are nodes which may be reused it is possible that an entry in a table refers to a now deleted node N (that should have been renamed by the value replacement map) while a new node N' exists. If N' is then replaced that entry would be wrong. Previously we avoided this by when potentially violating this property, walking every table and updating all node pointers. This is very expensive but hopefully rare occurance. This patch assigns each instance of a SDValue used in legalization a unique id and uses these ids in the legalization tables. This avoids any such aliasing issue, avoiding the full table search and allowing more aggressive incremental table pruning. In some cases this is a 1000x speedup to compilation. Reviewers: jyknight, echristo, bogner, tra Reviewed By: bogner Subscribers: dberris, grandinj, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D47959 llvm-svn: 334729
* [X86] Add more vector instructions to the memory folding table using the ↵Craig Topper2018-06-141-1/+215
| | | | | | | | autogenerated table as a guide. The test cahnge is because we now fold stack reload into RNDSCALE and RNDSCALE can be turned into ROUND by EVEX->VEX. llvm-svn: 334728
* [X86] Remove '128' from the internal name of some scalar FP instructions to ↵Craig Topper2018-06-141-8/+8
| | | | | | be consistent with other scalar instructions. llvm-svn: 334727
* [X86] Disable load unfolding for a bunch of instruction where unfolding ↵Craig Topper2018-06-141-16/+16
| | | | | | | | would increase the size of the load. Found by an audit of the manual table vs the autogenerated table. llvm-svn: 334726
* [X86] Remove NotMemoryFoldable from some AVX/AVX512 scalar instructions.Craig Topper2018-06-142-15/+14
| | | | | | Some of these instructions are already in the manual folding table so we should have them in the auto table too. llvm-svn: 334725
* [ORC] Filter out self-dependencies in VSO::addDependencies.Lang Hames2018-06-141-1/+1
| | | | llvm-svn: 334724
* [ORC] Assert that the query argument to VSO::lookup must be non-null.Lang Hames2018-06-141-0/+2
| | | | llvm-svn: 334723
* [ORC] Add a WaitUntilReady argument to blockingLookup.Lang Hames2018-06-142-24/+44
| | | | | | | | | | | If WaitUntilReady is set to true then blockingLookup will return once all requested symbols are ready. If WaitUntilReady is set to false then blockingLookup will return as soon as all requested symbols have been resolved. In the latter case, if any error occurs in finalizing the symbols it will be reported to the ExecutionSession, rather than returned by blockingLookup. llvm-svn: 334722
* [ORC] Strip the Materializing flag off finalized symbols in VSOs.Lang Hames2018-06-141-3/+6
| | | | | | Finalized symbols are no longer in the materializing state. llvm-svn: 334721
* [EarlyCSE] Fix MSVC build. NFCI.Simon Pilgrim2018-06-141-9/+5
| | | | | | MSVC doesn't let you assign different lambdas through a ternary operator. llvm-svn: 334715
* [MC] Move MCAssembler::dump into the correct cpp file. NFCSam Clegg2018-06-142-22/+24
| | | | | | Differential Revision: https://reviews.llvm.org/D46556 llvm-svn: 334713
* [DWARFv5] Tolerate files not all having an MD5 checksum.Paul Robinson2018-06-143-15/+27
| | | | | | | | | | | | | | | | | | In some cases, for example when compiling a preprocessed file, the front-end is not able to provide an MD5 checksum for all files. When that happens, omit the MD5 checksums from the final DWARF, because DWARF doesn't have a way to indicate that some but not all files have a checksum. When assembling a .s file, and some but not all .file directives provide an MD5 checksum, issue a warning and don't emit MD5 into the DWARF. Fixes PR37623. Differential Revision: https://reviews.llvm.org/D48135 llvm-svn: 334710
* [mips] Correct predicates for MSA pseudo instructionsSimon Dardis2018-06-141-1/+2
| | | | llvm-svn: 334708
* [EarlyCSE] Propagate conditions of AND and OR instructionsMax Kazantsev2018-06-141-14/+43
| | | | | | | | | | | This patches teaches EarlyCSE to figure out that if `and i1 %x, %y` is true then both `%x` and `%y` are true in the taken branch, and if `or i1 %x, %y` is false then both `%x` and `%y` are false in non-taken branch. Fix for PR37635. Differential Revision: https://reviews.llvm.org/D47574 Reviewed By: reames llvm-svn: 334707
* [DebugInfo] Check size of variable in ConvertDebugDeclareToDebugValueBjorn Pettersson2018-06-142-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Do not convert a DbgDeclare to DbgValue if the store instruction only refer to a fragment of the variable described by the DbgDeclare. Problem was seen when for example having an alloca for an array or struct, and there were stores to individual elements. In the past we inserted a DbgValue intrinsics for each store, just as if the store wrote the whole variable. When handling store instructions we insert a DbgValue that indicates that the variable is "undefined", as we do not know which part of the variable that is updated by the store. When ConvertDebugDeclareToDebugValue is used with a load/phi instruction we assert that the referenced value is large enough to cover the whole variable. Afaict this should be true for all scenarios where those methods are used on trunk. If the assert blows in the future I guess we could simply skip to insert a dbg.value instruction. In the future I think we should examine which part of the variable that is accessed, and add a DbgValue instrinsic with an appropriate DW_OP_LLVM_fragment expression. Reviewers: dblaikie, aprantl, rnk Reviewed By: aprantl Subscribers: JDevlieghere, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D48024 llvm-svn: 334704
* [SLPVectorizer] Remove RawInstructionsData/getMainOpcode and merge into ↵Simon Pilgrim2018-06-141-49/+20
| | | | | | | | | | | | getSameOpcode This is part of the work to cleanup use of 'alternate' ops so we can use the more general SK_Select shuffle type. Only getSameOpcode calls getMainOpcode and much of the logic is repeated in both functions. This will require some reworking of D28907 but that patch has hit trouble and is unlikely to be completed anytime soon. Differential Revision: https://reviews.llvm.org/D48120 llvm-svn: 334701
* [CostModel] Cleanup isSingleSourceVectorMask to match other shuffle ↵Simon Pilgrim2018-06-141-10/+12
| | | | | | matchers. NFCI. llvm-svn: 334699
* [CostModel] Recognise REVERSE shuffle mask if the elements come from the ↵Simon Pilgrim2018-06-141-4/+11
| | | | | | second src llvm-svn: 334698
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-06-1414-31/+31
| | | | llvm-svn: 334687
* [x86] fix mappings of cvttp2si/cvttp2ui x86 intrinsics to x86-specific nodes ↵Craig Topper2018-06-144-43/+178
| | | | | | | | | | | | | | | | | | | | | and isel patterns (PR37551) Summary: The tests in: https://bugs.llvm.org/show_bug.cgi?id=37751 ...show miscompiles because we wrongly mapped and folded x86-specific intrinsics into generic DAG nodes. This patch corrects the mappings in X86IntrinsicsInfo.h and adds isel matching corresponding to the new patterns. The complete tests for the failure cases should be in avx-cvttp2si.ll and sse-cvttp2si.ll and avx512-cvttp2i.ll Reviewers: RKSimon, gbedwell, spatel Reviewed By: spatel Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D47993 llvm-svn: 334685
* AMDGPU/GlobalISel: Implement select() for 32-bit G_FADD and G_FMULTom Stellard2018-06-133-0/+16
| | | | | | | | | | | | Reviewers: arsenm, nhaehnle Reviewed By: arsenm Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D46171 llvm-svn: 334665
* Revert "Enable ThreadPool to queue tasks that return values."Zachary Turner2018-06-131-2/+19
| | | | | | | | This is failing to compile when LLVM_ENABLE_THREADS is false, and the fix is not immediately obvious, so reverting while I look into it. llvm-svn: 334658
* Reland: [Timers] Use the pass argument name for JSON keys in time-passesFrancis Visoiu Mistrih2018-06-131-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using clang --save-stats -mllvm -time-passes, both timers and stats end up in the same json file. We could end up with things like: { "asm-printer.EmittedInsts": 1, "time.pass.Virtual Register Map.wall": 2.9015541076660156e-04, "time.pass.Virtual Register Map.user": 2.0500000000000379e-04, "time.pass.Virtual Register Map.sys": 8.5000000000001741e-05, } This patch makes use of the pass argument name (if available) in the JSON key to end up with things like: { "asm-printer.EmittedInsts": 1, "time.pass.virtregmap.wall": 2.9015541076660156e-04, "time.pass.virtregmap.user": 2.0500000000000379e-04, "time.pass.virtregmap.sys": 8.5000000000001741e-05, } This also helps avoiding to write another JSON printer to handle all the cases that we could have in our pass names. Fixed test instead of adding a new one originally from r334649. Differential Revision: https://reviews.llvm.org/D48109 llvm-svn: 334657
* [WinASan] Don't instrument globals in sections containing '$'Reid Kleckner2018-06-131-5/+9
| | | | | | | | | | | | | Such globals are very likely to be part of a sorted section array, such the .CRT sections used for dynamic initialization. The uses its own sorted sections called ATL$__a, ATL$__m, and ATL$__z. Instead of special casing them, just look for the dollar sign, which is what invokes linker section sorting for COFF. Avoids issues with ASan and the ATL uncovered after we started instrumenting comdat globals on COFF. llvm-svn: 334653
* Revert r334649 "[Timers] Use the pass argument name for JSON keys in ↵Francis Visoiu Mistrih2018-06-131-5/+1
| | | | | | | | | | time-passes" This reverts commit r334649. This breaks a test. llvm-svn: 334651
* [Timers] Use the pass argument name for JSON keys in time-passesFrancis Visoiu Mistrih2018-06-131-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using clang --save-stats -mllvm -time-passes, both timers and stats end up in the same json file. We could end up with things like: { "asm-printer.EmittedInsts": 1, "time.pass.Virtual Register Map.wall": 2.9015541076660156e-04, "time.pass.Virtual Register Map.user": 2.0500000000000379e-04, "time.pass.Virtual Register Map.sys": 8.5000000000001741e-05, } This patch makes use of the pass argument name (if available) in the JSON key to end up with things like: { "asm-printer.EmittedInsts": 1, "time.pass.virtregmap.wall": 2.9015541076660156e-04, "time.pass.virtregmap.user": 2.0500000000000379e-04, "time.pass.virtregmap.sys": 8.5000000000001741e-05, } This also helps avoiding to write another JSON printer to handle all the cases that we could have in our pass names. Differential Revision: https://reviews.llvm.org/D48109 llvm-svn: 334649
* [X86] Move RCPSSr_Int, RSQRTSSr_Int, SQRTSDr_Int, SQRTSSr_Int to the correct ↵Craig Topper2018-06-131-4/+4
| | | | | | | | load folding table. They were in the operand 1 folding table, but their foldable operand is operand 2. llvm-svn: 334648
* Enable ThreadPool to support tasks that return values.Zachary Turner2018-06-131-19/+2
| | | | | | | | | | | | | | | | | | | | | Previously ThreadPool could only queue async "jobs", i.e. work that was done for its side effects and not for its result. It's useful occasionally to queue async work that returns a value. From an API perspective, this is very intuitive. The previous API just returned a shared_future<void>, so all we need to do is make it return a shared_future<T>, where T is the type of value that the operation returns. Making this work required a little magic, but ultimately it's not too bad. Instead of keeping a shared queue<packaged_task<void()>> we just keep a shared queue<unique_ptr<TaskBase>>, where TaskBase is a class with a pure virtual execute() method, then have a templated derived class that stores a packaged_task<T()>. Everything else works out pretty cleanly. Differential Revision: https://reviews.llvm.org/D48115 llvm-svn: 334643
* [AMDGPU] Corrected computeKnownBits for V_PERM_B32Stanislav Mekhanoshin2018-06-131-7/+8
| | | | | | Differential Revision: https://reviews.llvm.org/D48133 llvm-svn: 334640
* LTO: Keep file handles open for memory mapped files.Peter Collingbourne2018-06-135-102/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Windows we've observed that if you open a file, write to it, map it into memory and close the file handle, the contents of the memory mapping can sometimes be incorrect. That was what we did when adding an entry to the ThinLTO cache using the TempFile and MemoryBuffer classes, and it was causing intermittent build failures on Chromium's ThinLTO bots on Windows. More details are in the associated Chromium bug (crbug.com/786127). We can prevent this from happening by keeping a handle to the file open while the mapping is active. So this patch changes the mapped_file_region class to duplicate the file handle when mapping the file and close it upon unmapping it. One gotcha is that the file handle that we keep open must not have been created with FILE_FLAG_DELETE_ON_CLOSE, as otherwise the operating system will prevent other processes from opening the file. We can achieve this by avoiding the use of FILE_FLAG_DELETE_ON_CLOSE altogether. Instead, we use SetFileInformationByHandle with FileDispositionInfo to manage the delete-on-close bit. This lets us remove the hack that we used to use to clear the delete-on-close bit on a file opened with FILE_FLAG_DELETE_ON_CLOSE. A downside of using SetFileInformationByHandle/FileDispositionInfo as opposed to FILE_FLAG_DELETE_ON_CLOSE is that it prevents us from using CreateFile to open the file while the flag is set, even within the same process. This doesn't seem to matter for almost every client of TempFile, except for LockFileManager, which calls sys::fs::create_link to create a hard link from the lock file, and in the process of doing so tries to open the file. To prevent this change from breaking LockFileManager I changed it to stop using TempFile by effectively reverting r318550. Differential Revision: https://reviews.llvm.org/D48051 llvm-svn: 334630
* [AMDGPU] Change enqueue kernel handle typeYaxun Liu2018-06-131-1/+2
| | | | | | | | | | Currently the handle type is a global pointer which holds 8 bytes. We need a larger type which hold 16 bytes, therefore change it to [i64 x 2]. Differential Revision: https://reviews.llvm.org/D48094 llvm-svn: 334625
* [AMDGPU][MC] Enabled parsing of relocations on VALU instructionsDmitry Preobrazhensky2018-06-131-2/+2
| | | | | | | | | | See bug 37566: https://bugs.llvm.org/show_bug.cgi?id=37566 Reviewers: artem.tamazov, arsenm, nhaehnle Differential Revision: https://reviews.llvm.org/D47884 llvm-svn: 334622
* [CostModel] Recognise BROADCAST shuffle mask if the elements come from the ↵Simon Pilgrim2018-06-131-4/+11
| | | | | | second src llvm-svn: 334620
* [AMDGPU][MC][GFX8][GFX9] Allow LDS direct reads for BUFFER_LOAD_DWORDX2/X3/X4Dmitry Preobrazhensky2018-06-131-3/+19
| | | | | | | | | | See bug 37653: https://bugs.llvm.org/show_bug.cgi?id=37653 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D47885 llvm-svn: 334609
* [DAGCombiner] remove hasOneUse() check from fadd constants transformSanjay Patel2018-06-131-7/+6
| | | | | | | | | | | We're constant folding here, so we shouldn't check uses. This matches the IR optimizer behavior. The x86 test shows the expected win. The AArch64 test shows something else. This only seems to happen if the "generic" AArch64 CPU model is used by MachineCombiner, so I'll file a bug report to follow-up. llvm-svn: 334608
* AMDGPU: Move isSDNodeSourceOfDivergence() implementation to SITargetLoweringTom Stellard2018-06-134-71/+69
| | | | | | | | | | | | | | | | | | Summary: The code that handles ISD:Register and ISD::CopyFromReg assumes the target is amdgcn, so this is broken on r600. We don't need this analysis on r600 anyway so we can safely move it to SITargetLowering. Reviewers: alex-t, arsenm, nhaehnle Reviewed By: arsenm Subscribers: msearles, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D46298 llvm-svn: 334607
* [FPEnv] Expand constrained FP operationsCameron McInally2018-06-131-8/+88
| | | | | | | | | | Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
* Do not enforce absolute path argv0 in windowsHans Wennborg2018-06-131-29/+39
| | | | | | | | | | | | | | | | Even if we support no-canonical-prefix on clang-cl(https://reviews.llvm.org/D47480), argv0 becomes absolute path in clang-cl and that embeds absolute path in /showIncludes. This patch removes such full path normalization from InitLLVM on windows, and that removes absolute path from clang-cl output (obj/stdout/stderr) when debug flag is disabled. Patch by Takuto Ikuta! Differential Revision https://reviews.llvm.org/D47578 llvm-svn: 334602
* Revert "Improve handling of COPY instructions with identical value numbers"Krzysztof Parzyszek2018-06-131-53/+19
| | | | | | This reverts r334594, it breaks buildbots and fails with expensive checks. llvm-svn: 334598
* [mips][microMIPS] Extending size reduction pass with LWP and SWPZoran Jovanovic2018-06-134-55/+245
| | | | | | | | | | | | Author: milena.vujosevic.janicic Reviewers: sdardis The patch extends size reduction pass for MicroMIPS. It introduces reduction of two instructions into one instruction: Two SW instructions are transformed into one SWP instrucition. Two LW instructions are transformed into one LWP instrucition. Differential Revision: https://reviews.llvm.org/D39115 llvm-svn: 334595
* Improve handling of COPY instructions with identical value numbersKrzysztof Parzyszek2018-06-131-19/+53
| | | | | | Differential Revision: https://reviews.llvm.org/D48102 llvm-svn: 334594
* [x86] eliminate even more sign-bit tests with vector selectSanjay Patel2018-06-131-5/+4
| | | | | | | | | | | | | | | | | | | This shortcoming was noted in D47330, and the test diffs show we already had other examples where we failed to fold to a SHRUNKBLEND: /// Dynamic (non-constant condition) vector blend where only the sign bits /// of the condition elements are used. This is used to enforce that the /// condition mask is not valid for generic VSELECT optimizations. This patch implements an idea from D48043 and would obsolete that patch because it catches more cases (notable the AVX1 case that was missed there). All we're doing is allowing the existing transform to fire more often by removing the post-legalize constraint. All of the relevant feature checks and other predicates are left as-is. Differential Revision: https://reviews.llvm.org/D48078 llvm-svn: 334592
* [RISCV] Add codegen support for atomic load/stores with RV32AAlex Bradbury2018-06-134-2/+56
| | | | | | | | | | | | | | | Fences are inserted according to table A.6 in the current draft of version 2.3 of the RISC-V Instruction Set Manual, which incorporates the memory model changes and definitions contributed by the RISC-V Memory Consistency Model task group. Instruction selection failures will now occur for 8/16/32-bit atomicrmw and cmpxchg operations when targeting RV32IA until lowering for these operations is added in a follow-on patch. Differential Revision: https://reviews.llvm.org/D47589 llvm-svn: 334591
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