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* Add missing getters. They will be used in llvm-ar.Rafael Espindola2013-07-091-0/+32
| | | | llvm-svn: 185937
* Archive members cannot be larger than 4GB. Return a uint32_t.Rafael Espindola2013-07-091-5/+5
| | | | llvm-svn: 185936
* Add getHeader helper and move ToHeader to the cpp file.Rafael Espindola2013-07-091-2/+6
| | | | llvm-svn: 185933
* Add MC assembly/disassembly support for VRINT{A, N, P, M} to V8FP.Joey Gouly2013-07-093-3/+59
| | | | llvm-svn: 185929
* Add MC assembly/disassembly support for VRINT{Z, X, R} to V8FP.Joey Gouly2013-07-091-0/+21
| | | | llvm-svn: 185926
* [PowerPC] Support ".machine any"Ulrich Weigand2013-07-091-0/+27
| | | | | | | | | | | | The PowerPC assembler is supposed to provide a directive .machine that allows switching the supported CPU instruction set on the fly. Since we do not yet check CPU feature sets at all and always accept any available instruction, this is not really useful at this point. However, it makes sense to accept (and ignore) ".machine any" to avoid spuriously rejecting existing assembler files that use this. llvm-svn: 185924
* Revert r185872 - "Stop emitting weak symbols into the "coal" sections"Alexander Potapenko2013-07-091-6/+6
| | | | | | | | | | | | | This patch broke `make check-asan` on Mac, causing ld warnings like the following one: ld: warning: direct access in __GLOBAL__I_a to global weak symbol ___asan_mapping_scale means the weak symbol cannot be overridden at runtime. This was likely caused by different translation units being compiled with different visibility settings. The resulting test binaries crashed with incorrect ASan warnings. llvm-svn: 185923
* Add MC assembly/disassembly support for VCVT{A, N, P, M} to V8FP.Joey Gouly2013-07-093-6/+86
| | | | llvm-svn: 185922
* [SystemZ] Use MVC for simple load/store pairsRichard Sandiford2013-07-094-0/+86
| | | | | | | | | | | | Look for patterns of the form (store (load ...), ...) in which the two locations are known not to partially overlap. (Identical locations are OK.) These sequences are better implemented by MVC unless either the load or the store could use RELATIVE LONG instructions. The testcase showed that we weren't using LHRL and LGHRL for extload16, only sextloadi16. The patch fixes that too. llvm-svn: 185919
* [SystemZ] Use "STC;MVC" for memsetRichard Sandiford2013-07-093-0/+95
| | | | | | | | | | | | Use "STC;MVC" for memsets that are too big for two STCs or MV...Is yet small enough for a single MVC. As with memcpy, I'm leaving longer cases till later. The number of tests might seem excessive, but f33 & f34 from memset-04.ll failed the first cut because I'd not added the "?:" on the calculation of Size1. llvm-svn: 185918
* InstCombine: Fix typo in comment for visitICmpInstWithInstAndIntCstDavid Majnemer2013-07-091-2/+2
| | | | llvm-svn: 185916
* InstCombine: variations on 0xffffffff - x >= 4David Majnemer2013-07-091-0/+12
| | | | | | | | | | The following transforms are valid if -C is a power of 2: (icmp ugt (xor X, C), ~C) -> (icmp ult X, C) (icmp ult (xor X, C), -C) -> (icmp uge X, C) These are nice, they get rid of the xor. llvm-svn: 185915
* InstCombine: X & -C != -C -> X <= u ~CDavid Majnemer2013-07-091-0/+9
| | | | | | Tests were added in r185910 somehow. llvm-svn: 185912
* [PowerPC] Support .llong and fix .wordUlrich Weigand2013-07-091-1/+3
| | | | | | | | This adds support for the .llong PowerPC-specifc assembler directive. In doing so, I notices that .word is currently incorrect: it is supposed to define a 2-byte data element, not a 4-byte one. llvm-svn: 185911
* Commit r185909 was a misapplied patch, fix itDavid Majnemer2013-07-091-21/+13
| | | | llvm-svn: 185910
* InstCombine: add more transformsDavid Majnemer2013-07-091-0/+42
| | | | | | | | | C1-X <u C2 -> (X|(C2-1)) == C1 C1-X >u C2 -> (X|C2) == C1 X-C1 <u C2 -> (X & -C2) == C1 X-C1 >u C2 -> (X & ~C2) == C1 llvm-svn: 185909
* PPC: Allocate RS spill slot for unaligned i64 load/storeHal Finkel2013-07-091-2/+33
| | | | | | | | | | | | | | | | | | | This fixes another bug found by llvm-stress! If we happen to be doing an i64 load or store into a stack slot that has less than a 4-byte alignment, then the frame-index elimination may need to use an indexed load or store instruction (because the offset may not be a multiple of 4, a requirement of the STD/LD instructions). The extra register needed to hold the offset comes from the register scavenger, and it is possible that the scavenger will need to use an emergency spill slot. As a result, we need to make sure that a spill slot is allocated when doing an i64 load/store into a less-than-4-byte-aligned stack slot. Because test cases for things like this tend to be fairly fragile, I've concatenated a few small bugpoint-reduced test cases together to form the regression test. llvm-svn: 185907
* Compute the size of an archive member in the constructor.Rafael Espindola2013-07-091-14/+13
| | | | | | | It is always computed the same way (by parsing the header). Doing it in the constructor simplifies the callers a bit. llvm-svn: 185905
* Move some code out of line. No functionality change.Rafael Espindola2013-07-091-0/+70
| | | | llvm-svn: 185901
* X86: Add comment.Jim Grosbach2013-07-091-0/+5
| | | | llvm-svn: 185900
* X86 fast-isel: Avoid explicit AH subreg reference for [SU]Rem.Jim Grosbach2013-07-091-4/+31
| | | | | | | | | | | | | Explicit references to %AH for an i8 remainder instruction can lead to references to %AH in a REX prefixed instruction, which causes things to blow up. Do the same thing in FastISel as we do for DAG isel and instead shift %AX right by 8 bits and then extract the 8-bit subreg from that result. rdar://14203849 http://llvm.org/bugs/show_bug.cgi?id=16105 llvm-svn: 185899
* Make BinaryRef output correctly in case of empty data.Sean Silva2013-07-091-0/+4
| | | | | | | Previously, it would simply output nothing, but it should output an empty string `""`. llvm-svn: 185894
* Style fixes: remove unnecessary braces for one-statement if blocks, no else ↵Stephen Lin2013-07-091-54/+30
| | | | | | after return, etc. No funcionality change. llvm-svn: 185893
* Revert "DebugInfo: remove unused helper function getDICompositeType."Eric Christopher2013-07-091-0/+11
| | | | | | | This reverts commit r185876 as the functions appear to still be used by dragonegg. llvm-svn: 185890
* Fix commentEli Bendersky2013-07-081-3/+2
| | | | llvm-svn: 185888
* This patch changes the saved IRBuilder insert point from ↵Nadav Rotem2013-07-081-1/+2
| | | | | | | | | | BasicBlock::iterator to AssertingVH. Commit 185883 fixes a bug in the IRBuilder that should fix the ASan bot. AssertingVH can help in exposing some RAUW problems. Thanks Ben and Alexey! llvm-svn: 185886
* [objc-arc] Fix assertion in EraseInstruction so that noop on null calls when ↵Michael Gottesman2013-07-081-1/+3
| | | | | | | | passed null do not trigger the assert. The specific case of interest is when objc_retainBlock is passed null. llvm-svn: 185885
* DebugInfo: remove unused helper function getDICompositeType.Manman Ren2013-07-081-11/+0
| | | | llvm-svn: 185876
* Stop emitting weak symbols into the "coal" sections.Bill Wendling2013-07-081-6/+6
| | | | | | | | | | | | | | | | | The Mach-O linker has been able to support the weak-def bit on any symbol for quite a while now. The compiler however continued to place these symbols into a "coal" section, which required the linker to map them back to the base section name. Replace the sections like this: __TEXT/__textcoal_nt instead use __TEXT/__text __TEXT/__const_coal instead use __TEXT/__const __DATA/__datacoal_nt instead use __DATA/__data <rdar://problem/14265330> llvm-svn: 185872
* Update comment to avoid mentioning DbgValues which is an instanceEric Christopher2013-07-081-1/+1
| | | | | | variable later in the class. llvm-svn: 185866
* Revert r185852.Manman Ren2013-07-081-5/+0
| | | | llvm-svn: 185861
* Find xdot or xdot.py.Matt Arsenault2013-07-081-3/+3
| | | | | | Ubuntu installs this as xdot, so finding xdot.py would fail. llvm-svn: 185860
* [PowerPC] Always use "assembler dialect" 1Ulrich Weigand2013-07-089-42/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A setting in MCAsmInfo defines the "assembler dialect" to use. This is used by common code to choose between alternatives in a multi-alternative GNU inline asm statement like the following: __asm__ ("{sfe|subfe} %0,%1,%2" : "=r" (out) : "r" (in1), "r" (in2)); The meaning of these dialects is platform specific, and GCC defines those for PowerPC to use dialect 0 for old-style (POWER) mnemonics and 1 for new-style (PowerPC) mnemonics, like in the example above. To be compatible with inline asm used with GCC, LLVM ought to do the same. Specifically, this means we should always use assembler dialect 1 since old-style mnemonics really aren't supported on any current platform. However, the current LLVM back-end uses: AssemblerDialect = 1; // New-Style mnemonics. in PPCMCAsmInfoDarwin, and AssemblerDialect = 0; // Old-Style mnemonics. in PPCLinuxMCAsmInfo. The Linux setting really isn't correct, we should be using new-style mnemonics everywhere. This is changed by this commit. Unfortunately, the setting of this variable is overloaded in the back-end to decide whether or not we are on a Darwin target. This is done in PPCInstPrinter (the "SyntaxVariant" is initialized from the MCAsmInfo AssemblerDialect setting), and also in PPCMCExpr. Setting AssemblerDialect to 1 for both Darwin and Linux no longer allows us to make this distinction. Instead, this patch uses the MCSubtargetInfo passed to createPPCMCInstPrinter to distinguish Darwin targets, and ignores the SyntaxVariant parameter. As to PPCMCExpr, this patch adds an explicit isDarwin argument that needs to be passed in by the caller when creating a target MCExpr. (To do so this patch implicitly also reverts commit 184441.) llvm-svn: 185858
* PPC: Mark vector CC action for SETO and SETONE as ExpandHal Finkel2013-07-081-0/+3
| | | | | | | | Another bug found by llvm-stress! This fixes hitting llvm_unreachable("Invalid integer vector compare condition"); at the end of getVCmpInst in PPCISelDAGToDAG. llvm-svn: 185855
* Add a comment to this change, requested by Eric Christopher.Joey Gouly2013-07-081-0/+4
| | | | llvm-svn: 185853
* StringRef: add DenseMapInfo for StringRef.Manman Ren2013-07-081-0/+5
| | | | | | | | Remove the implementation in include/llvm/Support/YAMLTraits.h. Added a DenseMap type DITypeHashMap in DebugInfo.h: DenseMap<std::pair<StringRef, unsigned>, MDNode*> llvm-svn: 185852
* Debug Info: clean up usage of Verify.Manman Ren2013-07-083-20/+20
| | | | | | | No functionality change. It should suffice to check the type of a debug info metadata, instead of calling Verify. llvm-svn: 185847
* ARM: Improve codegen for generic vselect.Jim Grosbach2013-07-081-0/+18
| | | | | | | | Fall back to by-element insert rather than building it up on the stack. rdar://14351991 llvm-svn: 185846
* DebugInfo: Correct comment & re-format a nearby loopDavid Blaikie2013-07-081-5/+3
| | | | llvm-svn: 185844
* Fix a SCEV update problem.Shuxin Yang2013-07-081-2/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The symptom is seg-fault, and the root cause is that a SCEV contains a SCEVUnknown which has null-pointer to a llvm::Value. This is how the problem take place: =================================== 1). In the pristine input IR, there are two relevant instrutions Op1 and Op2, Op1's corresponding SCEV (denoted as SCEV(op1)) is a SCEVUnknown, and SCEV(Op2) contains SCEV(Op1). None of these instructions are dead. Op1 : V1 = ... ... Op2 : V2 = ... // directly or indirectly (data-flow) depends on Op1 2) Optimizer (LSR in my case) generates an instruction holding the equivalent value of Op1, making Op1 dead. Op1': V1' = ... Op1: V1 = ... ; now dead) Op2 : V2 = ... //Now deps on Op1', but the SCEV(Op2) still contains SCEV(Op1) 3) Op1 is deleted, and call-back function is called to reset SCEV(Op1) to indicate it is invalid. However, SCEV(Op2) is not invalidated as well. 4) Following pass get the cached, invalid SCEV(Op2), and try to manipulate it, and cause segfault. The fix: ======== It seems there is no clean yet inexpensive fix. I write to dev-list soliciting good solution, unforunately no ack. So, I decide to fix this problem in a brute-force way: When ScalarEvolution::getSCEV is called, check if the cached SCEV contains a invalid SCEVUnknow, if yes, remove the cached SCEV, and re-evaluate the SCEV from scratch. I compile buch of big *.c and *.cpp, fortunately, I don't see any increase in compile time. Misc: ===== The reduced test-case has 2357 lines of code+other-stuff, too big to commit. rdar://14283433 llvm-svn: 185843
* DebugInfo: Simplify Address Pool index handling.David Blaikie2013-07-081-5/+3
| | | | | | | | | | Since the pool indexes are necessarily sequential and contiguous, just insert things in the right place rather than having to sort the sequence after the fact. No functionality change. llvm-svn: 185842
* PPC: Mark vector FREM as Expand by defaultHal Finkel2013-07-081-0/+1
| | | | | | | Another bug found by llvm-stress! This fixes crashing with: LLVM ERROR: Cannot select: v4f32 = frem ... llvm-svn: 185840
* We now always create files with the correct permissions. Simplify the interface.Rafael Espindola2013-07-082-65/+1
| | | | llvm-svn: 185834
* Create files with the correct permission instead of changing it afterwards.Rafael Espindola2013-07-081-22/+7
| | | | | | Not intended functionality change. llvm-svn: 185830
* [PowerPC] Support time base instructionsUlrich Weigand2013-07-081-0/+6
| | | | | | | | This adds support for the old-style time base instructions; while new programs are supposed to use mfspr, the mftb instructions are still supported and in use by existing assembler files. llvm-svn: 185829
* [PowerPC] Support basic compare mnemonicsUlrich Weigand2013-07-083-0/+43
| | | | | | | | | | | | | | | | | This adds support for the basic mnemoics (with the L operand) for the fixed-point compare instructions. These are defined as aliases for the already existing CMPW/CMPD patterns, depending on the value of L. This requires use of InstAlias patterns with immediate literal operands. To make this work, we need two further changes: - define a RegisterPrefix, because otherwise literals 0 and 1 would be parsed as literal register names - provide a PPCAsmParser::validateTargetOperandClass routine to recognize immediate literals (like ARM does) llvm-svn: 185826
* Improve the comment from r185794 (re: PromoteIntRes_BUILD_VECTOR)Hal Finkel2013-07-081-2/+4
| | | | | | | In response to Duncan's review, I believe that the original comment was not as clear as it could be. Hopefully, this is better. llvm-svn: 185824
* [PowerPC] Fix PR16556 (handle undef ppcf128 in LowerFP_TO_INT).Bill Schmidt2013-07-081-0/+9
| | | | | | | | | | | | | | | | | | | | | PPCTargetLowering::LowerFP_TO_INT() expects its source operand to be either an f32 or f64, but this is not checked. A long double (ppcf128) operand will normally be custom-lowered to a conversion to f64 in this context. However, this isn't the case for an UNDEF node. This patch recognizes a ppcf128 as a legal source operand for FP_TO_INT only if it's an undef, in which case it creates an undef of the target type. At some point we might want to do a wholesale custom lowering of ISD::UNDEF when the type is ppcf128, but it's not really clear that's a great idea, and probably more work than it's worth for a situation that only arises in the case of a programming error. At this point I think simple is best. The test case comes from PR16556, and is a crash-test only. llvm-svn: 185821
* InstCombine: Fold X-C1 <u 2 -> (X & -2) == C1David Majnemer2013-07-081-0/+8
| | | | | | | | | | | Back in r179493 we determined that two transforms collided with each other. The fix back then was to reorder the transforms so that the preferred transform would give it a try and then we would try the secondary transform. However, it was noted that the best approach would canonicalize one transform into the other, removing the collision and allowing us to optimize IR given to us in that form. llvm-svn: 185808
* Reuse %rax after calling __chkstk on win64Nico Rieck2013-07-082-7/+9
| | | | | | Reapply this as I reverted the wrong commit. llvm-svn: 185807
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