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* ARM: Proactively ensure that the LowerCallResult hack for 'this'-returns is ↵Stephen Lin2013-06-263-4/+23
| | | | | | | | not used for incompatible calling conventions. (Currently, ARM 'this'-returns are handled in the standard calling convention case by treating R0 as preserved and doing some extra magic in LowerCallResult; this may not apply to calling conventions added in the future so this patch provides and documents an interface for indicating such) llvm-svn: 185024
* Debug Info: clean up usage of Verify.Manman Ren2013-06-263-6/+6
| | | | | | | | No functionality change. It should suffice to check the type of a debug info metadata, instead of calling Verify. llvm-svn: 185020
* Minor formatting fix to ARMBaseRegisterInfo::getCalleeSavedRegsStephen Lin2013-06-261-7/+5
| | | | llvm-svn: 185016
* Rename PathV2 to just Path now that it is the only one.Rafael Espindola2013-06-264-11/+11
| | | | llvm-svn: 185015
* [mips] Do not emit ".option pic0" if target is mips64.Akira Hatanaka2013-06-261-1/+1
| | | | llvm-svn: 185012
* [mips] Improve code generation for constant multiplication using shifts, ↵Akira Hatanaka2013-06-261-0/+54
| | | | | | | | adds and subs. llvm-svn: 185011
* Use enums instead of raw octal values.Rafael Espindola2013-06-261-1/+0
| | | | | | Patch by 罗勇刚(Yonggang Luo). llvm-svn: 184971
* Erase all of the instructions that we RAUWedNadav Rotem2013-06-261-0/+9
| | | | llvm-svn: 184969
* Add a subtarget feature 'v8' to the ARM backend.Joey Gouly2013-06-268-4/+25
| | | | | | This allows for targeting the ARMv8 AArch32 variant. llvm-svn: 184967
* Do not add cse-ed instructions into the visited map because we dont want to ↵Nadav Rotem2013-06-261-5/+9
| | | | | | consider them as a candidate for replacement of instructions to be visited. llvm-svn: 184966
* ARM: fix more cases where predication may or may not be allowedTim Northover2013-06-264-36/+35
| | | | | | | | | | Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. llvm-svn: 184965
* ARM: allow predicated barriers in Thumb modeTim Northover2013-06-262-18/+16
| | | | | | | The barrier instructions are only "always-execute" in ARM mode, they can quite happily sit inside an IT block in Thumb. llvm-svn: 184964
* Remove the 'generic' CPU from the ARM eabi attributes printer.Joey Gouly2013-06-261-9/+2
| | | | | | Make v4 the default ARM architecture attribute, to match CodeGen. llvm-svn: 184962
* PathV1 is deprecated since the 18th of Dec 2010. Remove it.Rafael Espindola2013-06-264-1164/+0
| | | | llvm-svn: 184960
* [PowerPC] Accept 17-bit signed immediates for addisUlrich Weigand2013-06-263-4/+26
| | | | | | | | | | | | | | | | | | | The assembler currently strictly verifies that immediates for s16imm operands are in range (-32768 ... 32767). This matches the behaviour of the GNU assembler, with one exception: gas allows, as a special case, operands in an extended range (-65536 .. 65535) for the addis instruction only (and its extended mnemonic lis). The main reason for this seems to be to allow using unsigned 16-bit operands for lis, e.g. like lis %r1, 0xfedc. Since this has been supported by gas for a long time, and assembler source code seen "in the wild" actually exploits this feature, this patch adds equivalent support to LLVM for compatibility reasons. llvm-svn: 184946
* [PowerPC] Support symbolic u16imm operandsUlrich Weigand2013-06-265-9/+14
| | | | | | | | | | | | | | Currently, all instructions taking s16imm operands support symbolic operands. However, for u16imm operands, we only support actual immediate integers. This causes the assembler to reject code like ori %r5, %r5, symbol@l This patch changes the u16imm operand definition to likewise accept symbolic operands. In fact, s16imm and u16imm can share the same encoding routine, now renamed to getImm16Encoding. llvm-svn: 184944
* ARM: operands should be explicit when disassembledAmaury de la Vieuville2013-06-261-8/+3
| | | | llvm-svn: 184943
* [Sparc]: Add memory operands for the frame references in the storeRegToStackSlotVenkatraman Govindaraju2013-06-261-8/+30
| | | | | | and loadRegFromStackSlot. llvm-svn: 184935
* Fixed a comment.Elena Demikhovsky2013-06-261-2/+2
| | | | llvm-svn: 184933
* Optimized integer vector multiplication operation by replacing it with ↵Elena Demikhovsky2013-06-262-22/+63
| | | | | | shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector. llvm-svn: 184931
* [asan] workaround for PR16277: don't instrument AllocaInstr with alignment ↵Kostya Serebryany2013-06-261-1/+2
| | | | | | more than the redzone size llvm-svn: 184928
* [asan] add option -asan-keep-uninstrumented-functionsKostya Serebryany2013-06-261-4/+47
| | | | llvm-svn: 184927
* Remove calls to Path in #ifdefs that don't seem to be used in any of the ↵Rafael Espindola2013-06-261-3/+3
| | | | | | bots :-( llvm-svn: 184920
* Fix the build when __APPLE__ is defined.Rafael Espindola2013-06-261-1/+5
| | | | llvm-svn: 184917
* Remove sys::GetMainExecutable.Rafael Espindola2013-06-262-116/+0
| | | | llvm-svn: 184916
* Port GetMainExecutable over to PathV2.Rafael Espindola2013-06-262-0/+113
| | | | | | I will remove the V1 version as soon as I change clang in the next commit. llvm-svn: 184914
* Remove PathWithStatus.Rafael Espindola2013-06-262-49/+0
| | | | llvm-svn: 184910
* dbgs() << Instruction doesn't print a newline on the end any more. Update theseNick Lewycky2013-06-261-5/+5
| | | | | | | debug statements to add a missing newline. Also canonicalize to '\n' instead of "\n"; the latter calls a function with a loop the former does not. llvm-svn: 184897
* s/C++0x/C++11/Adrian Prantl2013-06-251-1/+1
| | | | llvm-svn: 184892
* SLPVectorizer: support slp-vectorization of PHINodes between basic blocksNadav Rotem2013-06-251-1/+96
| | | | llvm-svn: 184888
* Print block frequencies in decimal form.Jakob Stoklund Olesen2013-06-251-1/+10
| | | | | | | | | This is easier to read than the internal fixed-point representation. If anybody knows the correct algorithm for converting fixed-point numbers to base 10, feel free to fix it. llvm-svn: 184881
* R600: Use new getNamedOperandIdx function generated by TableGenTom Stellard2013-06-2510-228/+160
| | | | llvm-svn: 184880
* X86 cost model: Vectorizing integer division is a bad ideaArnold Schwaighofer2013-06-251-0/+25
| | | | | | radar://14057959 llvm-svn: 184872
* Fix SROA to avoid unnecessary scalar conversions for 1-element vectors.Bob Wilson2013-06-251-15/+16
| | | | | | | | | | | When a 1-element vector alloca is promoted, a store instruction can often be rewritten without converting the value to a scalar and using an insertelement instruction to stuff it into the new alloca. This patch just adds a check to skip that conversion when it is unnecessary. This turns out to be really important for some ARM Neon operations where <1 x i64> is used to get around the fact that i64 is not a legal type. llvm-svn: 184870
* Remove unused code. No functionality change.Manman Ren2013-06-251-4/+0
| | | | llvm-svn: 184866
* The GCDA 402 format won't have a second checksum either.Bill Wendling2013-06-251-1/+1
| | | | llvm-svn: 184864
* [PowerPC] Support @got modifierUlrich Weigand2013-06-252-0/+27
| | | | | | | Add VK_... values and relocation types necessary to support the @got family of modifiers. Used by the asm parser only. llvm-svn: 184860
* Move GetEXESuffix to the one place it is used.Rafael Espindola2013-06-252-8/+0
| | | | llvm-svn: 184853
* Remove sys::PathSeparator.Rafael Espindola2013-06-252-4/+0
| | | | llvm-svn: 184852
* R600: Consolidate expansion of v2i32/v4i32 ops for EG/SIAaron Watry2013-06-253-49/+22
| | | | | | | | | | By default, we expand these operations for both EG and SI. Move the duplicated code into a common space for now. If the targets ever actually implement these operations as instructions, we can override that in the relevant target. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184848
* R600/SI: Expand xor v2i32/v4i32Aaron Watry2013-06-251-0/+3
| | | | | | | Add test cases for both vector sizes on SI and also add v2i32 test for EG. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184846
* R600/SI: Expand urem of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
| | | | | | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Note: I followed the guidance of the v4i32 EG check... UREM produces really complex code, so let's just check that the instruction was lowered successfully. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184844
* R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EGAaron Watry2013-06-252-0/+4
| | | | | | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Note: I followed the guidance of the v4i32 EG check... UDIV produces really complex code, so let's just check that the instruction was lowered successfully. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184843
* R600/SI: Expand ashr of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+2
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184842
* R600/SI: Expand srl of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+2
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184841
* R600/SI: Expand shl of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184840
* R600/SI: Expand or of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184839
* R600/SI: Expand mul of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184838
* R600/SI: Expand and of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184837
* BlockFrequency: Bump up the entry frequency a bit.Benjamin Kramer2013-06-252-10/+0
| | | | | | | This is a band-aid to fix the most severe regressions we're seeing from basing spill decisions on block frequencies, until we have a better solution. llvm-svn: 184835
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