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* [SystemZ] Enable the use of MVC for frame-to-frame spillsRichard Sandiford2013-07-051-10/+2
| | | | | | | | | | ...now that the problem that prompted the restriction has been fixed. The original spill-02.py was a compromise because at the time I couldn't find an example that actually failed without the two scavenging slots. The version included here did. llvm-svn: 185701
* [PowerPC] Add some special @got@tprel fixup casesUlrich Weigand2013-07-051-0/+20
| | | | | | | | | | | | | | | When a target@got@tprel or target@got@tprel@l symbol variant is used in a fixup_ppc_half16 (*not* fixup_ppc_half16ds) context, we currently fail, since the corresponding R_PPC64_GOT_TPREL16 / R_PPC64_GOT_TPREL16_LO relocation types do not exist. However, since such symbol variants resolve to GOT offsets which are always 4-aligned, we can simply instead use the _DS variants of the relocation types, which *do* exist. The same applies for the @got@dtprel variants. llvm-svn: 185700
* [SystemZ] Allocate a second register scavenging slotRichard Sandiford2013-07-051-2/+6
| | | | | | | | | | | | | This is another prerequisite for frame-to-frame MVC copies. I'll commit the patch that makes use of the slot separately. The downside of trying to test many corner cases with each of the available addressing modes is that a fair few tests need to account for the new frame layout. I do still think it's useful to have all these tests though, since it's something that wouldn't get much coverage otherwise. llvm-svn: 185698
* [SystemZ] Clean up register scavenging codeRichard Sandiford2013-07-055-62/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | SystemZ wants normal register scavenging slots, as close to the stack or frame pointer as possible. The only reason it was using custom code was because PrologEpilogInserter assumed an x86-like layout, where the frame pointer is at the opposite end of the frame from the stack pointer. This meant that when frame pointer elimination was disabled, the slots ended up being as close as possible to the incoming stack pointer, which is the opposite of what we want on SystemZ. This patch adds a new knob to say which layout is used and converts SystemZ to use target-independent scavenging slots. It's one of the pieces needed to support frame-to-frame MVCs, where two slots might be required. The ABI requires us to allocate 160 bytes for calls, so one approach would be to use that area as temporary spill space instead. It would need some surgery to make sure that the slot isn't live across a call though. I stuck to the "isFPCloseToIncomingSP - ..." style comment on the "do what the surrounding code does" principle. The FP case is already covered by several Systemz/frame-* tests, which fail without the PrologueEpilogueInserter change, so no new ones are needed. No behavioural change intended. llvm-svn: 185696
* [PowerPC] Support @tls in the asm parserUlrich Weigand2013-07-059-22/+70
| | | | | | | | | | | | | | | | | | This adds support for the last missing construct to parse TLS-related assembler code: add 3, 4, symbol@tls The ADD8TLS currently hard-codes the @tls into the assembler string. This cannot be handled by the asm parser, since @tls is parsed as a symbol variant. This patch changes ADD8TLS to have the @tls suffix printed as symbol variant on output too, which allows us to remove the isCodeGenOnly marker from ADD8TLS. This in turn means that we can add a AsmOperand to accept @tls marked symbols on input. As a side effect, this means that the fixup_ppc_tlsreg fixup type is no longer necessary and can be merged into fixup_ppc_nofixup. llvm-svn: 185692
* Simplify code. No functionality change.Benjamin Kramer2013-07-051-7/+3
| | | | llvm-svn: 185689
* PR16490: fix a crash in ARMDAGToDAGISel::SelectInlineAsm.Joey Gouly2013-07-051-0/+6
| | | | | | | | | | | In the SelectionDAG immediate operands to inline asm are constructed as two separate operands. The first is a constant of value InlineAsm::Kind_Imm and the second is a constant with the value of the immediate. In ARMDAGToDAGISel::SelectInlineAsm, if we reach an operand of Kind_Imm we should skip over the next operand too. llvm-svn: 185688
* Use the raw member names in Archive::Archive.Rafael Espindola2013-07-051-15/+10
| | | | | | | This a bit more efficient and avoids having a function that uses the string table being called by a function that searches for it. llvm-svn: 185680
* InstCombine: (icmp eq B, 0) | (icmp ult A, B) -> (icmp ule A, B-1)David Majnemer2013-07-051-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This transform allows us to turn IR that looks like: %1 = icmp eq i64 %b, 0 %2 = icmp ult i64 %a, %b %3 = or i1 %1, %2 ret i1 %3 into: %0 = add i64 %b, -1 %1 = icmp uge i64 %0, %a ret i1 %1 which means we go from lowering: cmpq %rsi, %rdi setb %cl testq %rsi, %rsi sete %al orb %cl, %al ret to lowering: decq %rsi cmpq %rdi, %rsi setae %al ret llvm-svn: 185677
* Remove use of asymmetric std::lower_bound comparator.Ahmed Bougacha2013-07-041-12/+18
| | | | | | VS 2008 doesn't like it when in debug mode. llvm-svn: 185676
* DebugInfo: Consider global variables without locations to be validDavid Blaikie2013-07-041-3/+0
| | | | | | | | | | | | | | | | | We were being a bit too aggresive here in classifying global variables with no global reference or constant value to be invalid - this would cause LLVM to not emit the DWARF description of the global variable if it had been optimized away, which isn't helpful for users who might benefit from the global variable's description even if there's no location information. This also fixes a crasher issue here that I was unable to reduce a test case for - involving a using decl (& subsequent DW_TAG_imported_declaration ) of such a global variable that, once optimized away, would crash when an attempt to emit the imported declaration was made. llvm-svn: 185675
* Use a OwningPtr instead of a manual delete.Rafael Espindola2013-07-041-5/+3
| | | | llvm-svn: 185673
* Initialize object file info before output streamerNico Rieck2013-07-041-2/+2
| | | | | | | | | r179494 switched to using the object file info to retrieve the default text section for some MC streamers. It is possible that initializing an MC streamer can request sections before the object file info is initialized when the AutoInitSections flag is set on the streamer. llvm-svn: 185670
* MC: Add .section directive to COFFNico Rieck2013-07-041-0/+172
| | | | | | | | Supports GAS flags "abdnrswxy". No support for alignment or subsections. Fixes PR16366. llvm-svn: 185669
* InstCombine: Reimplementation of visitUDivOperandDavid Majnemer2013-07-041-56/+139
| | | | | | | | | | | This transform was originally added in r185257 but later removed in r185415. The original transform would create instructions speculatively and then discard them if the speculation was proved incorrect. This has been replaced with a scheme that splits the transform into two parts: preflight and fold. While we preflight, we build up fold actions that inform the folding stage on how to act. llvm-svn: 185667
* Add support for archives with no symbol table or string table.Rafael Espindola2013-07-041-1/+1
| | | | llvm-svn: 185664
* Fix leak. Should bring back the valgrind bot.Rafael Espindola2013-07-041-0/+1
| | | | llvm-svn: 185663
* [PowerPC] Implement writeNopDataUlrich Weigand2013-07-041-4/+8
| | | | | | | | | | | This implements a proper PPCAsmBackend::writeNopData routine that actually writes PowerPC nop instructions. This fixes the last remaining difference in object file output (text section) between the integrated assembler and GNU as that I've seen anywhere. llvm-svn: 185662
* Remove an unneeded call to 'UpdateThumbVFPPredicate', spotted by Amaury.Joey Gouly2013-07-041-1/+0
| | | | llvm-svn: 185651
* Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} ↵Joey Gouly2013-07-044-2/+94
| | | | | | | | | instructions. This adds a new decoder table/namespace 'VFPV8', as these instructions have their top 4 bits as 0b1111, while other Thumb instructions have 0b1110. llvm-svn: 185642
* [PowerPC] Add all trap mnemonicsUlrich Weigand2013-07-041-0/+31
| | | | | | | This adds support for all basic and extended variants of the trap instructions to the asm parser. llvm-svn: 185638
* [PowerPC] Add asm parser support for CR expressionsUlrich Weigand2013-07-042-5/+84
| | | | | | | | This adds support for specifying condition registers and condition register fields via expressions using the symbols defined by the PowerISA, like "4*cr2+eq". llvm-svn: 185633
* SimplifyCFG: Teach switch generation some patterns that instcombine forms.Benjamin Kramer2013-07-041-1/+27
| | | | | | | | This allows us to create switches even if instcombine has munged two of the incombing compares into one and some bit twiddling. This was motivated by enum compares that are common in clang. llvm-svn: 185632
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-049-48/+0
| | | | | | These exception-related opcodes are not used any longer. llvm-svn: 185625
* Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.Joey Gouly2013-07-042-1/+57
| | | | llvm-svn: 185620
* Typo.Jakob Stoklund Olesen2013-07-041-1/+1
| | | | llvm-svn: 185618
* Simplify landing pad lowering.Jakob Stoklund Olesen2013-07-042-26/+21
| | | | | | | | | | | | | | | | | | | | | Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering landing pad arguments. These nodes were previously legalized into CopyFromReg nodes, but that never worked properly because the CopyFromReg node weren't guaranteed to be scheduled at the top of the basic block. This meant the exception pointer and selector registers could be clobbered before being copied to a virtual register. This patch copies the two physical registers to virtual registers at the beginning of the basic block, and lowers the landingpad instruction directly to two CopyFromReg nodes reading the *virtual* registers. This is safe because virtual registers don't get clobbered. A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION nodes. llvm-svn: 185617
* FastISel can only apend to basic blocks.Jakob Stoklund Olesen2013-07-041-8/+5
| | | | | | | | | | Compute the insertion point from the end of the basic block instead of skipping labels from the front. This caused failures in landing pads when live-in copies where inserted before instruction selection. llvm-svn: 185616
* Live-in copies go *after* EH_LABELs.Jakob Stoklund Olesen2013-07-041-1/+1
| | | | | | This will soon be tested by exception handling working at all. llvm-svn: 185615
* Tabs to spaces. No functionality change.Nick Lewycky2013-07-041-10/+10
| | | | llvm-svn: 185612
* Add a space between closing template '>' to unbreak build.Craig Topper2013-07-041-3/+3
| | | | llvm-svn: 185607
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-0427-62/+62
| | | | | | specifying the vector size. llvm-svn: 185606
* Reapply r185601 with a fix for the cmake build.Eric Christopher2013-07-041-0/+10
| | | | llvm-svn: 185605
* Temporarily revert 185601 as it caused cmake build regressions.Eric Christopher2013-07-041-10/+0
| | | | llvm-svn: 185603
* Add support for futimens for platforms that don't support futimes.Eric Christopher2013-07-041-0/+10
| | | | | | Patch by pashev.igor. llvm-svn: 185601
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-0411-21/+74
| | | | | | | Revert "Simplify landing pad lowering." Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes." llvm-svn: 185600
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-039-48/+0
| | | | | | These exception-related opcodes are not used any longer. llvm-svn: 185596
* Simplify landing pad lowering.Jakob Stoklund Olesen2013-07-032-26/+21
| | | | | | | | | | | | | | | | | | | | | Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering landing pad arguments. These nodes were previously legalized into CopyFromReg nodes, but that never worked properly because the CopyFromReg node weren't guaranteed to be scheduled at the top of the basic block. This meant the exception pointer and selector registers could be clobbered before being copied to a virtual register. This patch copies the two physical registers to virtual registers at the beginning of the basic block, and lowers the landingpad instruction directly to two CopyFromReg nodes reading the *virtual* registers. This is safe because virtual registers don't get clobbered. A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION nodes. llvm-svn: 185595
* Add MachineBasicBlock::addLiveIn().Jakob Stoklund Olesen2013-07-031-0/+33
| | | | | | | This function adds a live-in physical register to an MBB and ensures that it is copied to a virtual register immediately. llvm-svn: 185594
* Have ARMBaseRegisterInfo::getCallPreservedMask return the 'correct' mask for ↵Stephen Lin2013-07-032-10/+13
| | | | | | | | the GHC calling convention. This is purely academic because GHC calls are always tail calls so the register mask will never be used; however, this change makes the code clearer and brings the ARM implementation of the GHC calling convention in line with the X86 implementation. Also, it might save someone else some time trying to figuring out what is happening... llvm-svn: 185592
* Hoist all of the Entry.getLoc() calls int a single variable.Eric Christopher2013-07-031-7/+8
| | | | llvm-svn: 185589
* Make DotDebugLocEntry a class, reorder the members along with commentsEric Christopher2013-07-032-14/+29
| | | | | | for them and update all uses. llvm-svn: 185588
* [ARM] Improve the instruction selection of vector loads.Quentin Colombet2013-07-031-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | In the ARM back-end, build_vector nodes are lowered to a target specific build_vector that uses floating point type. This works well, unless the inserted bitcasts survive until instruction selection. In that case, they incur moves between integer unit and floating point unit that may result in inefficient code. In other words, this conversion may introduce artificial dependencies when the code leading to the build vector cannot be completed with a floating point type. In particular, this happens when loads are not aligned. Before this patch, in that case, the compiler generates general purpose loads and creates the floating point vector from them, instead of directly using the vector unit. The patch uses a vector friendly sequence of code when the inserted bitcasts to floating point survived DAGCombine. This is done by a target specific DAGCombine that changes the target specific build_vector into a sequence of insert_vector_elt that get rid of the bitcasts. <rdar://problem/14170854> llvm-svn: 185587
* Elaborate on comment.Eric Christopher2013-07-031-1/+1
| | | | llvm-svn: 185586
* Add names to the header file since they help in documenting the APIEric Christopher2013-07-031-10/+11
| | | | | | (and for consistency). llvm-svn: 185585
* [PowerPC] FreeBSD does not require f128 in its data layout string.Bill Schmidt2013-07-031-1/+1
| | | | | | Long double is 64 bits on FreeBSD PPC, so the f128 entry is superfluous. llvm-svn: 185583
* ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying ↵Tilmann Scheller2013-07-031-9/+5
| | | | | | | | | | | | | | certain Thumb2 add immediate T3 encodings. Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding. The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process. This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly. Fixes <rdar://problem/14224440>. llvm-svn: 185575
* Move typedefs inside the class that they belong to.Eric Christopher2013-07-031-10/+7
| | | | llvm-svn: 185573
* Use an RWMutex instead of a Mutex in PassRegistry.Chad Rosier2013-07-031-10/+11
| | | | | | Patch by Alex Crichton <alex@crichton.co>. Approved by Chris Lattner. llvm-svn: 185566
* [PowerPC] Support lmw/stmw in the asm parserUlrich Weigand2013-07-031-0/+8
| | | | | | | This adds support for the load/store multiple instructions, currently used by the asm parser only. llvm-svn: 185564
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