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* [libFuzzer] add -trace_malloc= flagKostya Serebryany2016-10-137-5/+70
| | | | llvm-svn: 284149
* [AArch64][RegisterBankInfo] Switch to fully static opds mapping for G_BITCAST.Quentin Colombet2016-10-131-4/+10
| | | | | | NFC. llvm-svn: 284146
* Add interface to compute number of physical cores on host systemTeresa Johnson2016-10-132-1/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For now I have only added support for x86_64 Linux, but other systems can be added incrementally. This is to be used for setting the default parallelism for ThinLTO backends (instead of thread::hardware_concurrency which includes hyperthreading and is too aggressive). I'll send this as a follow-on patch, and it will fall back to hardware_concurrency when the new getHostNumPhysicalCores returns -1 (when not supported for a given host system). I also added an interface to MemoryBuffer to force reading a file as a stream - this is required for /proc/cpuinfo which is a special file that looks like a normal file but appears to have 0 size. The existing readers of this file in Host.cpp are reading the first 1024 or so bytes from it, because the necessary info is near the top. But for the new functionality we need to be able to read the entire file. I can go back and change the other readers to use the new getFileAsStream as a follow-on patch since it seems much more robust. Added a unittest. Reviewers: mehdi_amini Subscribers: beanz, mgorny, llvm-commits, modocache Differential Revision: https://reviews.llvm.org/D25564 llvm-svn: 284138
* Truncate long names in type recordsReid Kleckner2016-10-132-18/+29
| | | | | | | | | In the MS ABI, the frontend is supposed to MD5 such pathologically long names. LLVM should still defend itself from long names, though. Fixes part of PR29098. llvm-svn: 284136
* [X86][AVX512] Fix sext v32i1 -> v32i8 lowering.Igor Breger2016-10-131-1/+1
| | | | | | | | Fix PR30600. Differential Revision: https://reviews.llvm.org/D25554 llvm-svn: 284134
* [libFuzzer] reapply r283946: refactoring to speed things up, NFC. Now with a ↵Kostya Serebryany2016-10-132-36/+23
| | | | | | fix for gcc build llvm-svn: 284132
* Fix for PR30687. Avoid dereferencing MBB.end().Reid Kleckner2016-10-132-38/+31
| | | | | | | | | | | | | | | | | | | | We don't need to return a MachineInstr* from these stack probe insertion calls anyway. If we ever need to add it back, we can return an iterator instead. Based on a patch by David Kreitzer This bug is a consequence of r279314 | dexonsmith | 2016-08-19 13:40:12 -0700 (Fri, 19 Aug 2016) | 110 lines We hit the "Assertion `!NodePtr->isKnownSentinel()' failed" assertion, but only when inserting a stack probe call at the end of an MBB, which isn't necessarily a common situation. Differential Revision: https://reviews.llvm.org/D25566 llvm-svn: 284130
* Do not delete leading ../ in remove_dots.Eric Liu2016-10-131-6/+5
| | | | | | | | | | Reviewers: bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25561 llvm-svn: 284129
* [ARM]: Assign cost of scaling used in addressing mode for ARM coresJaved Absar2016-10-134-2/+29
| | | | | | | | | | | | | | | | | | | | | This patch assigns cost of the scaling used in addressing. On many ARM cores, a negated register offset takes longer than a non-negated register offset, in a register-offset addressing mode. For instance: LDR R0, [R1, R2 LSL #2] LDR R0, [R1, -R2 LSL #2] Above, (1) takes less cycles than (2). By assigning appropriate scaling factor cost, we enable the LLVM to make the right trade-offs in the optimization and code-selection phase. Differential Revision: http://reviews.llvm.org/D24857 Reviewers: jmolloy, rengolin llvm-svn: 284127
* [LV] Account for predicated stores in instruction costsMatthew Simpson2016-10-131-0/+6
| | | | | | | This patch ensures that we scale the estimated cost of predicated stores by block probability. This is a follow-on patch for r284123. llvm-svn: 284126
* [LV] Avoid rounding errors for predicated instruction costsMatthew Simpson2016-10-131-26/+29
| | | | | | | | | | | | This patch modifies the cost calculation of predicated instructions (div and rem) to avoid the accumulation of rounding errors due to multiple truncating integer divisions. The calculation for predicated stores will be addressed in a follow-on patch since we currently don't scale the cost of predicated stores by block probability. Differential Revision: https://reviews.llvm.org/D25333 llvm-svn: 284123
* [DAGCombiner] Add vector support to (mul (shl X, Y), Z) -> (shl (mul X, Z), ↵Simon Pilgrim2016-10-131-7/+6
| | | | | | Y) style combines llvm-svn: 284122
* AMDGPU: Assume spilling will occur at -O0Matt Arsenault2016-10-131-1/+5
| | | | | | | | Because everything live is spilled at the end of a block by fast regalloc, assume this will happen and avoid the copies of the resource descriptor. llvm-svn: 284119
* [DAGCombiner] Add vector support to C2-(A+C1) -> (C2-C1)-A foldingSimon Pilgrim2016-10-131-5/+5
| | | | llvm-svn: 284117
* AMDGPU: Fix truncate to bool warningsMatt Arsenault2016-10-131-5/+5
| | | | llvm-svn: 284116
* [mips] Add IAS support for dvp, evpSimon Dardis2016-10-134-4/+44
| | | | | | | | | | | | | These instructions were only defined for microMIPSR6 previously. Add definitions for MIPSR6, correct definitions for microMIPSR6, flag these instructions as having unmodelled side effects (they disable/enable virtual processors) and add missing disassember tests for microMIPSR6. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24291 llvm-svn: 284115
* [DAGCombiner] Add vector support to (sub -1, x) -> (xor x, -1) canonicalizationSimon Pilgrim2016-10-131-1/+12
| | | | | | Improves commutation potential llvm-svn: 284113
* [X86] Basic additions to support RegCall Calling Convention.Oren Ben Simhon2016-10-137-0/+227
| | | | | | | | | | The Register Calling Convention (RegCall) was introduced by Intel to optimize parameter transfer on function call. This calling convention ensures that as many values as possible are passed or returned in registers. This commit presents the basic additions to LLVM CodeGen in order to support RegCall in X86. Differential Revision: http://reviews.llvm.org/D25022 llvm-svn: 284108
* Silence unused warning in non-assert builds.Daniel Jasper2016-10-131-3/+3
| | | | llvm-svn: 284107
* [AVX-512] Teach shuffle lowering to recognize 512-bit zero extends.Craig Topper2016-10-131-2/+27
| | | | llvm-svn: 284105
* [X86] Simplify the lowering code for extracting and inserting subvectors.Craig Topper2016-10-131-24/+21
| | | | | | | We don't need to check if AVX is enabled. It's implied by the operation action being set to Custom. We don't need to check both the input and output type widths. We only need to check the type that's being inserted or extracted. The other type is known to be a legal type and we can assume its a different width. llvm-svn: 284102
* Memory-SSA: strengthen defClobbersUseOrDef interfaceSebastian Pop2016-10-131-19/+15
| | | | | | | As Danny pointed out, defClobbersUseOrDef should use MemoryLocOrCall to make sure fences are properly handled. llvm-svn: 284099
* commit back "GVN-hoist: fix store past load dependence analysis (PR30216, ↵Sebastian Pop2016-10-132-90/+109
| | | | | | | | | | PR30499)" This is with an extra change to avoid calling MemoryLocation::get() on a call instruction. Differential Revision: https://reviews.llvm.org/D25542 llvm-svn: 284098
* [AArch64][RegisterBankInfo] Provide alternative mappings for 64-bit loadQuentin Colombet2016-10-131-1/+30
| | | | | | | | This allows RegBankSelect in greedy mode to get rid some of the cross register bank copies when loads are involved in the chain of computation. llvm-svn: 284097
* Correct PrivateLinkage for COFFReid Kleckner2016-10-131-3/+3
| | | | | | | | | | | | | - Use storage class C_STAT for 'PrivateLinkage' The storage class for PrivateLinkage should equal to the Internal Linkage. - Set 'PrivateGlobalPrefix' from "L" to ".L" for MM_WinCOFF (includes x86_64) MM_WinCOFF has empty GlobalPrefix '\0' so PrivateGlobalPrefix "L" may conflict to the normal symbol name starting with 'L'. Based on a patch by Han Sangjin! Manually updated test cases. llvm-svn: 284096
* [AArch64][RegisterBankInfo] Provide alternative mappings for G_BITCASTs.Quentin Colombet2016-10-131-8/+45
| | | | | | | Thanks to this patch, RegBankSelect is able to get rid of some register bank copies as demonstrated in the test case. llvm-svn: 284094
* Revert "GVN-hoist: fix store past load dependence analysis (PR30216, PR30499)"Reid Kleckner2016-10-132-104/+90
| | | | | | | | | | | This CL didn't actually address the test case in PR30499, and clang still crashes. Also revert dependent change "Memory-SSA cleanup of clobbers interface, NFC" Reverts r283965 and r283967. llvm-svn: 284093
* [AArch64][RegisterBankInfo] Describe cross regbank copies statically.Quentin Colombet2016-10-132-2/+68
| | | | | | NFC. llvm-svn: 284091
* [AArch64][RegisterBankInfo] Use static mapping for same bank G_BITCAST.Quentin Colombet2016-10-131-0/+8
| | | | | | NFC. llvm-svn: 284090
* [AArch64][MachineLegalizer] Mark more G_BITCAST as legal.Quentin Colombet2016-10-131-1/+8
| | | | | | | Basically any vector types that fits in a 32-bit register is also valid as far as copies are concerned. llvm-svn: 284089
* [AArch64][RegisterBankInfo] Bump the cost of vector loads.Quentin Colombet2016-10-131-0/+10
| | | | | | | This does not change anything yet, because we do not offer any alternative mapping. llvm-svn: 284088
* [AArch64][RegisterBankInfo] Use a proper cost for cross regbank G_BITCASTs.Quentin Colombet2016-10-131-2/+11
| | | | | | | This does not change anything yet, because we do not offer any alternative mapping. llvm-svn: 284087
* [AArch64][RegisterBankInfo] Provide more realistic copy costs.Quentin Colombet2016-10-131-1/+10
| | | | llvm-svn: 284086
* Handle lane masks in LivePhysRegs when adding live-insKrzysztof Parzyszek2016-10-121-5/+12
| | | | | | Differential Revision: https://reviews.llvm.org/D25533 llvm-svn: 284076
* GlobalISel: support G_TRUNC selection on AArch64.Tim Northover2016-10-121-0/+80
| | | | | | Ahmed's patch again. llvm-svn: 284075
* GlobalISel: support int <-> float conversions on AArch64.Tim Northover2016-10-121-1/+95
| | | | | | More of Ahmed's work. llvm-svn: 284074
* GlobalISel: select G_FCMP instructions on AArch64.Tim Northover2016-10-121-0/+116
| | | | | | Another of Ahmed's patches. llvm-svn: 284073
* GlobalISel: support selection of G_ICMP on AArch64.Tim Northover2016-10-121-0/+71
| | | | | | Patch from Ahmed Bougaca again. llvm-svn: 284072
* GlobalISel: select G_BRCOND instructions on AArch64.Tim Northover2016-10-121-0/+22
| | | | llvm-svn: 284071
* GlobalISel: mark G_BRCOND on s1 as legal.Tim Northover2016-10-121-3/+2
| | | | | | It's going to be a TBNZ (at -O0) anyway, so the high bits don't matter. llvm-svn: 284070
* [Coverage] Factor out logic to create FunctionRecords (NFC)Vedant Kumar2016-10-121-40/+45
| | | | llvm-svn: 284063
* Create llvm.addressofreturnaddress intrinsicAlbert Gutowski2016-10-127-2/+23
| | | | | | | | | | | | Summary: We need a new LLVM intrinsic to implement MS _AddressOfReturnAddress builtin on 64-bit Windows. Reviewers: majnemer, rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25293 llvm-svn: 284061
* Update _MSC_VER equality checks for msdiaNNN.dllReid Kleckner2016-10-121-10/+6
| | | | | | | | | Use inequality instead of equality to defend against minor version increases in _MSC_VER. An _MSC_VER value of 1901 should still use msdia140.dll, as described in this blog post: https://blogs.msdn.microsoft.com/vcblog/2016/10/05/visual-c-compiler-version/ llvm-svn: 284058
* Reapply "[LoopUnroll] Use the upper bound of the loop trip count to fullly ↵Haicheng Wu2016-10-123-46/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | unroll a loop" Reappy r284044 after revert in r284051. Krzysztof fixed the error in r284049. The original summary: This patch tries to fully unroll loops having break statement like this for (int i = 0; i < 8; i++) { if (a[i] == value) { found = true; break; } } GCC can fully unroll such loops, but currently LLVM cannot because LLVM only supports loops having exact constant trip counts. The upper bound of the trip count can be obtained from calling ScalarEvolution::getMaxBackedgeTakenCount(). Part of the patch is the refactoring work in SCEV to prevent duplicating code. The feature of using the upper bound is enabled under the same circumstance when runtime unrolling is enabled since both are used to unroll loops without knowing the exact constant trip count. llvm-svn: 284053
* [MIRParser] Parse lane masks for register live-insKrzysztof Parzyszek2016-10-124-24/+64
| | | | | | Differential Revision: https://reviews.llvm.org/D25530 llvm-svn: 284052
* Revert "[LoopUnroll] Use the upper bound of the loop trip count to fullly ↵Haicheng Wu2016-10-123-111/+46
| | | | | | | | unroll a loop" This reverts commit r284044. llvm-svn: 284051
* [LoopUnroll] Use the upper bound of the loop trip count to fullly unroll a loopHaicheng Wu2016-10-123-46/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch tries to fully unroll loops having break statement like this for (int i = 0; i < 8; i++) { if (a[i] == value) { found = true; break; } } GCC can fully unroll such loops, but currently LLVM cannot because LLVM only supports loops having exact constant trip counts. The upper bound of the trip count can be obtained from calling ScalarEvolution::getMaxBackedgeTakenCount(). Part of the patch is the refactoring work in SCEV to prevent duplicating code. The feature of using the upper bound is enabled under the same circumstance when runtime unrolling is enabled since both are used to unroll loops without knowing the exact constant trip count. Differential Revision: https://reviews.llvm.org/D24790 llvm-svn: 284044
* LTO: Use the correct mangler function in ↵Peter Collingbourne2016-10-121-2/+2
| | | | | | | | | | | | LTOCodeGenerator::applyScopeRestrictions(). We need to use the overload of Mangler::getNameWithPrefix that takes a GlobalValue in order to mangle in the stdcall stack byte count for Windows targets. Differential Revision: https://reviews.llvm.org/D25529 llvm-svn: 284040
* Do not remove implicit defs in BranchFolderKrzysztof Parzyszek2016-10-122-55/+0
| | | | | | | | | | | Branch folder removes implicit defs if they are the only non-branching instructions in a block, and the branches do not use the defined registers. The problem is that in some cases these implicit defs are required for the liveness information to be correct. Differential Revision: https://reviews.llvm.org/D25478 llvm-svn: 284036
* AMDGPU: Initial implementation of VGPR indexing modeMatt Arsenault2016-10-123-43/+194
| | | | | | | | | | | This is the most basic handling of the indirect access pseudos using GPR indexing mode. This currently only enables the mode for a single v_mov_b32 and then disables it. This is much more complicated to use than the movrel instructions, so a new optimization pass is probably needed to fold the access into the uses and keep the mode enabled for them. llvm-svn: 284031
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