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* Revert "[X86] Add a new LOW32_ADDR_ACCESS_RBP register class."Quentin Colombet2016-05-062-14/+1
| | | | | | | | This reverts commit r268796. I believe it breaks test/CodeGen/X86/asm-mismatched-types.ll with: Cannot emit physreg copy instruction llvm-svn: 268799
* [X86] Add a new LOW32_ADDR_ACCESS_RBP register class.Quentin Colombet2016-05-062-1/+14
| | | | | | | | ABIs like NaCl uses 32-bit addresses but have 64-bit frame. The new register class reflects those constraints when choosing a register class for a address access. llvm-svn: 268796
* [X86] Rename the X32_ADDR_ACCESS register class into LOW32_ADDR_ACCESS.Quentin Colombet2016-05-062-8/+12
| | | | | | | | This register class may be used by any ABIs that uses x86_64 ISA while using 32-bit addresses, not just in X32 cases. Make sure the name reflects that. llvm-svn: 268795
* Revert r268760, it caused PR27670.Nico Weber2016-05-061-53/+0
| | | | llvm-svn: 268794
* Add missing include.Zachary Turner2016-05-061-0/+1
| | | | llvm-svn: 268792
* Port DebugInfoPDB over to using llvm::Error.Zachary Turner2016-05-0617-224/+475
| | | | | | | Differential Revision: http://reviews.llvm.org/D19940 Reviewed By: rnk llvm-svn: 268791
* [RS4GC] Fix typo in commentSanjoy Das2016-05-061-1/+1
| | | | llvm-svn: 268790
* Change GenericBinaryError to no longer include a FileName, which is then notKevin Enderby2016-05-062-32/+30
| | | | | | | | | | | | | | | | | | part of the error message. As the caller is the one that needs to add the name of where the "object file" comes from to the error message as the object file could be in an archive, or coming from a slice of a Mach-O universal file or a buffer created by a JIT. In the cases of a Mach-O universal file the architecture name may or may not also need to be printed which is up to the tool code. For example if the tool code is only selecting the host architecture slice then that architecture name is never printed. This patch is the change to the libObject code and there will be follow on commits for changes to the code for each tool. llvm-svn: 268789
* [X86] Accept imp-defs of GR64 super-registers in FixupBW MOVrr.Ahmed Bougacha2016-05-061-5/+11
| | | | | | Testcase will follow shortly. llvm-svn: 268787
* [MSan] [X86] Fix vararg helper for fixed arguments in overflow area.Marcin Koscielnicki2016-05-061-0/+11
| | | | | | | | This fixes http://llvm.org/PR27646 on x86_64. Differential Revision: http://reviews.llvm.org/D19997 llvm-svn: 268783
* [AMDGPU][llvm-mc] Some refactoring of .td filesArtem Tamazov2016-05-062-27/+27
| | | | | | | | | Some custom Operands and AsmOperandClasses moved to proper place. No functional changes. Differential Revision: http://reviews.llvm.org/D20012 llvm-svn: 268780
* Refactor the Verifier so it can diagnose IR validation errors and debugAdrian Prantl2016-05-061-159/+195
| | | | | | | | | | | | | | | | | | | | | | | info metadata errors separately. (NFC) This patch refactors the Verifier so it can diagnose IR validation errors and debug info metadata errors separately. The motivation behind this change is that broken (or outdated) debug info can be "recovered" from by stripping the debug info. The problem I'm trying to solve with this sequence of patches is that historically we've done a really bad job at verifying debug info. We want to be able to make the verifier stricter without having to worry about breaking bitcode compatibility with existing producers. For example, we don't necessarily want IR produced by an older version of clang to be rejected by an LTO link just because of malformed debug info, and rather provide an option to strip it. Note that merely outdated (but well-formed) debug info would continue to be auto-upgraded in this scenario. http://reviews.llvm.org/D19986 rdar://problem/25818489 llvm-svn: 268778
* [Hexagon] Be careful about anti-dependencies with a call in packetizerKrzysztof Parzyszek2016-05-061-2/+24
| | | | | | | | | | | In a case like J2_callr <ga:@foo>, %R0<imp-use>, ... R0<def> = ... the anti-dependency on R0 cannot be ignored and the two instructions cannot be packetized together, since if they were, the assignment to R0 would take place before the call. llvm-svn: 268776
* [GVN] Handle unordered atomics in cross block FREPhilip Reames2016-05-061-5/+5
| | | | | | You'll note there are essentially no code changes here. Cross block FRE heavily reuses code from the block local FRE. All of the tricky parts were done as part of the previous patch and the refactoring that removed the original code duplication. llvm-svn: 268775
* SDAG: Don't leave dangling dead nodes after SelectCodeCommonJustin Bogner2016-05-061-1/+3
| | | | | | | Relying on the caller to clean up after we've replaced all uses of a node won't work when we've migrated to the `void Select(...)` API. llvm-svn: 268774
* [X86] Get rid of X32_NOREX_ADDR_ACCESS register class.Quentin Colombet2016-05-062-4/+1
| | | | | | | According to H.J. Lu <hjl.tools@gmail.com>, this register class is never used. llvm-svn: 268771
* [GVN] Do local FRE for unordered atomic loadsPhilip Reames2016-05-061-4/+21
| | | | | | | | | | This patch is the first in a small series teaching GVN to optimize unordered loads aggressively. This change just handles block local FRE because that's the simplest thing which lets me test MDA, and the AvailableValue pieces. Somewhat suprisingly, MDA appears fine and only a couple of small changes are needed in GVN. Once this is in, I'll tackle non-local FRE and PRE. The former looks like a natural extension of this, the later will require a couple of minor changes. Differential Revision: http://reviews.llvm.org/D19440 llvm-svn: 268770
* Tweak the ThinLTO pass pipelineMehdi Amini2016-05-061-17/+7
| | | | | | | | | | | | | | | | | | | | | Summary: The original ThinLTO pipeline was derived from some work I did tuning FullLTO on the test suite and SPEC. This patch reduces the amount of work done in the "linker phase" of the build, and extend the function simplifications passes performed during the "compile phase". This helps the build time by reducing the IR as much as possible during the compile phase and limiting the work to be performed during the "link phase", while keeping the performance "on par" with the existing pipeline. Reviewers: tejohnson Subscribers: llvm-commits, joker.eph Differential Revision: http://reviews.llvm.org/D19773 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 268769
* [SimplifyCFG] propagate branch metadata when creating select (retry r268550 ↵Sanjay Patel2016-05-061-1/+21
| | | | | | | | | | | | | | | | / r268751 with possible fix) Retrying r268550/r268751 which were reverted at r268577/r268765 due a memory sanitizer failure. I have not been able to reproduce that failure, but I've taken another guess at fixing the problem in this version of the patch and will watch for another failure. Original commit message: Unlike earlier similar fixes, we need to recalculate the branch weights in this case. Differential Revision: http://reviews.llvm.org/D19674 llvm-svn: 268767
* revert r268751 - caused same failures on msan botSanjay Patel2016-05-061-24/+9
| | | | llvm-svn: 268765
* [AMDGPU][llvm-mc] Add support for sendmsg(...) syntax.Artem Tamazov2016-05-065-27/+379
| | | | | | | | | | | | | | | | | | | Added support for sendmsg(MSG[, OP[, STREAM_ID]]) syntax in s_sendmsg and s_sendmsghalt instructions. The syntax matches the SP3 assembler/disassembler rules. That is why implicit inputs (like M0 and EXEC) are not printed to disassembly output anymore. sendmsg(...) allows only known message types and attributes, even if literals are used instead of symbolic names. However, raw literal (without "sendmsg") still can be used, and that allows for any 16-bit value. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19596 llvm-svn: 268762
* [X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr.Ahmed Bougacha2016-05-061-0/+47
| | | | | | | | Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268760
* [X86] Remove \brief in FixupBW. NFC.Ahmed Bougacha2016-05-061-13/+11
| | | | llvm-svn: 268754
* [X86] Simplify FixupBW sub_8bit_hi-related logic. NFC.Ahmed Bougacha2016-05-061-17/+12
| | | | | | | | | Instead of passing around sizes and asking for subregs, we can check the subreg indices we care about: sub_8bit_hi and sub_8bit. Differential Revision: http://reviews.llvm.org/D20006 llvm-svn: 268753
* [SimplifyCFG] propagate branch metadata when creating select (retry r268550 ↵Sanjay Patel2016-05-061-9/+24
| | | | | | | | | | | | | | | | with possible fix) Retrying r268550 which was reverted at r268577 due a memory sanitizer failure. I have not been able to reproduce that failure, but I've taken a guess at fixing the problem in this version of the patch and will watch for another failure. Original commit message: Unlike earlier similar fixes, we need to recalculate the branch weights in this case. Differential Revision: http://reviews.llvm.org/D19674 llvm-svn: 268751
* [AArch64] Combine callee-save and local stack SP adjustment instructions.Geoff Berry2016-05-063-80/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: If a function needs to allocate both callee-save stack memory and local stack memory, we currently decrement/increment the SP in two steps: first for the callee-save area, and then for the local stack area. This changes the code to allocate them both at once at the very beginning/end of the function. This has two benefits: 1) there is one fewer sub/add micro-op in the prologue/epilogue 2) the stack adjustment instructions act as a scheduling barrier, so moving them to the very beginning/end of the function increases post-RA scheduler's ability to move instructions (that only depend on argument registers) before any of the callee-save stores This change can cause an increase in instructions if the original local stack SP decrement could be folded into the first store to the stack. This occurs when the first local stack store is to stack offset 0. In this case we are trading off one more sub instruction for one fewer sub micro-op (along with benefits (2) and (3) above). Reviewers: t.p.northover Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18619 llvm-svn: 268746
* [AArch64] Decouple zero store promotion from narrow ld merge. NFC.Jun Bum Lim2016-05-061-28/+16
| | | | | | | | | | | | Summary: This change refactors to decouple the zero store promotion from the narrow ld merge and add a flag (enable-narrow-ld-merge=true) to control the narrow ld merge optimization. Reviewers: jmolloy, t.p.northover, mcrosier Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D19885 llvm-svn: 268744
* Revert "AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2."Nikolay Haustov2016-05-062-9/+5
| | | | | | | | This reverts commit 47486d52454d60cdf6becc0b2efe533c73794380. It broke calling OpenCL kernel from another kernel. llvm-svn: 268739
* [mips] Fix inconsistent .cprestore behaviour between direct object emission ↵Daniel Sanders2016-05-063-7/+26
| | | | | | | | | | | | | | | | | | | and assembling. Summary: Direct object emission has an initialization order problem where an InitMCObjectFile is called after MipsTargetELFStreamer determines whether PIC is enabled by default or not. There doesn't seem to be point that initializes all cases so split the responsibility between MipsTargetELFStreamer and MipsAsmPrinter. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19728 llvm-svn: 268737
* [SimplifyCFG] Prefer a simplification based on a dominating condition.Chad Rosier2016-05-061-20/+24
| | | | | | | Rather than merge two branches with a common destination. Differential Revision: http://reviews.llvm.org/D19743 llvm-svn: 268735
* [mips] Correct the ordering of HI/LO pairs in the relocation table.Daniel Sanders2016-05-062-191/+278
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: There seems to have been a misunderstanding as to the meaning of 'offset' in the rules laid down by our ABI. The previous code believed that 'offset' meant the offset within the section that the relocation is applied to. However, it should have meant the offset from the symbol used in the relocation expression. This patch adds two fields to ELFRelocationEntry and uses them to correct the order of relocations for MIPS. These fields contain: * The original symbol before shouldRelocateWithSymbol() is considered. This ensures that R_MIPS_GOT16 is able to correctly distinguish between local and external symbols, allowing us to tell whether %got() requires a matching %lo() or not (local symbols require one, external symbols don't). It also prevents confusing cases where the fuzzy matching rules cause things like %hi(foo)/%lo(foo+3) and %hi(bar)/%lo(bar+1) to swap their %lo()'s. * The original offset before shouldRelocateWithSymbol() is considered. The existing Addend field is always zero when the object uses in place addends (because it's already moved it to the encoding) but MIPS needs to use the original offset to ensure that the linker correctly calculates the carry-in bit for %hi() and %got(). IAS ensures that unmatchable %hi()/%got() relocations are placed at the end of the table to ensure that the linker rejects the table (we're unable to report such errors directly). The alternatives to this risk accidental matching against inappropriate relocations which may silently compute incorrect values due to an incorrect carry bit between the %lo() and %hi()/%got(). Reviewers: sdardis Subscribers: dsanders, sdardis, rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D19718 llvm-svn: 268733
* [mips][mips16] Use isUnconditionalBranch() in AnalyzeBranch() and constant ↵Daniel Sanders2016-05-062-14/+4
| | | | | | | | | | | | | | | | island pass. Summary: This stops it misidentifying unconditional branches as conditional branches which fixes a -verify-machineinstrs error about exiting a function via fall through. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19864 llvm-svn: 268731
* [mips][fastisel] Conditional moves do not have implicit operands.Daniel Sanders2016-05-061-5/+4
| | | | | | | | | | Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19862 llvm-svn: 268730
* [TableGen] AsmMatcher: support for default values for optional operandsSam Kolton2016-05-064-106/+118
| | | | | | | | | | | | | | Summary: This change allows to specify "DefaultMethod" for optional operand (IsOptional = 1) in AsmOperandClass that return default value for operand. This is used in convertToMCInst to set default values in MCInst. Previously if you wanted to set default value for operand you had to create custom converter method. With this change it is possible to use standard converters even when optional operands presented. Reviewers: tstellarAMD, ab, craig.topper Subscribers: jyknight, dsanders, arsenm, nhaustov, llvm-commits Differential Revision: http://reviews.llvm.org/D18242 llvm-svn: 268726
* Fix whitespace and line wrapping. NFC.Ryan Govostes2016-05-061-3/+4
| | | | llvm-svn: 268725
* [asan] add option to set shadow mapping offsetRyan Govostes2016-05-061-2/+9
| | | | | | | | | | Allowing overriding the default ASAN shadow mapping offset with the -asan-shadow-offset option, and allow zero to be specified for both offset and scale. Patch by Aaron Carroll <aaronc@apple.com>. llvm-svn: 268724
* [AVR] Add a majority of the backend codeDylan McKay2016-05-0613-1/+1483
| | | | | | | | | | | | Summary: This adds the majority of the AVR backend. Reviewers: hfinkel, dsanders, vkalintiris, arsenm Subscribers: dylanmckay Differential Revision: http://reviews.llvm.org/D17906 llvm-svn: 268722
* AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2.Nikolay Haustov2016-05-062-5/+9
| | | | | | | | | | | | | | | | | Summary: Check calling convention in AMDGPUMachineFunction::isKernel This will be used for AMDGPU_HSA_KERNEL symbol type in output ELF. Also, in the future unused non-kernels may be optimized. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D19917 llvm-svn: 268719
* AMDGPU/SI: Add amdgpu_kernel calling convention. Part 1.Nikolay Haustov2016-05-064-0/+5
| | | | | | | | | | | | | | | | | Summary: This will be used for AMDGPU_HSA_KERNEL symbol type in output ELF. Also, in the future unused non-kernels may be optimized. For now, also accept SPIR_KERNEL for HCC frontend. Also, add bitcode compatibility tests for missing calling conventions except AVR_BUILTIN which doesn't have parse code. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, joker.eph, llvm-commits llvm-svn: 268717
* ThinLTO: fix assertion and refactor check for hidden use from inline ASM in ↵Mehdi Amini2016-05-062-54/+49
| | | | | | | | | | | a helper function This test was crashing, and currently it breaks bootstrapping clang with debuginfo Differential Revision: http://reviews.llvm.org/D20008 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 268715
* [mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructionsZlatko Buljan2016-05-065-20/+52
| | | | | | Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
* [PM] port IR based PGO prof-gen pass to new pass managerXinliang David Li2016-05-065-11/+35
| | | | llvm-svn: 268710
* BitcodeWriter: Simplify. NFC.Peter Collingbourne2016-05-061-4/+2
| | | | llvm-svn: 268707
* [EarlyCSE] Rename a variable for clarity [NFC]Philip Reames2016-05-061-8/+8
| | | | llvm-svn: 268701
* [CodeGen] Round [SU]INT_TO_FP result when promoting from f16.Ahmed Bougacha2016-05-061-1/+6
| | | | | | | | | | | | If we don't, values that aren't precisely representable in f16 could be used as-is in a promoted f32 operation, which would produce incorrect results. AArch64 had the correct behavior; add a focused test. Fixes http://llvm.org/PR26871 llvm-svn: 268700
* Make StringTableBuilder to cache hash values.Rui Ueyama2016-05-061-4/+4
| | | | | | | | | | | | | | This change seems to speed up LLD a bit if it has a lot of mergeable sections. The number is below. It's not too bad for a small patch. Time to link Clang (debug build): w/o patch 6.3696 seconds w/patch 6.2746 seconds (-1.5%) Differential Revision: http://reviews.llvm.org/D19933 llvm-svn: 268698
* Object: Fix two -Wpessimizing-move warnings after r268694Justin Bogner2016-05-051-5/+4
| | | | llvm-svn: 268697
* Fix window bots failures due to r268694 - Cleanup and refactor of ↵Kevin Enderby2016-05-051-1/+1
| | | | | | malformedError() in lib/Object/MachOObjectFile.cpp . llvm-svn: 268696
* [LAA] Fix confusing debug messageAdam Nemet2016-05-051-1/+1
| | | | | | | | This message used to be correct, when all we cared about was whether the dependence was safe (i.e. NoDep) or unsafe. With the current more precise characterization, this is a forward dep. llvm-svn: 268695
* Cleanup and refactor of malformedError() in lib/Object/MachOObjectFile.cpp .Kevin Enderby2016-05-051-71/+41
| | | | | | No functional change. llvm-svn: 268694
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