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* LTO: Apply global DCE to ThinLTO modules at LTO opt level 0.Peter Collingbourne2017-11-012-31/+42
| | | | | | | | | | | | | | | | | | | | | | | | | This is necessary because DCE is applied to full LTO modules. Without this change, a reference from a dead ThinLTO global to a dead full LTO global will result in an undefined reference at link time. This problem is only observable when --gc-sections is disabled, or when targeting COFF, as the COFF port of lld requires all symbols to have a definition even if all references are dead (this is consistent with link.exe). This change also adds an EliminateAvailableExternally pass at -O0. This is necessary to handle the situation on Windows where a non-prevailing copy of a linkonce_odr function has an SEH filter function; any such filters must be DCE'd because they will contain a call to the llvm.localrecover intrinsic, passing as an argument the address of the function that the filter belongs to, and llvm.localrecover requires this function to be defined locally. Fixes PR35142. Differential Revision: https://reviews.llvm.org/D39484 llvm-svn: 317108
* loop-rotate: avoid duplicating dbg.value intrinsics in the entry block.Adrian Prantl2017-11-011-0/+24
| | | | | | This fixes the second half of PR35113. llvm-svn: 317106
* loop-rotate: eliminate duplicate debug intrinsics after splicing.Adrian Prantl2017-11-011-1/+23
| | | | | | Fixes part of PR35113. llvm-svn: 317105
* [X86] Add 64-bit int to float/double conversion with AVX to ↵Craig Topper2017-11-011-3/+4
| | | | | | | | | | | | | | | | | | | | | X86FastISel::X86SelectSIToFP Summary: [X86] Teach fast isel to handle i64 sitofp with AVX. For some reason we only handled i32 sitofp with AVX. But with SSE only we support i64 so we should do the same with AVX. Also add i686 command lines for the 32-bit tests. 64-bit tests are in a separate file to avoid a fast-isel abort failure in 32-bit mode. Reviewers: RKSimon, zvi Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39450 llvm-svn: 317102
* Update VCVTx, VMOVNTPx and VROUNDYPx instructions scheduling on btver2.Andrew V. Tischenko2017-11-011-0/+39
| | | | | | Differential Revision: https://reviews.llvm.org/D39059 llvm-svn: 317101
* Correct dwarf unwind information in function epilogue for X86Petar Jovanovic2017-11-0110-14/+474
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: - CFI instructions do not affect code generation - Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Changed CFI instructions so that they: - are duplicable - are not counted as instructions when tail duplicating or tail merging - can be compared as equal Added CFIInstrInserter pass: - analyzes each basic block to determine cfa offset and register valid at its entry and exit - verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors - inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D35844 llvm-svn: 317100
* [X86][SSE] Begun generalizing truncateVectorWithPACKSS to work with ↵Simon Pilgrim2017-11-011-11/+14
| | | | | | | | PACKSS/PACKUS functions Renamed to truncateVectorWithPACK llvm-svn: 317098
* [BranchProbabilityInfo] Handle irreducible loops.Geoff Berry2017-11-011-10/+80
| | | | | | | | | | | | | | | Summary: Compute the strongly connected components of the CFG and fall back to use these for blocks that are in loops that are not detected by LoopInfo when computing loop back-edge and exit branch probabilities. Reviewers: dexonsmith, davidxl Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D39385 llvm-svn: 317094
* Revert r313618 "[ARM] Use ADDCARRY / SUBCARRY"Roger Ferrer Ibanez2017-11-012-168/+20
| | | | | | That change causes PR35103, so reverting until I figure it out. llvm-svn: 317092
* Fix warnings discovered by rL317076. [-Wunused-private-field]NAKAMURA Takumi2017-11-015-8/+3
| | | | llvm-svn: 317091
* Suppress a warning discovered by rL317076. [-Wunused-private-field]NAKAMURA Takumi2017-11-011-0/+1
| | | | llvm-svn: 317090
* Revert rL311205 "[IRCE] Fix buggy behavior in Clamp"Max Kazantsev2017-11-011-2/+1
| | | | | | | | | | | | | This patch reverts rL311205 that was initially a wrong fix. The real problem was in intersection of signed and unsigned ranges (see rL316552), and the patch being reverted masked the problem instead of fixing it. By now, the test against which rL311205 was made works OK even without this code. This revert patch also contains a test case that demonstrates incorrect behavior caused by rL311205: it is caused by incorrect choise of signed max instead of unsigned. llvm-svn: 317088
* [SelectionDAG] computeKnownBits - use ashrInPlace on known bits of ISD::SRA ↵Simon Pilgrim2017-11-011-11/+3
| | | | | | input. NFCI. llvm-svn: 317087
* [X86][SSE] Truncate with PACKSS any input with sufficient sign-bitsSimon Pilgrim2017-11-011-9/+12
| | | | | | | | | | So far we've only been using PACKSS truncations with 'all-bits or zero-bits' patterns (vector comparison results etc.). When really we can safely use it for any case as long as the number of sign bits reach down to the last 16-bits (or 8-bits if we're truncating to bytes). The next steps after this is add the equivalent support for PACKUS and to support packing to sub-128 bit vectors for truncating stores etc. Differential Revision: https://reviews.llvm.org/D39476 llvm-svn: 317086
* [CodeExtractor] Fix iterator invalidation in findOrCreateBlockForHoisting.Florian Hahn2017-11-011-1/+3
| | | | | | | | | | | | | | | | | | | Summary: By replacing branches to CommonExitBlock, we remove the node from CommonExitBlock's predecessors, invalidating the iterator. The problem is exposed when the common exit block has multiple predecessors and needs to sink lifetime info. The modification in the test case trigger the issue. Reviewers: davidxl, davide, wmi Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39112 llvm-svn: 317084
* Fix APFloat mod signSerguei Katkov2017-11-011-0/+3
| | | | | | | | | | | | fmod specification requires the sign of the remainder is the same as numerator in case remainder is zero. Reviewers: gottesmm, scanon, arsenm, davide, craig.topper Reviewed By: scanon Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D39225 llvm-svn: 317081
* [X86] Add more type qualifiers to INSERT_SUBREG operations in rotate ↵Craig Topper2017-11-011-8/+8
| | | | | | | | | | patterns so they don't get created with a v64i8 type. Not sure why tablegen didn't error on this. Fixes PR35158. llvm-svn: 317079
* [DAGCombiner] Fix typos in comments. NFCCraig Topper2017-11-011-2/+2
| | | | llvm-svn: 317072
* [X86] Add AVX512 support to X86FastISel::fastMaterializeFloatZero.Craig Topper2017-11-011-4/+5
| | | | llvm-svn: 317059
* [AMDGPU] Clean up symbols in the global namespace.Benjamin Kramer2017-10-314-57/+41
| | | | llvm-svn: 317051
* [SimplifyIndVar] Inline makIVComparisonInvariant to eleminate code ↵Philip Reames2017-10-311-51/+29
| | | | | | | | duplication [NFC] This formulation might be slightly slower since I eagerly compute the cheap replacements. If anyone sees this having a compile time impact, let me know and I'll use lazy population instead. llvm-svn: 317048
* Object: Move some code from ELF.h into ELF.cpp.Peter Collingbourne2017-10-311-0/+263
| | | | | | Differential Revision: https://reviews.llvm.org/D39271 llvm-svn: 317046
* [codeview] Merge file checksum entries for DIFiles with the same absolute pathReid Kleckner2017-10-312-4/+5
| | | | | | | | Change the map key from DIFile* to the absolute path string. Computing the absolute path isn't expensive because we already have a map that caches the full path keyed on DIFile*. llvm-svn: 317041
* AMDGPU: Select s_buffer_load_dword with a non-constant SGPR offsetMarek Olsak2017-10-314-17/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Apps that benefit: - alien isolation - bioshock infinite - civilization: beyond earth - company of heroes 2 - dirt showdown - dota 2 - F1 2015 - grid autosport - hitman - legend of grimrock - serious sam 3: bfe - shadow warrior - talos principle - total war: warhammer - UE4 demos: effects cave, elemental, sun temple Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D38914 llvm-svn: 317038
* loop-rotate: simplify code by using llvm::findDbgValues(). (NFC)Adrian Prantl2017-10-311-31/+23
| | | | llvm-svn: 317037
* Revert "[DWARF] Now that Optional is standard layout, put it into an union ↵Benjamin Kramer2017-10-311-2/+2
| | | | | | | | instead of splatting it." GCC doesn't like it. This reverts commit r317028. llvm-svn: 317030
* [DWARF] Now that Optional is standard layout, put it into an union instead ↵Benjamin Kramer2017-10-311-2/+2
| | | | | | | | of splatting it. No functionality change intended. llvm-svn: 317028
* [coro] Make Spill a proper struct instead of deriving from pair.Benjamin Kramer2017-10-311-12/+10
| | | | | | No functionality change. llvm-svn: 317027
* [SimplifyCFG] Use a more generic name for the selects created by ↵Craig Topper2017-10-311-2/+2
| | | | | | | | | | | | SpeculativelyExecuteBB to prevent long names from being created Currently the selects are created with the names of their inputs concatenated together. It's possible to get cases that chain these selects together resulting in long names due to multiple levels of concatenation. Our internal branch of llvm managed to generate names over 100000 characters in length on a particular test due to an extreme compounding of the names. This patch changes the name to a generic name that is not dependent on its inputs. Differential Revision: https://reviews.llvm.org/D39440 llvm-svn: 317024
* [IndVarSimplify] Extract wrapper around SE-.isLoopInvariantPredicate [NFC]Philip Reames2017-10-311-17/+33
| | | | | | This an intermediate state, the next patch will re-inline the markLoopInvariantPredicate function to reduce code duplication. llvm-svn: 317016
* [Support] Make the default chunk size of raw_fd_ostream to 1 GiB.Rui Ueyama2017-10-311-11/+12
| | | | | | | | | | | | | | | | | | Previously, we call write(2) for each 32767 byte chunk. That is not efficient because Linux can handle much larger write requests. This patch changes the chunk size on Linux to 1 GiB. This patch also changes the default chunks size to SSIZE_MAX. I think that doesn't in practice change this function's behavior on any operating system because SSIZE_MAX on 64-bit machine is unrealistically large, and writing 2 GiB (SSIZE_MAX on 32-bit) on a 32-bit machine by a single call of write(2) is also unrealistic, as the userspace is usually limited to 2 GiB. That said, it is in general a good thing to do because a write larger than SSIZE_MAX is implementation-defined in POSIX. Differential Revision: https://reviews.llvm.org/D39444 llvm-svn: 317015
* [IndVarSimplify] Simplify code using a dictionaryPhilip Reames2017-10-311-16/+8
| | | | | | Possibly very slightly slower, but this code is not performance critical and the readability benefit alone is huge. llvm-svn: 317012
* [X86][AsmParser] Treat '%' as the modulo operator under Intel syntaxReid Kleckner2017-10-311-0/+1
| | | | | | | | | | It can't be a register prefix, anyway. This is consistent with the masm docs on MSDN: https://msdn.microsoft.com/en-us/library/t4ax90d2.aspx This is a straight-forward extension of our support for "MOD" implemented in https://reviews.llvm.org/D33876 / r306425 llvm-svn: 317011
* LTOModule::isBitcodeFile() shouldn't assert when returning false.Nico Weber2017-10-311-4/+16
| | | | | | | | | | | | Fixes a bunch of assert-on-invalid-bitcode regressions after 315483. Expected<> calls assertIsChecked() in its dtor, and operator bool() only calls setChecked() if there's no error. So for functions that don't return an error itself, the Expected<> version needs explicit code to disarm the error that the ErrorOr<> code didn't need. https://reviews.llvm.org/D39437 llvm-svn: 317010
* [asan] Upgrade private linkage globals to internal linkage on COFFReid Kleckner2017-10-311-2/+7
| | | | | | | COFF comdats require symbol table entries, which means the comdat leader cannot have private linkage. llvm-svn: 317009
* [X86][SSE] Add VSRLI/VSRAI/VSLLI demanded elts support to ↵Simon Pilgrim2017-10-311-5/+6
| | | | | | | | computeKnownBits/ComputeNumSignBits Mainly a perf improvements as most combines will have occurred before we lower to these instructions llvm-svn: 317005
* [LoopVectorize] Replace manual VPlan memory management with unique_ptr.Benjamin Kramer2017-10-311-26/+10
| | | | | | No functionality change intended. llvm-svn: 317003
* [InstCombine] Simplify selects that test cmpxchg instructionsMatthew Simpson2017-10-311-0/+76
| | | | | | | | | | If a select instruction tests the returned flag of a cmpxchg instruction and selects between the returned value of the cmpxchg instruction and its compare operand, the result of the select will always be equal to its false value. Differential Revision: https://reviews.llvm.org/D39383 llvm-svn: 316994
* [LoopUnroll] Clean up remarks for unroll remainderDavid Green2017-10-312-31/+35
| | | | | | | | | | | | | | | | The optimisation remarks for loop unrolling with an unrolled remainder looks something like: test.c:7:18: remark: completely unrolled loop with 3 iterations [-Rpass=loop-unroll] C[i] += A[i*N+j]; ^ test.c:6:9: remark: unrolled loop by a factor of 4 with run-time trip count [-Rpass=loop-unroll] for(int j = 0; j < N; j++) ^ This removes the first of the two messages. Differential revision: https://reviews.llvm.org/D38725 llvm-svn: 316986
* [AVX512] Adding new patterns for extract_subvector of vXi1Michael Zuckerman2017-10-311-14/+42
| | | | | | | | | | | | | | | | | extract subvector of vXi1 from vYi1 is poorly supported by LLVM and most of the time end with an assertion. This patch fixes this issue by adding new patterns to the TD file. Reviewers: 1. guyblank 2. igorb 3. zvi 4. ayman 5. craig.topper Differential Revision: https://reviews.llvm.org/D39292 Change-Id: Ideb4d7e946c8d40cfce2920891f2d89fe64c58f8 llvm-svn: 316981
* [CGP] Fix the detection of trivial case for addressing modeSerguei Katkov2017-10-311-10/+9
| | | | | | | The address can be presented as a bitcast of baseReg. In this case it is still trivial but OriginalValue != baseReg. llvm-svn: 316980
* [IRCE][NFC] Rename fields of InductiveRangeCheckMax Kazantsev2017-10-311-23/+23
| | | | | | | | | | Rename `Offset`, `Scale`, `Length` into `Begin`, `Step`, `End` respectively to make naming of similar entities for Ranges and Range Checks more consistent. Differential Revision: https://reviews.llvm.org/D39414 llvm-svn: 316979
* [X86] Make AVX512_512_SET0 XMM16-31 lower to 128-bit XOR when AVX512VL is ↵Craig Topper2017-10-311-13/+2
| | | | | | | | | | enabled. Use 128-bit VLX instruction when VLX is enabled. Unfortunately, this weakens our ability to do domain fixing when AVX512DQ is not enabled, but it is consistent with our 256-bit behavior. Maybe we should add custom handling to domain fixing to allow EVEX integer XOR/AND/OR/ANDN to switch to VEX encoded fp instructions if the high registers aren't being used? llvm-svn: 316978
* [NFC] Get rid of variables used in assert onlyMax Kazantsev2017-10-311-6/+6
| | | | llvm-svn: 316977
* [IndVarSimplify] Simplify code using preheader assumptionPhilip Reames2017-10-311-44/+6
| | | | | | | | As noted in the nice block comment, the previous code didn't actually handle multi-entry loops correctly, it just assumed SCEV didn't analyze such loops. Given SCEV has comments to the contrary, that seems a bit suspect. More importantly, the pass actually requires loopsimplify form which ensures a loop-preheader is available. Remove the excessive generaility and shorten the code greatly. Note that we do successfully analyze many multi-entry loops, but we do so by converting them to single entry loops. See the added test case. llvm-svn: 316976
* Reapply "[GVN] Prevent LoadPRE from hoisting across instructions that don't ↵Max Kazantsev2017-10-311-0/+97
| | | | | | | | | | | | | | | | | | pass control flow to successors" This patch fixes the miscompile that happens when PRE hoists loads across guards and other instructions that don't always pass control flow to their successors. PRE is now prohibited to hoist across such instructions because there is no guarantee that the load standing after such instruction is still valid before such instruction. For example, a load from under a guard may be invalid before the guard in the following case: int array[LEN]; ... guard(0 <= index && index < LEN); use(array[index]); Differential Revision: https://reviews.llvm.org/D37460 llvm-svn: 316975
* [SimplifyIndVar] Extract out invariant expression handlingPhilip Reames2017-10-311-82/+107
| | | | | | | | Previously, the code returned early from the *function* when it couldn't find a free expansion, it should be returning from the *transform*. I don't have a test case, noticed this via inspection. As a follow up, I'm going to revisit the logic in the extract function. I think that essentially the whole helper routine can be replaced with SCEVExpander, but I wanted to do that in a series of separate commits. llvm-svn: 316974
* [X86] Clang-format some code. NFCCraig Topper2017-10-311-2/+8
| | | | llvm-svn: 316973
* Undo accidental commitPhilip Reames2017-10-312-245/+82
| | | | | | These files shouldn't have been submitted in 316967 llvm-svn: 316968
* [CGP] Fix crash on i96 bit multiplyPhilip Reames2017-10-303-83/+246
| | | | | | | | Issue found by llvm-isel-fuzzer on OSS fuzz, https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3725 If anyone actually cares about > 64 bit arithmetic, there's a lot more to do in this area. There's a bunch of obviously wrong code in the same function. I don't have the time to fix all of them and am just using this to understand what the workflow for fixing fuzzer cases might look like. llvm-svn: 316967
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