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* BuildSDIV and BuildUDIV only work for i32/i64, but they don't check thatChris Lattner2005-10-221-10/+20
| | | | | | | | the input is that type, this caused a failure on gs on X86 last night. Move the hard checks into Build[US]Div since that is where decisions like this should be made. llvm-svn: 23881
* Add g3 back to the mix and reorder to irritate them anal folk. Actually, it'sJim Laskey2005-10-221-9/+10
| | | | | | | to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
* 64-bit reg support should not be enabled by default, as support isn't complete.Chris Lattner2005-10-211-2/+2
| | | | llvm-svn: 23878
* add a case missing from the dag combiner that exposed the failure onChris Lattner2005-10-211-0/+3
| | | | | | 2005-10-21-longlonggtu.ll. llvm-svn: 23875
* Instead of aborting if not a case we can handle specially, break out andChris Lattner2005-10-212-55/+52
| | | | | | | | let the generic code handle it. This fixes CodeGen/Generic/2005-10-21-longlonggtu.ll on ppc. also, reindent this code llvm-svn: 23874
* Plugin new subtarget backend into the build.Jim Laskey2005-10-215-80/+42
| | | | llvm-svn: 23870
* silence a release mode warningChris Lattner2005-10-211-1/+1
| | | | llvm-svn: 23868
* Make the coallescer a bit smarter, allowing it to join more live ranges.Chris Lattner2005-10-211-30/+85
| | | | | | | | | | | | For example, we can now join things like [0-30:0)[31-40:1)[52-59:2) with [40:60:0) if the 52-59 range is defined by a copy from the 40-60 range. The resultant range ends up being [0-30:0)[31-60:1). This fires a lot through-out the test suite (e.g. shrinking bc from 19492 -> 18509 machineinstrs) though most gains are smaller (e.g. about 50 copies eliminated from crafty). llvm-svn: 23866
* Fix LiveInterval::getOverlapingRanges to take things in the right orderChris Lattner2005-10-211-3/+3
| | | | | | | | | | (an unused method). Fix the merger so that it can merge ranges like this [10:12)[16:40) with [12:38) into [10:40) instead of bogus ranges. This sort of input will be possible for the merger coming shortly llvm-svn: 23865
* Match rotate. This does actually match the rotates in an rc5 cipher, but INate Begeman2005-10-211-0/+3
| | | | | | haven't seen it fire on our testsuite. llvm-svn: 23863
* My previous patch was too conservative. Reject FP and void types, but doChris Lattner2005-10-211-1/+2
| | | | | | allow pointer types. llvm-svn: 23859
* Don't generate operations that aren't yet supportedNate Begeman2005-10-211-1/+4
| | | | llvm-svn: 23858
* Kill some now-dead code.Nate Begeman2005-10-211-159/+0
| | | | llvm-svn: 23857
* Fix a typo in the dag combiner, so that this can work on i64 targetsNate Begeman2005-10-211-3/+2
| | | | llvm-svn: 23856
* byte zap not immediate goodnessAndrew Lenharth2005-10-211-12/+47
| | | | llvm-svn: 23855
* Invert the TargetLowering flag that controls divide by consant expansion.Nate Begeman2005-10-215-66/+45
| | | | | | | | | | Add a new flag to TargetLowering indicating if the target has really cheap signed division by powers of two, make ppc use it. This will probably go away in the future. Implement some more ISD::SDIV folds in the dag combiner Remove now dead code in the x86 backend. llvm-svn: 23853
* Inst cleanup. As a bonus, operands are in the correct order for cmovs. ↵Andrew Lenharth2005-10-202-47/+33
| | | | | | Expect new stuff to pass in the JIT tonight llvm-svn: 23852
* Use a literal to define ineg instead of immzeroChris Lattner2005-10-201-2/+1
| | | | llvm-svn: 23851
* Fix a conditional so we don't access past the end of the range. Thanks toChris Lattner2005-10-201-6/+4
| | | | | | Andrew for bringing this to my attn. llvm-svn: 23850
* added a few 1 operand form stuff. Seems to break regalloc on alpha. sighAndrew Lenharth2005-10-203-13/+33
| | | | llvm-svn: 23849
* add cttz and ctpopAndrew Lenharth2005-10-201-0/+2
| | | | llvm-svn: 23848
* Fix a couple bugs in the const div stuff where we'd generate MULHS/MULHUNate Begeman2005-10-201-3/+4
| | | | | | | for types that aren't legal, and fail a divisor is less than zero comparison, which would cause us to drop a subtract. llvm-svn: 23846
* don't use llabs with apparently VC++ doesn't haveChris Lattner2005-10-201-1/+1
| | | | llvm-svn: 23845
* Fix order of eval problem from when I refactored this into a function.Chris Lattner2005-10-201-3/+2
| | | | llvm-svn: 23844
* Sounds good, finish the intop conversion.Andrew Lenharth2005-10-201-27/+20
| | | | llvm-svn: 23843
* Add some more patterns for i64 on ppcNate Begeman2005-10-201-6/+12
| | | | llvm-svn: 23842
* add a new method, play around with some code.Chris Lattner2005-10-201-10/+56
| | | | | | | | Fix a *bug* in the extendIntervalEndTo method. In particular, if adding [2:10) to an interval containing [0:2),[10:30), we produced [0:10),[10,30). Which is not the most smart thing to do. Now produce [0:30). llvm-svn: 23841
* Refactor some code, pulling it out into a function. No functionality change.Chris Lattner2005-10-201-15/+26
| | | | llvm-svn: 23839
* Do NOT touch FP ops with LSR. This fixes a testcase Nate sent me from anChris Lattner2005-10-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | inner loop like this: LBB_RateConvertMono8AltiVec_2: ; no_exit lis r2, ha16(.CPI_RateConvertMono8AltiVec_0) lfs f3, lo16(.CPI_RateConvertMono8AltiVec_0)(r2) fmr f3, f3 fadd f0, f2, f0 fadd f3, f0, f3 fcmpu cr0, f3, f1 bge cr0, LBB_RateConvertMono8AltiVec_2 ; no_exit to an inner loop like this: LBB_RateConvertMono8AltiVec_1: ; no_exit fsub f2, f2, f1 fcmpu cr0, f2, f1 fmr f0, f2 bge cr0, LBB_RateConvertMono8AltiVec_1 ; no_exit Doh! good catch! llvm-svn: 23838
* Add some pattern fragments to simplify the repetitive parts of the patternsChris Lattner2005-10-201-3/+22
| | | | | | | | for some common ops and use them for a few examples. Andrew, if you like this, feel free to convert the rest over, if you hate it, feel free to revert. llvm-svn: 23837
* simplify this a bit by using immediatesChris Lattner2005-10-201-24/+16
| | | | llvm-svn: 23836
* Move the target constant divide optimization up into the dag combiner, soNate Begeman2005-10-204-314/+265
| | | | | | | that the nodes can be folded with other nodes, and we can not duplicate code in every backend. Alpha will probably want this too. llvm-svn: 23835
* forgot this oneAndrew Lenharth2005-10-201-0/+265
| | | | llvm-svn: 23833
* ret 0; works, not much elseAndrew Lenharth2005-10-207-139/+226
| | | | | | | | still lots of uglyness. Maybe calls will come soon. Fixing the return value of things will be necessary to make alpha work. llvm-svn: 23832
* This fixes PR638:John Criswell2005-10-191-6/+6
| | | | | | Regression/CodeGen/Generic/2004-02-08-UnwindSupport.llx llvm-svn: 23831
* Added InstrSchedClass to each of the PowerPC Instructions.Jim Laskey2005-10-199-389/+427
| | | | | | | Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
* Write patterns for the various shl and srl patterns that don't involveNate Begeman2005-10-193-50/+71
| | | | | | doing something clever. llvm-svn: 23824
* Push processor descriptions to the top of target and add command line info.Jim Laskey2005-10-197-23/+80
| | | | llvm-svn: 23820
* now that tblgen is smarter, use integers directly. This should help Andrew tooChris Lattner2005-10-191-4/+1
| | | | llvm-svn: 23818
* teach ppc backend these are copiesChris Lattner2005-10-191-1/+2
| | | | llvm-svn: 23813
* Convert these cases to patternsChris Lattner2005-10-192-37/+11
| | | | llvm-svn: 23811
* Woo, it kinda works. We now generate this atrociously bad, but correct,Nate Begeman2005-10-192-23/+54
| | | | | | | | | | | | | | | | | | | | | | | code for long long foo(long long a, long long b) { return a + b; } _foo: or r2, r3, r3 or r3, r4, r4 or r4, r5, r5 or r5, r6, r6 rldicr r2, r2, 32, 31 rldicl r3, r3, 0, 32 rldicr r4, r4, 32, 31 rldicl r5, r5, 0, 32 or r2, r3, r2 or r3, r5, r4 add r4, r3, r2 rldicl r2, r4, 32, 32 or r4, r4, r4 or r3, r2, r2 blr llvm-svn: 23809
* apply some tblgen majik to simplify the X register definitionsChris Lattner2005-10-191-19/+19
| | | | llvm-svn: 23805
* Teach Legalize how to do something with EXTRACT_ELEMENT when the type ofNate Begeman2005-10-191-7/+30
| | | | | | the pair of elements is a legal type. llvm-svn: 23804
* Make a new reg class for 64 bit regs that aliases the 32 bit regs. ThisNate Begeman2005-10-193-9/+50
| | | | | | | | | | | will have to tide us over until we get real subreg support, but it prevents the PrologEpilogInserter from spilling 8 byte GPRs on a G4 processor. Add some initial support for TRUNCATE and ANY_EXTEND, but they don't currently work due to issues with ScheduleDAG. Something wll have to be figured out. llvm-svn: 23803
* Add the ability to lower return instructions to TargetLowering. ThisNate Begeman2005-10-184-7/+39
| | | | | | | allows us to lower legal return types to something else, to meet ABI requirements (such as that i64 be returned in two i32 regs on Darwin/ppc). llvm-svn: 23802
* Fix Generic/2005-10-18-ZeroSizeStackObject.ll by not requesting a zeroChris Lattner2005-10-181-0/+1
| | | | | | sized stack object if either the array size or the type size is zero. llvm-svn: 23801
* remove hackChris Lattner2005-10-181-3/+1
| | | | llvm-svn: 23797
* Simple edits; remove unimplimented cases and clarify long haul SLU cases.Jim Laskey2005-10-184-61/+3
| | | | llvm-svn: 23788
* Fix the JIT encoding of LWA, LD, STD, and STDU.Chris Lattner2005-10-183-4/+20
| | | | llvm-svn: 23787
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