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* Revert "Data Dependence Graph Basics"Bardia Mahjour2019-09-175-386/+0
| | | | | | This reverts commit c98ec60993a7aa65073692b62f6d728b36e68ccd, which broke the sphinx-docs build. llvm-svn: 372168
* NVPTXAsmPrinter - Don't dereference a dyn_cast result. NFCI.Simon Pilgrim2019-09-171-1/+1
| | | | llvm-svn: 372166
* WasmEmitter - Don't dereference a dyn_cast result. NFCI.Simon Pilgrim2019-09-171-1/+1
| | | | llvm-svn: 372165
* [AArch64][GlobalISel][NFC] Refactor tail call lowering codeJessica Paquette2019-09-172-31/+74
| | | | | | | | | | When you begin implementing -tailcallopt, this gets somewhat hairy. Refactor the call lowering code so that the tail call lowering stuff gets its own function. Differential Revision: https://reviews.llvm.org/D67577 llvm-svn: 372164
* Data Dependence Graph BasicsBardia Mahjour2019-09-175-0/+386
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the first patch in a series of patches that will implement data dependence graph in LLVM. Many of the ideas used in this implementation are based on the following paper: D. J. Kuck, R. H. Kuhn, D. A. Padua, B. Leasure, and M. Wolfe (1981). DEPENDENCE GRAPHS AND COMPILER OPTIMIZATIONS. This patch contains support for a basic DDGs containing only atomic nodes (one node for each instruction). The edges are two fold: def-use edges and memory-dependence edges. The implementation takes a list of basic-blocks and only considers dependencies among instructions in those basic blocks. Any dependencies coming into or going out of instructions that do not belong to those basic blocks are ignored. The algorithm for building the graph involves the following steps in order: 1. For each instruction in the range of basic blocks to consider, create an atomic node in the resulting graph. 2. For each node in the graph establish def-use edges to/from other nodes in the graph. 3. For each pair of nodes containing memory instruction(s) create memory edges between them. This part of the algorithm goes through the instructions in lexicographical order and creates edges in reverse order if the sink of the dependence occurs before the source of it. Authored By: bmahjour Reviewer: Meinersbur, fhahn, myhsu, xtian, dmgreen, kbarton, jdoerfert Reviewed By: Meinersbur, fhahn, myhsu Subscribers: ychen, arphaman, simoll, a.elovikov, mgorny, hiraditya, jfb, wuzish, llvm-commits, jsji, Whitney, etiotto Tag: #llvm Differential Revision: https://reviews.llvm.org/D65350 llvm-svn: 372162
* [X86] Use APInt::operator<<= and APInt::lshrInPlace. NFCCraig Topper2019-09-171-4/+4
| | | | llvm-svn: 372159
* [SimplifyDemandedBits] Use APInt::intersects to instead of ANDing and ↵Craig Topper2019-09-171-2/+3
| | | | | | comparing to 0 separately. NFC llvm-svn: 372158
* [X86] Simplify b2b KSHIFTL+KSHIFTR using demanded elts.Craig Topper2019-09-171-13/+66
| | | | llvm-svn: 372155
* [X86] Call SimplifyDemandedVectorElts on KSHIFTL/KSHIFTR nodes during DAG ↵Craig Topper2019-09-171-0/+16
| | | | | | combine. llvm-svn: 372154
* [X86] Simplify some code in LowerBUILD_VECTORvXi1. NFCICraig Topper2019-09-171-15/+8
| | | | | | | | | | | | | The case were Immediate is 0 and HasConstElts is true should never happen since that would mean the constant elts were all zero. But we check for all zero build vector earlier. So just use HasConstElts and blindly take Immediate without checking if its 0. Move the code that bitcasts and extract the immediate into the the HasConstElts case since the other code just creates an undef with the right type. No casting needed. llvm-svn: 372153
* [AMDGPU] Added MI bit IsDOTStanislav Mekhanoshin2019-09-176-2/+22
| | | | | | | | NFC, needed for future commit. Differential Revision: https://reviews.llvm.org/D67669 llvm-svn: 372151
* GSYM: Add the llvm::gsym::Header header class with testsGreg Clayton2019-09-172-0/+112
| | | | | | | | This patch adds the llvm::gsym::Header class which appears at the start of a stand alone GSYM file, or in the first bytes of the GSYM data in a GSYM section within a file. Added encode and decode methods with full error handling and full tests. Differential Revision: https://reviews.llvm.org/D67666 llvm-svn: 372149
* [ARM][AsmParser] Don't dereference a dyn_cast result. NFCI.Simon Pilgrim2019-09-171-50/+41
| | | | | | The static analyzer is warning about potential null dereferences of dyn_cast<> results - in these cases we can safely use cast<> directly as we know that these cases should all be the correct type, which is why its working atm and anyway cast<> will assert if they aren't. llvm-svn: 372145
* Reland "[SLC] Preserve attrs for strncpy(x, "", y) -> memset(align 1 x, ↵David Bolvansky2019-09-171-1/+4
| | | | | | '\0', y)" llvm-svn: 372142
* [PowerPC] Exploit single instruction load-and-splat for word and doublewordNemanja Ivanovic2019-09-174-14/+115
| | | | | | | | | | | We currently produce a load, followed by (possibly a move for integers and) a splat as separate instructions. VSX has always had a splatting load for doublewords, but as of Power9, we have it for words as well. This patch just exploits these instructions. Differential revision: https://reviews.llvm.org/D63624 llvm-svn: 372139
* [MemorySSA] Fix phi insertion when inserting a def.Alina Sbirlea2019-09-171-0/+3
| | | | | | | | | | | | | | | | | | | Summary: When inserting a Def, the current algorithm is walking edges backward and inserting new Phis where needed. There may be additional Phis needed in the IDF of the newly inserted Def and Phis. Adding Phis in the IDF of the Def was added ina previous patch, but we may also need other Phis in the IDF of the newly added Phis. Reviewers: george.burgess.iv Subscribers: Prazek, sanjoy.google, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67637 llvm-svn: 372138
* [MemorySSA] Update MSSA for non-conventional AA.Alina Sbirlea2019-09-171-1/+7
| | | | | | | | | | | | | | | | | | | Summary: Regularly when moving an instruction that may not read or write memory, the instruction is not modelled in MSSA, so not action is necessary. For a non-conventional AA pipeline, MSSA needs to explicitly check when creating accesses, so as to not model instructions that may not read and write memory. Reviewers: george.burgess.iv Subscribers: Prazek, sanjoy.google, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67562 llvm-svn: 372137
* GSYM: add encoding and decoding to FunctionInfoGreg Clayton2019-09-171-4/+132
| | | | | | | | This patch adds encoding and decoding of the FunctionInfo objects along with full error handling and tests. Full details of the FunctionInfo encoding format appear in the FunctionInfo.h header file. Differential Revision: https://reviews.llvm.org/D67506 llvm-svn: 372135
* [ARM] Add a SelectTAddrModeImm7 for MVE narrow loads and storesDavid Green2019-09-172-10/+35
| | | | | | | | | | | | We were previously using the SelectT2AddrModeImm7 for both normal and narrowing MVE loads/stores. As the narrowing instructions do not accept sp as a register, it makes little sense to optimise a FrameIndex into the load, only to have to recover that later on. This adds a SelectTAddrModeImm7 which does not do that folding, and uses it for narrowing load/store patterns. Differential Revision: https://reviews.llvm.org/D67489 llvm-svn: 372134
* [ARM] Reserve an emergency spill slot for fp16 addressing modes that need itDavid Green2019-09-171-1/+14
| | | | | | | | | | | Similar to D67327, but this time for the FP16 VLDR and VSTR instructions that use the AddrMode5FP16 addressing mode. We need to reserve an emergency spill slot for instructions that will be out of range to use sp directly. AddrMode5FP16 is 8 bits with a scale of 2. Differential Revision: https://reviews.llvm.org/D67483 llvm-svn: 372132
* [RISCV] Unbreak the buildBenjamin Kramer2019-09-171-4/+4
| | | | llvm-svn: 372127
* [ARM] Fix for buildbotsSam Parker2019-09-171-1/+0
| | | | | | | | Remove setPreservesCFG from ARMConstantIslandPass and add a couple of -verify-machine-dom-info instances into the existing codegen tests. llvm-svn: 372126
* Revert "[SLC] Preserve attrs for strncpy(x, "", y) -> memset(align 1 x, ↵Krasimir Georgiev2019-09-171-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | '\0', y)" Summary: This reverts commit r372101. Causes ASAN build bot failures: http://lab.llvm.org:8011/builders/sanitizer-ppc64be-linux/builds/14176 From http://lab.llvm.org:8011/builders/sanitizer-ppc64be-linux/builds/14176/steps/64-bit%20check-asan/logs/stdio: ``` [ RUN ] AddressSanitizer.StrNCatOOBTest /home/buildbots/ppc64be-sanitizer/sanitizer-ppc64be/build/llvm-project/compiler-rt/lib/asan/tests/asan_str_test.cpp:462: Failure Death test: strncat(to - 1, from, 0) Result: failed to die. ``` Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67658 llvm-svn: 372125
* [RISCV][NFC] Use NoRegister instead of 0 literalLuis Marques2019-09-171-4/+4
| | | | | | | | | | | | | | | | Summary: Trivial cleanup. Reviewers: asb, lenary Reviewed By: lenary Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67526 llvm-svn: 372120
* [X86] X86DAGToDAGISel::tryFoldLoad - assert root/parent pointers are ↵Simon Pilgrim2019-09-171-0/+1
| | | | | | | | non-null. NFCI. Silences a static analyzer warning. llvm-svn: 372118
* InterleavedAccessInfo - Don't dereference a dyn_cast result. NFCI.Simon Pilgrim2019-09-171-1/+1
| | | | llvm-svn: 372117
* [LoopVectorize] Don't dereference a dyn_cast result. NFCI.Simon Pilgrim2019-09-171-1/+1
| | | | | | The static analyzer is warning about potential null dereferences of dyn_cast<> results, we can use cast<> directly as we know that these cases should all be CastInst, which is why its working atm and anyway cast<> will assert if they aren't. llvm-svn: 372116
* [ARM] Fix for MVE load/store stack accessesDavid Green2019-09-171-7/+26
| | | | | | | | | | MVE loads and stores have a 7 bit immediate range, scaled by the length of the type. This needs to be taught to the stack estimation code to ensure that an emergency spill slot is reserved in case we run out of registers when materialising stack indices. Also the narrowing loads/stores can be created with frame indices even though they do not accept SP as a register. We need in those cases to make sure we have an emergency register to use as the frame base, as SP can never be used. Differential Revision: https://reviews.llvm.org/D67327 llvm-svn: 372114
* Hide implementation details in namespaces.Benjamin Kramer2019-09-176-9/+21
| | | | llvm-svn: 372113
* [ARM][LowOverheadLoops] Add LR def safety checkSam Parker2019-09-171-48/+139
| | | | | | | | | | | | | | | Converting the *LoopStart pseudo instructions into DLS/WLS results in LR being defined. These instructions were inserted on the assumption that LR would already contain the loop counter because a mov is introduced during ISel as the the consumers in the loop can only use LR. That assumption proved wrong! So perform a safety check, finding an appropriate place to insert the DLS/WLS instructions or revert if this isn't possible. Differential Revision: https://reviews.llvm.org/D67539 llvm-svn: 372111
* [obj2yaml] - Support PPC64 relocation types.George Rimar2019-09-171-0/+3
| | | | | | | | | | | | | We do not support them and fail with llvm_unreachable currently. This is not the only target we do not support and also seems we are missing the tests for those we have already. But I needed this one for another patch, so posted it separatelly. Relocation names are taken from llvm\include\llvm\BinaryFormat\ELFRelocs\PowerPC64.def Differential revision: https://reviews.llvm.org/D67615 llvm-svn: 372109
* [yaml2obj/obj2yaml] - Allow setting an arbitrary values for e_machine.George Rimar2019-09-171-0/+1
| | | | | | | | | | | | | | | Currently we only allow using a known named constants for `Machine` field in YAML documents. This patch allows using any numbers (valid or "unknown") and adds test cases for current and new functionality. With this it is possible to write a test cases for really unknown EM_* targets. Differential revision: https://reviews.llvm.org/D67652 llvm-svn: 372108
* [RISCV] Switch to the Machine SchedulerLuis Marques2019-09-171-0/+1
| | | | | | | | | Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
* [Attributor][Fix] Initialize the cache prior to using itJohannes Doerfert2019-09-171-59/+98
| | | | | | | | | | | | | | | | | | | | | Summary: There were segfaults as we modified and iterated the instruction maps in the cache at the same time. This was happening because we created new instructions while we populated the cache. This fix changes the order in which we perform these actions. First, the caches for the whole module are created, then we start to create abstract attributes. I don't have a unit test but the LLVM test suite exposes this problem. Reviewers: uenoku, sstefan1 Subscribers: hiraditya, bollu, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67232 llvm-svn: 372105
* Revert Patch from PhabricatorLuis Marques2019-09-171-1/+0
| | | | | | This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
* [X86] Use APInt::getLowBitsSet helper. NFCI.Simon Pilgrim2019-09-171-1/+2
| | | | | | Also avoids a static analyzer warning about out of range shifts. llvm-svn: 372103
* [SLC] Preserve attrs for strncpy(x, "", y) -> memset(align 1 x, '\0', y)David Bolvansky2019-09-171-1/+4
| | | | llvm-svn: 372101
* [SVE][MVT] Fixed-length vector MVT rangesGraham Hunter2019-09-1715-30/+33
| | | | | | | | | | | | | | | | | * Reordered MVT simple types to group scalable vector types together. * New range functions in MachineValueType.h to only iterate over the fixed-length int/fp vector types. * Stopped backends which don't support scalable vector types from iterating over scalable types. Reviewers: sdesmalen, greened Reviewed By: greened Differential Revision: https://reviews.llvm.org/D66339 llvm-svn: 372099
* [InstCombine] Annotate strdup with deref_or_nullDavid Bolvansky2019-09-172-0/+13
| | | | llvm-svn: 372098
* [NFCI] Fixed buildbotsDavid Bolvansky2019-09-171-6/+1
| | | | llvm-svn: 372097
* [SimplifyLibCalls] Fix -Wunused-result after D53342/r372091Fangrui Song2019-09-171-1/+2
| | | | llvm-svn: 372096
* Patch from PhabricatorLuis Marques2019-09-171-0/+1
| | | | llvm-svn: 372092
* [SimplifyLibCalls] Mark known arguments with nonnullDavid Bolvansky2019-09-171-84/+204
| | | | | | | | | | | | Reviewers: efriedma, jdoerfert Reviewed By: jdoerfert Subscribers: ychen, rsmith, joerg, aaron.ballman, lebedev.ri, uenoku, jdoerfert, hfinkel, javed.absar, spatel, dmgreen, llvm-commits Differential Revision: https://reviews.llvm.org/D53342 llvm-svn: 372091
* [AMDGPU]: PHI Elimination hooks added for custom COPY insertion. FixedAlexander Timofeev2019-09-174-29/+98
| | | | | | | Defferential Revision: https://reviews.llvm.org/D67101 Reviewers: rampitec, vpykhtin llvm-svn: 372086
* [ARM] LE support in ConstantIslandsSam Parker2019-09-171-26/+111
| | | | | | | | | | | | | The low-overhead branch extension provides a loop-end 'LE' instruction that performs no decrement nor compare, it just jumps backwards. This patch modifies the constant islands pass to try to insert LE instructions in place of a Thumb2 conditional branch, instead of shrinking it. This only happens if a cmp can be converted to a cbn/z and used to exit the loop. Differential Revision: https://reviews.llvm.org/D67404 llvm-svn: 372085
* [LoopUnroll] Use LoopSize+1 as threshold, to allow unrolling loops matching ↵Florian Hahn2019-09-171-3/+3
| | | | | | | | | | | | | | | | | LoopSize. We use `< UP.Threshold` later on, so we should use LoopSize + 1, to allow unrolling if the result won't exceed to loop size. Fixes PR43305. Reviewers: efriedma, dmgreen, paquette Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D67594 llvm-svn: 372084
* [ARM][MVE] Add invalidForTailPredication to TSFlagsSam Parker2019-09-173-0/+14
| | | | | | | | | Set this bit for the MVE reduction instructions to prevent a loop from becoming tail predicated in their presence. Differential Revision: https://reviews.llvm.org/D67444 llvm-svn: 372076
* [Attributor] Use Alias Analysis in noalias callsite argument deductionHideto Ueno2019-09-171-5/+12
| | | | | | | | | | | | | | | | Summary: This patch adds a check of alias analysis in `noalias` callsite argument deduction. Reviewers: jdoerfert, sstefan1 Reviewed By: jdoerfert Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67604 llvm-svn: 372075
* [Attributor] Create helper struct for handling analysis gettersHideto Ueno2019-09-171-18/+8
| | | | | | | | | | | | | | | | Summary: This patch introduces a helper struct `AnalysisGetter` to put together analysis getters. In this patch, a getter for `AAResult` is also added for `noalias`. Reviewers: jdoerfert, sstefan1 Reviewed By: jdoerfert Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67603 llvm-svn: 372072
* [X86] Split oversized vXi1 vector arguments and return values into scalars ↵Craig Topper2019-09-172-0/+34
| | | | | | | | | | | | | | | | | on avx512 targets. Previously we tried to split them into narrower v64i1 or v16i1 pieces that each got promoted to vXi8 and then passed in a zmm or xmm register. But this crashes when you need to pass more pieces than available registers reserved for argument passing. The scalarizing done here generates much longer and slower code, but is consistent with the behavior of avx2 and earlier targets for these types. Fixes PR43323. llvm-svn: 372069
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