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* WebAssembly: print basic integer assembly.JF Bastien2015-07-316-10/+134
| | | | | | | | | | | | | | | | | | | Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
* [COFF] Consider the ImageBase when reporting section addressesDavid Majnemer2015-07-311-2/+10
| | | | | | This lets us reenable the lld test disabled in r243758. llvm-svn: 243761
* [libFuzzer] support switch interception in dfsan modeKostya Serebryany2015-07-314-4/+41
| | | | llvm-svn: 243760
* [CodeGenPrepare] Compress a pair. No functional change.Benjamin Kramer2015-07-311-7/+3
| | | | llvm-svn: 243759
* [x86] reassociate integer multiplies using machine combiner passSanjay Patel2015-07-311-10/+30
| | | | | | | | | | | | | Add i16, i32, i64 imul machine instructions to the list of reassociation candidates. A new bit of logic is needed to handle integer instructions: they have an implicit EFLAGS operand, so we have to make sure it's dead in order to do any reassociation with integer ops. Differential Revision: http://reviews.llvm.org/D11660 llvm-svn: 243756
* [COFF] Return symbol VAs instead of RVAs for PE filesReid Kleckner2015-07-311-0/+8
| | | | | | | | This makes llvm-nm consistent with binutils nm on executables and DLLs. For a vanilla hello world executable, the address of main should include the default image base of 0x400000. llvm-svn: 243755
* [AArch64] Favor extended reg patterns for subGeoff Berry2015-07-311-0/+2
| | | | | | | | | | | | | | Summary: Favor the extended reg patterns over the shifted reg patterns that match only the operand shift and not the full sign/zero extend and shift. Reviewers: jmolloy, t.p.northover Subscribers: mcrosier, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D11569 llvm-svn: 243753
* [CaptureTracker] Provide an ordered basic block to PointerMayBeCapturedBeforeBruno Cardoso Lopes2015-07-315-72/+123
| | | | | | | | | | | | | | | | | | This patch is a follow up from r240560 and is a step further into mitigating the compile time performance issues in CaptureTracker. By providing the CaptureTracker with a "cached ordered basic block" instead of computing it every time, MemDepAnalysis can use this cache throughout its calls to AA->callCapturesBefore, avoiding to recompute it for every scanned instruction. In the same testcase used in r240560, compile time is reduced from 2min to 30s. This also fixes PR22348. rdar://problem/19230319 Differential Revision: http://reviews.llvm.org/D11364 llvm-svn: 243750
* [regalloc] Make RegMask clobbers prevent merging vreg's into PhysRegs when ↵Daniel Sanders2015-07-311-0/+8
| | | | | | | | | | | | | | | | | | | | | hoisting def's upwards. Summary: This prevents vreg260 and D7 from being merged in: %vreg260<def> = LDC1 ... JAL <ga:@sin>, <regmask ... list not containing D7 ...> %D7<def> = COPY %vreg260; ... Doing so is not valid because the JAL clobbers the D7. This fixes the almabench regression in the LLVM 3.7.0 release branch. Reviewers: MatzeB Subscribers: MatzeB, qcolombet, hans, llvm-commits Differential Revision: http://reviews.llvm.org/D11649 llvm-svn: 243745
* Refactor: Simplify boolean conditional return statements in lib/Target/NVPTXJingyue Wu2015-07-313-37/+15
| | | | | | | | | | | | Summary: Use clang-tidy to simplify boolean conditional return statements Reviewers: rafael, echristo, chandlerc, bkramer, craig.topper, dexonsmith, chapuni, eliben, jingyue, jholewinski Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D9983 llvm-svn: 243734
* AMDGPU: Fix v16i32 to v16i8 truncstoreMatt Arsenault2015-07-311-0/+1
| | | | llvm-svn: 243731
* [libFuzzer] trace switch statements and apply mutations based on the ↵Kostya Serebryany2015-07-315-4/+111
| | | | | | expected case values llvm-svn: 243726
* ELFYAML: Enable parsing of EM_AMDGPUTom Stellard2015-07-311-0/+1
| | | | | | | | Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11263 llvm-svn: 243724
* AMDGPU/SI: Set DwarfRegNumMatt Arsenault2015-07-311-6/+14
| | | | | | | This requires a fix in tablegen for the cast<int> from bits<16> to work in the list initializer. llvm-svn: 243723
* TableGen: Support folding casts from bits to intMatt Arsenault2015-07-311-0/+8
| | | | | | | | | | | | | | | This is to fix an incorrect error when trying to initialize DwarfNumbers with a !cast<int> of a bits initializer. getValuesAsListOfInts("DwarfNumbers") would not see an IntInit and instead the cast, so would give up. It seems likely that this could be generalized to attempt the convertInitializerTo for any type. I'm not really sure why the existing code seems to special case the string cast cases when convertInitializerTo seems like it should generally handle this sort of thing. llvm-svn: 243722
* AMDGPU/SI: Remove unused pattern for f32 constant loadsTom Stellard2015-07-311-1/+0
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11603 llvm-svn: 243719
* [ARM] Lower modulo operation to generate __aeabi_divmod on AndroidSumanth Gundapaneni2015-07-311-3/+4
| | | | | | | | | | | | | | For a modulo (reminder) operation, clang -target armv7-none-linux-gnueabi generates "__modsi3" clang -target armv7-none-eabi generates "__aeabi_idivmod" clang -target armv7-linux-androideabi generates "__modsi3" Android bionic libc doesn't provide a __modsi3, instead it provides a "__aeabi_idivmod". This patch fixes the LLVM ARMISelLowering to generate the correct call when ever there is a modulo operation. Differential Revision: http://reviews.llvm.org/D11661 llvm-svn: 243717
* MIR Parser: Report an error when a constant pool item is redefined.Alex Lorenz2015-07-301-3/+6
| | | | llvm-svn: 243696
* MIR Parser: Report an error when a virtual register is redefined.Alex Lorenz2015-07-301-3/+5
| | | | llvm-svn: 243695
* fix memcpy/memset/memmove lowering when optimizing for sizeSanjay Patel2015-07-303-11/+21
| | | | | | | | | | | | | | | | | | | | Fixing MinSize attribute handling was discussed in D11363. This is a prerequisite patch to doing that. The handling of OptSize when lowering mem* functions was broken on Darwin because it wants to ignore -Os for these cases, but the existing logic also made it ignore -Oz (MinSize). The Linux change demonstrates a widespread problem. The backend doesn't usually recognize the MinSize attribute by itself; it assumes that if the MinSize attribute exists, then the OptSize attribute must also exist. Fixing this more generally will be a follow-on patch or two. Differential Revision: http://reviews.llvm.org/D11568 llvm-svn: 243693
* [libFuzzer] fix the strncmp interceptor -- it should respect short strings. Kostya Serebryany2015-07-303-3/+31
| | | | llvm-svn: 243691
* enable fast-math-flag propagation to DAG nodesSanjay Patel2015-07-301-1/+1
| | | | | | | | | | | This uncovered latent bugs previously: http://reviews.llvm.org/D10403 ...but it's time to try again because internal tests aren't finding more. If time passes and no other bugs are reported, we can remove this cl::opt. llvm-svn: 243687
* Enable dfsan for aarch64Adhemerval Zanella2015-07-301-0/+4
| | | | | | This patch enable DFSan memory transformation for aarch64 (39-bit VMA). llvm-svn: 243684
* Add a TargetMachine hook that verifies DataLayout compatibilityMehdi Amini2015-07-301-0/+4
| | | | | | | | | | | | | Summary: Also provide the associated assertion when CodeGen starts. Reviewers: echristo Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11654 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 243682
* [SLP vectorizer]: Choose the best consecutive candidate to pair with a store ↵Wei Mi2015-07-301-7/+18
| | | | | | | | | | | | | instruction. The patch changes the SLPVectorizer::vectorizeStores to choose the immediate succeeding or preceding candidate for a store instruction when it has multiple consecutive candidates. In this way it has better chance to find more slp vectorization opportunities. Differential Revision: http://reviews.llvm.org/D10445 llvm-svn: 243666
* AMDGPU: Set SubRegIndex size and offsetMatt Arsenault2015-07-301-2/+1
| | | | | | | | I'm not sure what reasons the comment here could have had for not setting these. Without these set, there is an assertion hit during DWARF emission. llvm-svn: 243661
* AMDGPU: Fix unreachable when emitting binary debug infoMatt Arsenault2015-07-301-1/+33
| | | | | | | | | | | Copy implementation of applyFixup from AArch64 with AArch64 bits ripped out. Tests will be included with a later commit. Several other problems must be fixed before binary debug info emission will work. llvm-svn: 243660
* MIR Serialization: Serialize the machine basic block's successor weights.Alex Lorenz2015-07-302-1/+26
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 243659
* [COFF] Add IMAGE_SCN_TYPE_NOLOAD to SectionCharacteristicsDavid Majnemer2015-07-301-0/+1
| | | | llvm-svn: 243658
* AMDGPU/SI: Simplify moveSMRDToVALU()Tom Stellard2015-07-301-11/+9
| | | | | | | | | | | | | | | Summary: Replace the switch on instruction opcode with a switch on register size. This way we don't need to update the switch statement when we add new SMRD variants. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11601 llvm-svn: 243652
* AMDGPU/SI: Remove isTriviallyReMaterializable() function from SIInstrInfoTom Stellard2015-07-302-15/+0
| | | | | | | | | | | | | | Summary: This function is never called. isReallyTriviallyReMaterializable() is the function that should be implemented instead. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11620 llvm-svn: 243651
* [mips][FastISel] Remove hidden mips-fast-isel option.Vasileios Kalintiris2015-07-301-6/+2
| | | | | | | | | | | | | | | Summary: This hidden option would disable code generation through FastISel by default. It was removed from the available options and from the Fast-ISel tests that required it in order to run the tests. Reviewers: dsanders Subscribers: qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D11610 llvm-svn: 243638
* [mips][FastISel] Apply only zero-extension to constants prior to their ↵Vasileios Kalintiris2015-07-301-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | materialization. Summary: Previously, we would sign-extend non-boolean negative constants and zero-extend otherwise. This was problematic for PHI instructions with negative values that had a type with bitwidth less than that of the register used for materialization. More specifically, ComputePHILiveOutRegInfo() assumes the constants present in a PHI node are zero extended in their container and afterwards deduces the known bits. For example, previously we would materialize an i16 -4 with the following instruction: addiu $r, $zero, -4 The register would end-up with the 32-bit 2's complement representation of -4. However, ComputePHILiveOutRegInfo() would generate a constant with the upper 16-bits set to zero. The SelectionDAG builder would use that information to generate an AssertZero node that would remove any subsequent trunc & zero_extend nodes. In theory, we should modify ComputePHILiveOutRegInfo() to consult target-specific hooks about the way they prefer to materialize the given constants. However, git-blame reports that this specific code has not been touched since 2011 and it seems to be working well for every target so far. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11592 llvm-svn: 243636
* [X86] Recognize "flags" as an identifier, not a register in Intel-syntax ↵Michael Kuperstein2015-07-301-0/+5
| | | | | | | | | inline asm Patch by: marina.yatsina@intel.com Differential Revision: http://reviews.llvm.org/D11512 llvm-svn: 243630
* Add amdopencl environment to tripleMatt Arsenault2015-07-301-0/+2
| | | | | | | This is used by the AMD x86 OpenCL implementation to change some ABI details on Windows and Linux. llvm-svn: 243627
* [LoopVer] Add missing std::moveAdam Nemet2015-07-301-1/+2
| | | | | | | | | | | | The reason I was passing this vector by value in the constructor so that I wouldn't have to copy when initializing the corresponding member but then I forgot the std::move. The use-case is LoopDistribution which filters the checks then std::moves it to LoopVersioning's constructor. With this interface we can avoid any copies. llvm-svn: 243616
* [LDist] Filter the checks locally rather than in LAA, NFCAdam Nemet2015-07-301-2/+43
| | | | | | | | | | | | | | | Before, we were passing the pointer partitions to LAA. Now, we get all the checks from LAA and filter out the checks within partitions in LoopDistribution. This effectively concludes the steps to move filtering memchecks from LAA into its clients. There is still some cleanup left to remove the unused interfaces in LAA that still take PtrPartition. (Moving this functionality to LoopDistribution also requires needsChecking on pointers to be made public.) llvm-svn: 243613
* [libFuzzer] implement strncmp hook for data-flow-guided fuzzing (w/ and w/o ↵Kostya Serebryany2015-07-306-4/+45
| | | | | | dfsan), add a test llvm-svn: 243611
* [libFuzzer] implement memcmp hook for data-flow-guided fuzzing (w/o dfsan), ↵Kostya Serebryany2015-07-305-3/+24
| | | | | | extend the memcmp fuzzer test llvm-svn: 243603
* push fast-math check for machine-combiner reassociations into ↵Sanjay Patel2015-07-301-7/+4
| | | | | | | | instruction-type check; NFC This makes it simpler to add instruction types that don't depend on fast-math. llvm-svn: 243596
* [MCJIT] Fix PR20656 by teaching MCJIT to honor ExecutionEngine's global mapping.Lang Hames2015-07-292-2/+15
| | | | | | | This is important for users of the C API who can't supply custom symbol resolvers yet. llvm-svn: 243589
* Fix typo "fuction" noticed in comments in AssumptionCache.h, and also all ↵Nick Lewycky2015-07-2914-14/+14
| | | | | | | | the other files that have the same typo. All comments, no functionality change! (Merely a "fuctionality" change.) Bonus change to remove emacs major mode marker from SystemZMachineFunctionInfo.cpp because emacs already knows it's C++ from the extension. Also fix typo "appeary" in AMDGPUMCAsmInfo.h. llvm-svn: 243585
* Reapply "Add reverse(ContainerTy) range adapter."Pete Cooper2015-07-291-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit r243567, which ultimately reapplies r243563. The fix here was to use std::enable_if for overload resolution. Thanks to David Blaikie for lots of help on this, and for the extra tests! Original commit message follows: For cases where we needed a foreach loop in reverse over a container, we had to do something like for (const GlobalValue *GV : make_range(TypeInfos.rbegin(), TypeInfos.rend())) { This provides a convenience method which shortens this to for (const GlobalValue *GV : reverse(TypeInfos)) { There are 2 versions of this, with a preference to the rbegin() version. The first uses rbegin() and rend() to construct an iterator_range. The second constructs an iterator_range from the begin() and end() methods wrapped in std::reverse_iterator's. Reviewed by David Blaikie. llvm-svn: 243581
* Rename hasCompatibleFunctionAttributes->areInlineCompatible basedEric Christopher2015-07-294-8/+8
| | | | | | | on suggestions. Currently the function is only used for inline purposes and this is more descriptive for the use. llvm-svn: 243578
* [X86][SSE] Keep 32-bit target i64 vector shifts on SSE unit.Simon Pilgrim2015-07-291-15/+31
| | | | | | | | This patch improves the 32-bit target i64 constant matching to detect the shuffle vector splats that are introduced by i64 vector shift vectorization (D8416). Differential Revision: http://reviews.llvm.org/D11327 llvm-svn: 243577
* AArch64: use 32-bit MOV rather than UBFX to truncate registers.Tim Northover2015-07-291-3/+3
| | | | | | | | | It's potentially more efficient on Cyclone, and from the optimization guides & schedulers looks like it has no effect on Cortex-A53 or A57. In general you'd expect a MOV to be about the most efficient instruction with its semantics, even though the official "UXTW" alias is really a UBFX. llvm-svn: 243576
* MIR Serialization: Serialize the frame info's save and restore points.Alex Lorenz2015-07-292-8/+33
| | | | | | | This commit serializes the save and restore machine basic block references from the machine frame information class. llvm-svn: 243575
* MIR Parser: Extract the code that parses MBB references into a new method. NFC.Alex Lorenz2015-07-291-5/+18
| | | | | | | This commit extracts the code that's used by the class 'MIRParserImpl' to parse the machine basic block references into a new method named 'parseMBBReference'. llvm-svn: 243572
* [X86][SSE] Vectorize i64 ASHR operationsSimon Pilgrim2015-07-292-4/+18
| | | | | | | | This patch vectorizes the v2i64/v4i64 ASHR shift operations - the last remaining integer vector shifts that are still being transferred to/from the scalar unit to be completed. Differential Revision: http://reviews.llvm.org/D11439 llvm-svn: 243569
* Revert "Add reverse(ContainerTy) range adapter."Pete Cooper2015-07-291-1/+2
| | | | | | | | | This reverts commit r243563. The GCC buildbots were extremely unhappy about this. Reverting while we discuss a better way of doing overload resolution. llvm-svn: 243567
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