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* Convert some AArch64 code to foreach loops. NFC.Pete Cooper2015-08-035-26/+23
| | | | | | | Also converted a cast<> to dyn_cast while i was working on the same line of code. llvm-svn: 243894
* Revert "-Wdeprecated-clean: Fix cases of violating the rule of 5 in ways ↵Reid Kleckner2015-08-032-20/+15
| | | | | | | | | | that are deprecated in C++11" This reverts commit r243824. It broke the build on Windows. llvm-svn: 243888
* DI: Disallow uniquable DICompileUnitsDuncan P. N. Exon Smith2015-08-039-92/+59
| | | | | | | | | | | | | | | | | | Since r241097, `DIBuilder` has only created distinct `DICompileUnit`s. The backend is liable to start relying on that (if it hasn't already), so make uniquable `DICompileUnit`s illegal and automatically upgrade old bitcode. This is a nice cleanup, since we can remove an unnecessary `DenseSet` (and the associated uniquing info) from `LLVMContextImpl`. Almost all the testcases were updated with this script: git grep -e '= !DICompileUnit' -l -- test | grep -v test/Bitcode | xargs sed -i '' -e 's,= !DICompileUnit,= distinct !DICompileUnit,' I imagine something similar should work for out-of-tree testcases. llvm-svn: 243885
* ARM: prefer allocating VFP regs at stride 4 on Darwin.Tim Northover2015-08-033-9/+27
| | | | | | | | | This is necessary for WatchOS support, where the compact unwind format assumes this kind of layout. For now we only want this on Swift-like CPUs though, where it's been the Xcode behaviour for ages. Also, since it can expand the prologue we don't want it at -Oz. llvm-svn: 243884
* Linker: Move distinct MDNodes instead of cloningDuncan P. N. Exon Smith2015-08-032-32/+43
| | | | | | | | | | | | | | | | | | | | | Instead of cloning distinct `MDNode`s when linking in a module, just move them over. The module linker destroys the source module, so the old node would otherwise just be leaked on the context. Create the new node in place. This also reduces the number of cloned uniqued nodes (since it's less likely their operands have changed). This mapping strategy is only correct when we're discarding the source, so the linker turns it on via a ValueMapper flag, `RF_MoveDistinctMDs`. There's nothing observable in terms of `llvm-link` output here: the linked module should be semantically identical. I'll be adding more 'distinct' nodes to the debug info metadata graph in order to break uniquing cycles, so the benefits of this will partly come in future commits. However, we should get some gains immediately, since we have a fair number of 'distinct' `DILocation`s being linked in. llvm-svn: 243883
* Refactor AtomicExpand::expandAtomicRMWToCmpXchg into a standalone function.JF Bastien2015-08-031-66/+82
| | | | | | | | | | | | | | | Summary: This is useful for PNaCl's `RewriteAtomics` pass. NaCl intrinsics don't exist for some of the more exotic RMW instructions, so by refactoring this function into its own, `RewriteAtomics` can share code rewriting those atomics with `AtomicExpand` while additionally saving a few cycles by generating the `cmpxchg` NaCl-specific intrinsic with the callback. Without this patch, `RewriteAtomics` would require two extra passes over functions, by first requiring use of the full `AtomicExpand` pass to just expand the leftover exotic RMWs and then running itself again to expand resulting `cmpxchg`s. NFC Reviewers: jfb Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D11422 llvm-svn: 243880
* Currently string attributes on function arguments/return values can be ↵Artur Pilipenko2015-08-032-7/+26
| | | | | | | | | | | | | | | generated using LLVM API. However they are not supported in parser. So, the following scenario will fail: * generate function with string attribute using API, * dump it in LL format, * try to parse. Add parser support for string attributes to fix the issue. Reviewed By: reames, hfinkel Differential Revision: http://reviews.llvm.org/D11058 llvm-svn: 243877
* [ARM] Make GlobalMerge merge extern globals by defaultJohn Brawn2015-08-031-1/+7
| | | | | | | | | | | Enabling merging of extern globals appears to be generally either beneficial or harmless. On some benchmarks suites (on Cortex-M4F, Cortex-A9, and Cortex-A57) it gives improvements in the 1-5% range, but in the rest the overall effect is zero. Differential Revision: http://reviews.llvm.org/D10966 llvm-svn: 243874
* [GlobalMerge] Allow targets to enable merging of extern variables, NFC.John Brawn2015-08-031-8/+15
| | | | | | | | | | Adjust the GlobalMergeOnExternal option so that the default behaviour is to do whatever the Target thinks is best. Explicitly enabled or disabling the option will override this default. Differential Revision: http://reviews.llvm.org/D10965 llvm-svn: 243873
* Be less conservative about forming IT blocks.James Molloy2015-08-031-1/+1
| | | | | | | | | | | | | | | | In http://reviews.llvm.org/rL215382, IT forming was made more conservative under the belief that a flag-setting instruction was unpredictable inside an IT block on ARMv6M. But actually, ARMv6M doesn't even support IT blocks so that's impossible. In the ARMARM for v7M, v7AR and v8AR it states that the semantics of such an instruction changes inside an IT block - it doesn't set the flags. So actually it is fine to use one inside an IT block as long as the flags register is dead afterwards. This gives significant performance improvements in a variety of MPEG based workloads. Differential revision: http://reviews.llvm.org/D11680 llvm-svn: 243869
* ValueMapper: Only check for cycles if operands changeDuncan P. N. Exon Smith2015-08-031-6/+7
| | | | | | | | | | This is a minor optimization to only check for unresolved operands inside `mapDistinctNode()` if the operands have actually changed. This shouldn't really cause any change in behaviour. I didn't actually see a slowdown in a profile, I was just poking around nearby and saw the opportunity. llvm-svn: 243866
* ValueMapper: Use a range-based for, NFCDuncan P. N. Exon Smith2015-08-031-6/+3
| | | | llvm-svn: 243865
* ValueMapper: Reuse local variable, NFCDuncan P. N. Exon Smith2015-08-031-2/+2
| | | | llvm-svn: 243864
* Use early return NFC.Frederic Riss2015-08-031-8/+8
| | | | llvm-svn: 243863
* WebAssembly: implement getScalarShiftAmountTy so we can shift by amount, ↵JF Bastien2015-08-032-0/+7
| | | | | | | | | | | | with type Summary: This currently sets the shift amount RHS to the same type as the LHS, and assumes that the LHS is a simple type. This isn't currently the case e.g. with weird integers sizes, but will eventually be true and will assert if not. That's what you get for having an experimental backend: break it and you get to keep both pieces. Most backends either set the RHS to MVT::i32 or MVT::i64, but WebAssembly is a virtual ISA and tries to have regular-looking binary operations where both operands are the same type (even if a 64-bit RHS shifter is slightly silly, hey it's free!). Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11715 llvm-svn: 243860
* Use range-based for loops. NFCCraig Topper2015-08-021-31/+26
| | | | llvm-svn: 243859
* AsmPrinter: Split out non-DIE printing from DIE::print(), NFCDuncan P. N. Exon Smith2015-08-021-28/+24
| | | | | | | | Split out a helper `printValues()` for printing `DIEBlock` and `DIELoc`, instead of relying on `DIE::print()`. The shared code was actually fairly small there. No functionality change intended. llvm-svn: 243856
* AsmPrinter: Take DIEValueList in some DwarfUnit API, NFCDuncan P. N. Exon Smith2015-08-022-13/+17
| | | | | | | Take `DIEValueList` instead of `DIE` so that `DIEBlock` and `DIELoc` can stop inheriting from `DIE` in a future commit. llvm-svn: 243855
* AsmPrinter: Change DIEValueList to a subclass of DIE, NFCDuncan P. N. Exon Smith2015-08-021-6/+6
| | | | | | | | | | | | | | | Rewrite `DIEValueList` as a subclass of `DIE`, renaming its API to match `DIE`'s. This is preparation for changing `DIEBlock` and `DIELoc` to stop inheriting from `DIE` and inherit directly from `DIEValueList`. I thought about leaving this as a has-a relationship (and changing `DIELoc` and `DIEBlock` to also have-a `DIEValueList`), but that seemed to require a fair bit more boilerplate and I think it needed more changes to the `DwarfUnit` API than this will. No functionality change intended here. llvm-svn: 243854
* Add support to set/get ordering for load/store from the C APIAndrew Wilkins2015-08-021-1/+34
| | | | | | | | | | | | Summary: As per title Reviewers: chandlerc, bogner, majnemer, axw Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11141 llvm-svn: 243847
* Mark CompositeType::getTypeAtIndex as const. NFCCraig Topper2015-08-011-5/+7
| | | | llvm-svn: 243845
* Mark Type::getPointerTo as const. Unfortunately, this requires a const_cast ↵Craig Topper2015-08-011-2/+2
| | | | | | inside, but at least it makes all methods on Type const. NFC llvm-svn: 243844
* Merge the const and non-const Type::getScalarType to a const version that ↵Craig Topper2015-08-011-9/+3
| | | | | | returns a non-const pointer. Since we don't put const on Types all places were already calling the non-const version. llvm-svn: 243843
* De-constify pointers to Type since they can't be modified. NFCCraig Topper2015-08-0126-116/+113
| | | | | | This was already done in most places a while ago. This just fixes the ones that crept in over time. llvm-svn: 243842
* [NVPTX] allow register copy between float and intJingyue Wu2015-08-011-22/+23
| | | | | | | | | | | | | | | Summary: Fixes PR24303. With Bruno's WIP (D11197) on PeepholeOptimizer, across-class register copying (e.g. i32 to f32) becomes possible. Enhance NVPTXInstrInfo::copyPhysReg to handle these cases. Reviewers: jholewinski Subscribers: eliben, jholewinski, llvm-commits, bruno Differential Revision: http://reviews.llvm.org/D11622 llvm-svn: 243839
* Remove trailing whitespace. NFCI.Simon Pilgrim2015-08-011-7/+7
| | | | llvm-svn: 243838
* Use SDValue bool check. NFCI.Simon Pilgrim2015-08-011-20/+10
| | | | llvm-svn: 243837
* [DAGCombiner] Convert constant AND masks to shuffle clear masks down to the ↵Simon Pilgrim2015-08-011-21/+64
| | | | | | | | | | | | | | byte level The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks. This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading. There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.) Differential Revision: http://reviews.llvm.org/D11518 llvm-svn: 243831
* -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are ↵David Blaikie2015-08-012-9/+1
| | | | | | | | | | deprecated in C++11 Remove some unnecessary explicit special members in Hexagon that, once removed, allow the other implicit special members to be used without depending on deprecated features. llvm-svn: 243825
* -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are ↵David Blaikie2015-08-012-15/+20
| | | | | | deprecated in C++11 llvm-svn: 243824
* WebAssembly: handle more than int32 argument/returnJF Bastien2015-08-014-8/+30
| | | | | | | | | | | | Summary: Also test 64-bit integers, except shifts for now which are broken because isel dislikes the 32-bit truncate that precedes them. Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11699 llvm-svn: 243822
* -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are ↵David Blaikie2015-08-011-81/+0
| | | | | | | | | | | | deprecated in C++11 Various targets use std::swap on specific MCAsmOperands (ARM and possibly Hexagon as well). It might be helpful to mark those subclasses as final, to ensure that the availability of move/copy operations can't lead to slicing. (same sort of requirements as the non-vitual dtor - protected or a final class) llvm-svn: 243820
* [libFuzzer] more refactoring of the Mutator and adding tests to itKostya Serebryany2015-08-013-26/+133
| | | | llvm-svn: 243818
* [libFuzzer] start refactoring the Mutator and adding tests to itKostya Serebryany2015-08-015-14/+58
| | | | llvm-svn: 243817
* AMDGPU/SI: Add implicit register operands in the correct order.Alex Lorenz2015-07-312-21/+1
| | | | | | | | | | | | | | | | | | This commit fixes a bug in the class 'SIInstrInfo' where the implicit register machine operands were added to a machine instruction in an incorrect order - the implicit uses were added before the implicit defs. I found this bug while working on moving the implicit register operand verification code from the MIR parser to the machine verifier. This commit also makes the method 'addImplicitDefUseOperands' in the machine instruction class public so that it can be reused in the 'SIInstrInfo' class. Reviewers: Matt Arsenault Differential Revision: http://reviews.llvm.org/D11689 llvm-svn: 243799
* MIR Parser: Report an error when a jump table entry is redefined.Alex Lorenz2015-07-311-2/+5
| | | | llvm-svn: 243798
* MIR Parser: Remove unused variable.Alex Lorenz2015-07-311-1/+0
| | | | | | This variable is unused as of r243572. llvm-svn: 243796
* [libFuzzer] limit the size of the inputs printed to stderrKostya Serebryany2015-07-311-4/+10
| | | | llvm-svn: 243795
* [NVPTX] convert pointers in byval kernel arguments to globalJingyue Wu2015-07-311-20/+81
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: For example, in struct S { int *x; int *y; }; __global__ void foo(S s) { int *b = s.y; // use b } "b" is guaranteed to point to global. NVPTX should emit ld.global/st.global for accessing "b". Reviewers: jholewinski Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11505 llvm-svn: 243790
* -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are ↵David Blaikie2015-07-311-4/+3
| | | | | | deprecated in C++11 llvm-svn: 243788
* WebAssembly: handle `ret void`.JF Bastien2015-07-313-3/+3
| | | | | | | | | | | | | | | Summary: Use -1 as numoperands for the return SDTypeProfile, denoting that return is variadic. Note that the patterns in InstrControl.td still need to match the inputs, so this ins't an "anything goes" variadic on ret! The next step will be to handle other local types (not just int32). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11692 llvm-svn: 243783
* [libFuzzer] make sure that 2-byte arguments of switch() are handled properlyKostya Serebryany2015-07-313-13/+52
| | | | llvm-svn: 243781
* MIR Serialization: Serialize the floating point immediate machine operands.Alex Lorenz2015-07-314-2/+80
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 243780
* [dwarfdump] Ignore scattered relocations for mach-o.Frederic Riss2015-07-311-3/+9
| | | | | | | | | | | | | | When encountering a scattered relocation, the code would assert trying to access an unexisting section. I couldn't find a way to expose the result of the processing of a scattered reloc, and I'm really unsure what the right thing to do is. This patch just skips them during the processing in DwarfContext and adds a mach-o file to the tests that exposed the asserting behavior. (This is a new failure that is being exposed by Rafael's recent work on the libObject interfaces. I think the wrong behavior has always happened, but now it's asserting) llvm-svn: 243778
* DI: Remove DW_TAG_arg_variable and DW_TAG_auto_variableDuncan P. N. Exon Smith2015-07-3112-51/+44
| | | | | | | | | | | | | | | | | | | | | | | | Remove the fake `DW_TAG_auto_variable` and `DW_TAG_arg_variable` tags, using `DW_TAG_variable` in their place Stop exposing the `tag:` field at all in the assembly format for `DILocalVariable`. Most of the testcase updates were generated by the following sed script: find test/ -name "*.ll" -o -name "*.mir" | xargs grep -l 'DILocalVariable' | xargs sed -i '' \ -e 's/tag: DW_TAG_arg_variable, //' \ -e 's/tag: DW_TAG_auto_variable, //' There were only a handful of tests in `test/Assembly` that I needed to update by hand. (Note: a follow-up could change `DILocalVariable::DILocalVariable()` to set the tag to `DW_TAG_formal_parameter` instead of `DW_TAG_variable` (as appropriate), instead of having that logic magically in the backend in `DbgVariable`. I've added a FIXME to that effect.) llvm-svn: 243774
* x86: check hasOpaqueSPAdjustment in canRealignStackJF Bastien2015-07-311-4/+6
| | | | | | | | | | | | | | | Summary: @rnk pointed out in [1] that x86's canRealignStack logic should match that in CantUseSP from hasBasePointer. [1]: http://reviews.llvm.org/D11160?id=29713#inline-89350 Reviewers: rnk Subscribers: rnk, llvm-commits Differential Revision: http://reviews.llvm.org/D11377 llvm-svn: 243772
* WebAssembly: handle unused function arguments.JF Bastien2015-07-311-4/+6
| | | | | | | | Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11684 llvm-svn: 243770
* [libFuzzer] record traces from the switch statements only when told to do soKostya Serebryany2015-07-311-0/+1
| | | | llvm-svn: 243768
* New EH representation for MSVC compatibilityDavid Majnemer2015-07-3126-49/+1180
| | | | | | | | | | This introduces new instructions neccessary to implement MSVC-compatible exception handling support. Most of the middle-end and none of the back-end haven't been audited or updated to take them into account. Differential Revision: http://reviews.llvm.org/D11097 llvm-svn: 243766
* DI: Rewrite the DIBuilder local variable APIDuncan P. N. Exon Smith2015-07-311-3/+23
| | | | | | | | | | | | Replace the general `createLocalVariable()` with two more specific functions: `createParameterVariable()` and `createAutoVariable()`, and rewrite the documentation. Besides cleaning up the API, this avoids exposing the fake DWARF tags `DW_TAG_arg_variable` and `DW_TAG_auto_variable` to frontends, and is preparation for removing them completely. llvm-svn: 243764
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