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* Make PPCCompilationCallbackC function to be static, so there will be no need ↵Anton Korobeynikov2012-04-031-3/+5
| | | | | | | | to issue call via PLT when LLVM is built as shared library. This mimics the X86 backend towards the approach. llvm-svn: 153938
* Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.Craig Topper2012-04-035-41/+49
| | | | llvm-svn: 153935
* Revert r153924. Delete test/MC/Disassembler/Mips and ↵Akira Hatanaka2012-04-034-0/+0
| | | | | | lib/Target/Mips/Disassembler. llvm-svn: 153926
* Revert r153924. There were buildbot failures.Akira Hatanaka2012-04-0313-925/+104
| | | | llvm-svn: 153925
* MIPS disassembler support.Akira Hatanaka2012-04-0313-104/+925
| | | | | | Patch by Vladimir Medic. llvm-svn: 153924
* Add a line number for the scope of the function (starting at the firstEric Christopher2012-04-033-5/+20
| | | | | | | | | | brace) so that we get more accurate line number information about the declaration of a given function and the line where the function first starts. Part of rdar://11026482 llvm-svn: 153916
* Fixes to r153903. Added missing explanation of behaviour when the ↵Pete Cooper2012-04-031-5/+5
| | | | | | VirtRegMap is NULL. Also changed it in this case to just avoid updating the map, but live ranges or intervals will still get updated and created llvm-svn: 153914
* Moved LiveRangeEdit.h so that it can be called from other parts of the ↵Pete Cooper2012-04-029-210/+8
| | | | | | backend, not just libCodeGen llvm-svn: 153906
* Allocate virtual registers in ascending order.Jakob Stoklund Olesen2012-04-021-2/+2
| | | | | | | | | This is just the fallback tie-breaker ordering, the main allocation order is still descending size. Patch by Shamil Kurmangaleev! llvm-svn: 153904
* Refactored the LiveRangeEdit interface so that MachineFunction, ↵Pete Cooper2012-04-028-93/+76
| | | | | | TargetInstrInfo, MachineRegisterInfo, LiveIntervals, and VirtRegMap are all passed into the constructor and stored as members instead of passed in to each method. llvm-svn: 153903
* Add an option to turn off the expensive GVN load PRE part of GVN.Bill Wendling2012-04-021-4/+5
| | | | llvm-svn: 153902
* Add predicates for checking whether targets have free FNEG and FABS ↵Owen Anderson2012-04-021-3/+5
| | | | | | operations, and prevent the DAGCombiner from turning them into bitwise operations if they do. llvm-svn: 153901
* During two-address lowering, rescheduling an instruction does not untieLang Hames2012-04-021-2/+2
| | | | | | | operands. Make TryInstructionTransform return false to reflect this. Fixes PR11861. llvm-svn: 153892
* Initial 64 bit direct object support.Akira Hatanaka2012-04-024-23/+49
| | | | | | | | | | | This patch allows llvm to recognize that a 64 bit object file is being produced and that the subsequently generated ELF header has the correct information. The test case checks for both big and little endian flavors. Patch by Jack Carter. llvm-svn: 153889
* The binutils for the IBM BG/P are too old to support CFI.Hal Finkel2012-04-022-0/+6
| | | | llvm-svn: 153886
* Add triple support for the IBM BG/P and BG/Q supercomputers.Hal Finkel2012-04-021-0/+6
| | | | llvm-svn: 153882
* Turn on the accelerator tables for Darwin.Eric Christopher2012-04-021-0/+6
| | | | llvm-svn: 153880
* Fast fix for PR12343:Stepan Dyatkovskiy2012-04-021-4/+29
| | | | | | | | | | http://llvm.org/bugs/show_bug.cgi?id=12343 We have not trivial way for splitting edges that are goes from indirect branch. We can do it with some tricks, but it should be additionally discussed. And it is still dangerous due to difficulty of indirect branches controlling. Fix forbids this case for unswitching. llvm-svn: 153879
* Implement the SVR4 byval alignment for aggregates. Fixing a FIXME.Roman Divacky2012-04-021-1/+10
| | | | llvm-svn: 153876
* Move getOpcodeName from the various target InstPrinters into the superclass ↵Benjamin Kramer2012-04-0213-30/+2
| | | | | | | | MCInstPrinter. All implementations used the same code. llvm-svn: 153866
* Optimizing swizzles of complex shuffles may generate additional complex ↵Nadav Rotem2012-04-021-1/+9
| | | | | | | | | shuffles. Do not try to optimize swizzles of shuffles if the source shuffle has more than a single user, except when the source shuffle is also a swizzle. llvm-svn: 153864
* Remove getInstructionName from MCInstPrinter implementations in favor of ↵Craig Topper2012-04-0213-24/+12
| | | | | | using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. llvm-svn: 153863
* Make MCInstrInfo available to the MCInstPrinter. This will be used to remove ↵Craig Topper2012-04-0221-31/+58
| | | | | | getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. llvm-svn: 153860
* Fix some 80-col. violations I introduced with the A2 PPC64 core.Hal Finkel2012-04-012-63/+126
| | | | llvm-svn: 153852
* Enable prefetch generation on PPC64.Hal Finkel2012-04-012-0/+6
| | | | llvm-svn: 153851
* Add LdStSTD* itin. for the PPC64 A2 core.Hal Finkel2012-04-011-0/+20
| | | | llvm-svn: 153850
* This commit contains a few changes that had to go in together.Nadav Rotem2012-04-012-8/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) (and also scalar_to_vector). 2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src). Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B)) 3. Optimize swizzles of shuffles: shuff(shuff(x, y), undef) -> shuff(x, y). 4. Fix an X86ISelLowering optimization which was very bitcast-sensitive. Code which was previously compiled to this: movd (%rsi), %xmm0 movdqa .LCPI0_0(%rip), %xmm2 pshufb %xmm2, %xmm0 movd (%rdi), %xmm1 pshufb %xmm2, %xmm1 pxor %xmm0, %xmm1 pshufb .LCPI0_1(%rip), %xmm1 movd %xmm1, (%rdi) ret Now compiles to this: movl (%rsi), %eax xorl %eax, (%rdi) ret llvm-svn: 153848
* Fix typo.Lang Hames2012-04-011-1/+1
| | | | llvm-svn: 153846
* Set the default PPC node scheduling preference to ILP (for the embedded cores).Hal Finkel2012-04-012-0/+10
| | | | | | | The 440 and A2 cores have detailed itineraries, and this allows them to be fully used to maximize throughput. llvm-svn: 153845
* Add ppc440 itin. entries for LdStSTD*Hal Finkel2012-04-011-0/+20
| | | | llvm-svn: 153844
* Use full anti-dep. breaking with post-ra sched. on the embedded ppc cores.Hal Finkel2012-04-011-2/+3
| | | | | | | | | | | Post-RA scheduling gives a significant performance improvement on the embedded cores, so turn it on. Using full anti-dep. breaking is important for FP-intensive blocks, so turn it on (just on the embedded cores for now; this should also be good on the 970s because post-ra scheduling is all that we have for now, but that should have more testing first). llvm-svn: 153843
* Add instruction itinerary for the PPC64 A2 core.Hal Finkel2012-04-017-4/+582
| | | | | | | This adds a full itinerary for IBM's PPC64 A2 embedded core. These cores form the basis for the CPUs in the new IBM BG/Q supercomputer. llvm-svn: 153842
* Belatedly address some code review from Chris.Chandler Carruth2012-04-011-1/+1
| | | | | | | As a side note, I really dislike array_pod_sort... Do we really still care about any STL implementations that get this so wrong? Does libc++? llvm-svn: 153834
* Fix a pretty scary bug I introduced into the always inliner withChandler Carruth2012-04-011-1/+1
| | | | | | | | | | a single missing character. Somehow, this had gone untested. I've added tests for returns-twice logic specifically with the always-inliner that would have caught this, and fixed the bug. Thanks to Matt for the careful review and spotting this!!! =D llvm-svn: 153832
* misched: Add finalizeScheduler to complete the target interface.Andrew Trick2012-04-011-0/+1
| | | | llvm-svn: 153827
* Removing a file that's no longer being used after the recent refactoringsEli Bendersky2012-04-011-388/+0
| | | | llvm-svn: 153825
* Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore.Hal Finkel2012-04-019-107/+140
| | | | | | | | | | | Loads and stores can have different pipeline behavior, especially on embedded chips. This change allows those differences to be expressed. Except for the 440 scheduler, there are no functionality changes. On the 440, the latency adjustment is only by one cycle, and so this probably does not affect much. Nevertheless, it will make a larger difference in the future and this removes a FIXME from the 440 itin. llvm-svn: 153821
* Teach CodeGen's version of computeMaskedBits to understand the range metadata.Rafael Espindola2012-03-315-13/+21
| | | | | | | | This is the CodeGen equivalent of r153747. I tested that there is not noticeable performance difference with any combination of -O0/-O2 /-g when compiling gcc as a single compilation unit. llvm-svn: 153817
* Fix dynamic linking on PPC64.Hal Finkel2012-03-318-35/+126
| | | | | | | | | | | | | | | | | | Dynamic linking on PPC64 has had problems since we had to move the top-down hazard-detection logic post-ra. For dynamic linking to work there needs to be a nop placed after every call. It turns out that it is really hard to guarantee that nothing will be placed in between the call (bl) and the nop during post-ra scheduling. Previous attempts at fixing this by placing logic inside the hazard detector only partially worked. This is now fixed in a different way: call+nop codegen-only instructions. As far as CodeGen is concerned the pair is now a single instruction and cannot be split. This solution works much better than previous attempts. The scoreboard hazard detector is also renamed to be more generic, there is currently no cpu-specific logic in it. llvm-svn: 153816
* Fix a typo reported in IRC by someone reviewing this code.Chandler Carruth2012-03-311-1/+1
| | | | llvm-svn: 153815
* Give the always-inliner its own custom filter. It shouldn't have to payChandler Carruth2012-03-311-20/+63
| | | | | | | | | | | | the very high overhead of the complex inline cost analysis when all it wants to do is detect three patterns which must not be inlined. Comment the code, clean it up, and leave some hints about possible performance improvements if this ever shows up on a profile. Moving this off of the (now more expensive) inline cost analysis is particularly important because we have to run this inliner even at -O0. llvm-svn: 153814
* Remove a bunch of empty, dead, and no-op methods from all of theseChandler Carruth2012-03-314-36/+0
| | | | | | | | | | interfaces. These methods were used in the old inline cost system where there was a persistent cache that had to be updated, invalidated, and cleared. We're now doing more direct computations that don't require this intricate dance. Even if we resume some level of caching, it would almost certainly have a simpler and more narrow interface than this. llvm-svn: 153813
* Initial commit for the rewrite of the inline cost analysis to operateChandler Carruth2012-03-315-621/+971
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on a per-callsite walk of the called function's instructions, in breadth-first order over the potentially reachable set of basic blocks. This is a major shift in how inline cost analysis works to improve the accuracy and rationality of inlining decisions. A brief outline of the algorithm this moves to: - Build a simplification mapping based on the callsite arguments to the function arguments. - Push the entry block onto a worklist of potentially-live basic blocks. - Pop the first block off of the *front* of the worklist (for breadth-first ordering) and walk its instructions using a custom InstVisitor. - For each instruction's operands, re-map them based on the simplification mappings available for the given callsite. - Compute any simplification possible of the instruction after re-mapping, and store that back int othe simplification mapping. - Compute any bonuses, costs, or other impacts of the instruction on the cost metric. - When the terminator is reached, replace any conditional value in the terminator with any simplifications from the mapping we have, and add any successors which are not proven to be dead from these simplifications to the worklist. - Pop the next block off of the front of the worklist, and repeat. - As soon as the cost of inlining exceeds the threshold for the callsite, stop analyzing the function in order to bound cost. The primary goal of this algorithm is to perfectly handle dead code paths. We do not want any code in trivially dead code paths to impact inlining decisions. The previous metric was *extremely* flawed here, and would always subtract the average cost of two successors of a conditional branch when it was proven to become an unconditional branch at the callsite. There was no handling of wildly different costs between the two successors, which would cause inlining when the path actually taken was too large, and no inlining when the path actually taken was trivially simple. There was also no handling of the code *path*, only the immediate successors. These problems vanish completely now. See the added regression tests for the shiny new features -- we skip recursive function calls, SROA-killing instructions, and high cost complex CFG structures when dead at the callsite being analyzed. Switching to this algorithm required refactoring the inline cost interface to accept the actual threshold rather than simply returning a single cost. The resulting interface is pretty bad, and I'm planning to do lots of interface cleanup after this patch. Several other refactorings fell out of this, but I've tried to minimize them for this patch. =/ There is still more cleanup that can be done here. Please point out anything that you see in review. I've worked really hard to try to mirror at least the spirit of all of the previous heuristics in the new model. It's not clear that they are all correct any more, but I wanted to minimize the change in this single patch, it's already a bit ridiculous. One heuristic that is *not* yet mirrored is to allow inlining of functions with a dynamic alloca *if* the caller has a dynamic alloca. I will add this back, but I think the most reasonable way requires changes to the inliner itself rather than just the cost metric, and so I've deferred this for a subsequent patch. The test case is XFAIL-ed until then. As mentioned in the review mail, this seems to make Clang run about 1% to 2% faster in -O0, but makes its binary size grow by just under 4%. I've looked into the 4% growth, and it can be fixed, but requires changes to other parts of the inliner. llvm-svn: 153812
* Internalize: Remove reference of @llvm.noinline, it was replaced with the ↵Benjamin Kramer2012-03-311-1/+0
| | | | | | noinline attribute a long time ago. llvm-svn: 153806
* I noticed in passing that the Metadata getIfExists method was creating a newDuncan Sands2012-03-311-4/+4
| | | | | | node and returning it if one didn't exist. llvm-svn: 153798
* Correctly vectorize powi.Hal Finkel2012-03-311-11/+33
| | | | | | | | The powi intrinsic requires special handling because it always takes a single integer power regardless of the result type. As a result, we can vectorize only if the powers are equal. Fixes PR12364. llvm-svn: 153797
* Select static relocation model if it is jitting.Akira Hatanaka2012-03-311-1/+3
| | | | llvm-svn: 153795
* Add a 2 byte safety margin in offset computations.Jakob Stoklund Olesen2012-03-311-2/+5
| | | | | | | | | | | | ARMConstantIslandPass still has bugs where jump table compression can cause constant pool entries to go out of range. Add a safety margin of 2 bytes when placing constant islands, but use the real max displacement for verification. <rdar://problem/11156595> llvm-svn: 153789
* Add more debugging output to ARMConstantIslandPass.Jakob Stoklund Olesen2012-03-311-2/+16
| | | | llvm-svn: 153788
* Rip out emission of the regIsInRegClass function for the asm printer.Benjamin Kramer2012-03-301-0/+1
| | | | | | It's slow, bloated and completely redundant with MCRegisterClass::contains. llvm-svn: 153782
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