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* Have getCallPreservedMask and getThisCallPreservedMask take aEric Christopher2015-03-1127-51/+75
| | | | | | | MachineFunction argument so that we can grab subtarget specific features off of it. llvm-svn: 231979
* One more getCalleeSavedRegs prototype with nullptr.Eric Christopher2015-03-111-2/+1
| | | | llvm-svn: 231977
* Have getCalleeSavedRegs take a non-null MachineFunction all theEric Christopher2015-03-1116-28/+19
| | | | | | | | time. The target independent code was passing in one all the time and targets weren't checking validity before using. Update a few calls to pass in a MachineFunction where necessary. llvm-svn: 231970
* Constify AArch64CollectLOH.cpp. NFCPete Cooper2015-03-111-7/+7
| | | | llvm-svn: 231969
* [mips][microMIPS] Make usage of NOT16 by code generatorJozef Kolek2015-03-112-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D7748 llvm-svn: 231963
* Put jump tables in unique sections on COFF.Rafael Espindola2015-03-111-0/+25
| | | | | | | | | | | If a function is going in an unique section (because of -ffunction-sections for example), putting a jump table in .rodata will keep .rodata alive and that will keep alive any other function that also has a jump table. Instead, put the jump table in a unique section that is associated with the function. llvm-svn: 231961
* ARM: simplify and extend byval handlingTim Northover2015-03-115-240/+110
| | | | | | | | | | | | | | | | | | | The main issue being fixed here is that APCS targets handling a "byval align N" parameter with N > 4 were miscounting what objects were where on the stack, leading to FrameLowering setting the frame pointer incorrectly and clobbering the stack. But byval handling had grown over many years, and had multiple layers of cruft trying to compensate for each other and calculate padding correctly. This only really needs to be done once, in the HandleByVal function. Elsewhere should just do what it's told by that call. I also stripped out unnecessary APCS/AAPCS distinctions (now that Clang emits byvals with the correct C ABI alignment), which simplified HandleByVal. rdar://20095672 llvm-svn: 231959
* Remove the need to cache the subtarget in the R600 TargetRegisterInfoEric Christopher2015-03-1112-66/+64
| | | | | | classes. llvm-svn: 231954
* Have getRegPressureSetLimit take a MachineFunction so that aEric Christopher2015-03-113-4/+6
| | | | | | we can inspect the subtarget and function when computing values. llvm-svn: 231951
* InstCombine: Don't fold call bitcast into args if callee is byvalDavid Majnemer2015-03-111-1/+4
| | | | | | | This fixes a bug reported here: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150309/265341.html llvm-svn: 231948
* Updated with list of possible improvements we are tracking internallyKit Barton2015-03-112-0/+40
| | | | llvm-svn: 231946
* Add the "vbroadcasti128" instruction back.Juergen Ributzka2015-03-111-0/+5
| | | | | | | | | | This is a follow-up to r231182. This adds the "vbroadcasti128" instruction back, but without the intrinsic mapping. Also add a test to check the instriction encoding. This is related to rdar://problem/18742778. llvm-svn: 231945
* Make NaCl's use of .init_array for static constructors match LinuxDerek Schuff2015-03-113-6/+7
| | | | | | | | | | | | Summary: The generic ELF TargetObjectFile defaults to .ctors, but Linux's defaults to .init_array by calling InitializeELF with the value of UseInitArray from TargetMachine. Make NaCl's behavior match. Reviewers: jvoung Differential Revision: http://reviews.llvm.org/D8240 llvm-svn: 231934
* Wrap in __MINGW32__ to avoid warnings from msvc.Benjamin Kramer2015-03-111-1/+3
| | | | llvm-svn: 231933
* Add missing namespace specifier for MSVC.Benjamin Kramer2015-03-111-1/+1
| | | | llvm-svn: 231930
* RtlCaptureContext is absent from the mingw32 headers, provide a prototype.Benjamin Kramer2015-03-111-1/+4
| | | | llvm-svn: 231929
* Inliner should not add callgraph edges for intrinsic calls (PR22857)Sanjay Patel2015-03-111-1/+8
| | | | | | | | | | | | The CallGraphNode function "addCalledFunction()" asserts that edges are not to intrinsics. This patch makes sure that the Inliner does not add such an edge to the callgraph. Fix for clang crash by assertion: https://llvm.org/bugs/show_bug.cgi?id=22857 Differential Revision: http://reviews.llvm.org/D8231 llvm-svn: 231927
* AVX-512: Added SKX forms of shift instructions.Elena Demikhovsky2015-03-112-39/+142
| | | | | | | Added rotation instructions, encoding only. Added encoding tests for all these forms. llvm-svn: 231916
* Fix another verifier crash where a GC intrinsic would look at the internals ↵Owen Anderson2015-03-111-0/+5
| | | | | | | | | | | of another intrinsic in order to verify itself. This causes a crash if the referenced intrinsic was malformed. In this case, we would already have reported an error on the referenced intrinsic, but then crashed on the second one when it tried to introspect the first without error checking. llvm-svn: 231910
* Don't print labels that on ELF are never used.Rafael Espindola2015-03-111-16/+14
| | | | llvm-svn: 231904
* InstrProf: Teach llvm-cov to handle universal binaries when given -archJustin Bogner2015-03-112-8/+31
| | | | llvm-svn: 231902
* Print section start labels when first switching to the section.Rafael Espindola2015-03-113-45/+9
| | | | | | | This is less brittle and avoids polluting the start of the file with every debug section. llvm-svn: 231898
* [Orc][MCJIT][RuntimeDyld] Re-apply r231726 and r231724 with fix suggested byLang Hames2015-03-115-57/+46
| | | | | | Dave Blaikie. Thanks Dave! llvm-svn: 231896
* Fix Value dangling reference debug outputAndrew Kaylor2015-03-102-7/+5
| | | | llvm-svn: 231889
* Have TargetRegisterInfo::getLargestLegalSuperClass take aEric Christopher2015-03-1012-22/+30
| | | | | | | MachineFunction argument so that it can look up the subtarget rather than using a cached one in some Targets. llvm-svn: 231888
* Remove subtarget dependence from HexagonRegisterInfo.Eric Christopher2015-03-103-14/+7
| | | | llvm-svn: 231887
* Remove dead code.Eric Christopher2015-03-102-25/+0
| | | | llvm-svn: 231883
* Add missing section symbol to COFF's .debug_types.dwo.Rafael Espindola2015-03-101-1/+1
| | | | | | | | | Should bring the cygwin bots back. I added a triple to the test that was failing so that it would have failed on Linux. llvm-svn: 231882
* If a conditional branch jumps to the same target, remove the conditionPhilip Reames2015-03-101-0/+9
| | | | | | | | | | | | Given that large parts of inst combine is restricted to instructions which have one use, getting rid of a use on the condition can help the effectiveness of the optimizer. Also, it allows the condition to potentially be deleted by instcombine rather than waiting for another pass. I noticed this completely by accident in another test case. It's not anything that actually came from a real workload. p.s. We should probably do the same thing for switch instructions. Differential Revision: http://reviews.llvm.org/D8220 llvm-svn: 231881
* Emit correct linkage-name attribute based on DWARF version.Paul Robinson2015-03-103-13/+15
| | | | | | | | | | There are still 4 tests that check for DW_AT_MIPS_linkage_name, because they specify DWARF 2 or 3 in the module metadata. So, I didn't create an explicit version-based test for the attribute. Differential Revision: http://reviews.llvm.org/D8227 llvm-svn: 231880
* Infer known bits from dominating conditionsPhilip Reames2015-03-101-0/+212
| | | | | | | | | | | | | | | | | This patch adds limited support in ValueTracking for inferring known bits of a value from conditional expressions which must be true to reach the instruction we're trying to optimize. At this time, the feature is off by default. Once landed, I'm hoping for feedback from others on both profitability and compile time impact. Forms of conditional value propagation have been tried in LLVM before and have failed due to compile time problems. In an attempt to side step that, this patch only considers conditions where the edge leaving the branch dominates the context instruction. It does not attempt full dataflow. Even with that restriction, it handles many interesting cases: * Early exits from functions * Early exits from loops (for context instructions in the loop and after the check) * Conditions which control entry into loops, including multi-version loops (such as those produced during vectorization, IRCE, loop unswitch, etc..) Possible applications include optimizing using information provided by constructs such as: preconditions, assumptions, null checks, & range checks. This patch implements two approaches to the problem that need further benchmarking. Approach 1 is to directly walk the dominator tree looking for interesting conditions. Approach 2 is to inspect other uses of the value being queried for interesting comparisons. From initial benchmarking, it appears that Approach 2 is faster than Approach 1, but this needs to be further validated. Differential Revision: http://reviews.llvm.org/D7708 llvm-svn: 231879
* Remove the use of the subtarget in MCCodeEmitter creation andEric Christopher2015-03-1023-57/+22
| | | | | | | update all ports accordingly. Required a couple of small rewrites in handling subtarget features during creation in PPC. llvm-svn: 231861
* Create symbols marking the start of a section earlier.Rafael Espindola2015-03-106-102/+122
| | | | | | | | | This lets us pass the symbol to the constructor and avoid the mutable field. This also opens the way for outputting the symbol only when needed, instead of outputting them at the start of the file. llvm-svn: 231859
* Remove createAMDGPUMCCodeEmitter and instead just register the correctEric Christopher2015-03-103-16/+7
| | | | | | | MCCodeEmitter creation routine based on TargetMachine since the only 64-bit R600 gpus are part of the GCN target. llvm-svn: 231856
* [CodeGenPrepare] Refine the cost model provided by the promotion helper.Quentin Colombet2015-03-101-61/+77
| | | | | | | | | | | | | | | | | - Use TargetLowering to check for the actual cost of each extension. - Provide a factorized method to check for the cost of an extension: TargetLowering::isExtFree. - Provide a virtual method TargetLowering::isExtFreeImpl for targets to be able to tune the cost of non-free extensions. This refactoring offers a better granularity to model what really happens on different targets. No performance changes and very few code differences. Part of <rdar://problem/19267165> llvm-svn: 231855
* [LoopAccesses] Add debug message to indicate the result of the analysisAdam Nemet2015-03-101-4/+7
| | | | | | | | | | The debug message was pretty confusing here. It only reported the situation with memchecks without the result of the dependence analysis. Now it prints whether the loop is safe from the POV of the dependence analysis and if yes, whether we need memchecks. llvm-svn: 231854
* Move a non-trivial virtual function out of line.Rafael Espindola2015-03-101-0/+11
| | | | llvm-svn: 231853
* [Hexagon] Adding frame index + add load/store patterns.Colin LeMahieu2015-03-102-5/+20
| | | | llvm-svn: 231850
* clang-format code that is about to change.Rafael Espindola2015-03-102-283/+219
| | | | llvm-svn: 231848
* [Hexagon] Simplifying deallocret definitions.Colin LeMahieu2015-03-101-12/+3
| | | | llvm-svn: 231847
* [Hexagon] Separating InstHexagon from OpcodeHexagon.Colin LeMahieu2015-03-103-47/+57
| | | | llvm-svn: 231844
* Add support for part-word atomics for PPCNemanja Ivanovic2015-03-107-67/+141
| | | | | | http://reviews.llvm.org/D8090#inline-67337 llvm-svn: 231843
* [AArch64] Avoid going through GPRs for across-vector instructions.Ahmed Bougacha2015-03-103-119/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds new node types for each intrinsic. For instance, for addv, we have AArch64ISD::UADDV, such that: (v4i32 (uaddv ...)) is the same as (v4i32 (scalar_to_vector (i32 (int_aarch64_neon_uaddv ...)))) that is, (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (i32 (int_aarch64_neon_uaddv ...)), ssub) In a combine, we transform all such across-vector-lanes intrinsics to: (i32 (extract_vector_elt (uaddv ...), 0)) This has one big advantage: by making the extract_element explicit, we enable the existing patterns for lane-aware instructions to fire. This lets us avoid needlessly going through the GPRs. Consider: uint32x4_t test_mul(uint32x4_t a, uint32x4_t b) { return vmulq_n_u32(a, vaddvq_u32(b)); } We now generate: addv.4s s1, v1 mul.4s v0, v0, v1[0] instead of the previous: addv.4s s1, v1 fmov w8, s1 dup.4s v1, w8 mul.4s v0, v1, v0 rdar://20044838 llvm-svn: 231840
* [AArch64] Remove integer INSvi*lane patterns. NFCI.Ahmed Bougacha2015-03-101-4/+0
| | | | | | | | | | | | | | | | | | | | | | | Most are redundant, and they never seem to fire. The V128 integer patterns already exist in the INS multiclass. The duplicates only fire when the vector index type isn't i64, because they accept "imm" instead of an explicit "i64", as the instruction definition patterns do. TLI::getVectorIdxTy is i64 on AArch64, so this should never happen. Also, one of them had a typo: for i64, INSvi32lane was used. I noticed because I mistakenly used an explicit i32 as the idx type, and got ins.s for an i64 vector_insert. The V64 patterns also don't seem to ever fire, as V64 vector extract/insert are legalized to V128. The equivalent float patterns are unique and useful, so keep them. No functional change intended; none exhibited on the LIT and LNT tests. llvm-svn: 231838
* Don't evaluate rend() on every iteration of the loop.Chad Rosier2015-03-101-1/+3
| | | | llvm-svn: 231837
* LoopAccessAnalysis: Silence -Wreturn-type diagnostic from GCCDavid Majnemer2015-03-101-0/+3
| | | | llvm-svn: 231836
* Don't use LLVM_LIBRARY_VISIBILITY in cpp files.Benjamin Kramer2015-03-101-1/+3
| | | | llvm-svn: 231831
* [AsmPrinter][TLOF] Reintroduce AArch64 testBruno Cardoso Lopes2015-03-101-11/+12
| | | | | | | | | | | | Follow up from r231505. Fix the non-determinism by using a MapVector and reintroduce the AArch64 testcase. Defer deleting the got candidates up to the end and remove them in a bulk, avoiding linear time removal of each element. Thanks to Renato Golin for trying it out on other platforms. llvm-svn: 231830
* [Hexagon] Adding nodes for PIC support.Colin LeMahieu2015-03-102-9/+55
| | | | llvm-svn: 231829
* [Hexagon] Adding DuplexInst instruction format and duplex class defs.Colin LeMahieu2015-03-103-3/+116
| | | | llvm-svn: 231828
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