| Commit message (Collapse) | Author | Age | Files | Lines |
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the file now, however the relocated address is currently wrong. Fixing
that will require some deep pondering.
llvm-svn: 30207
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in addition to immediate operands.
llvm-svn: 30205
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safe for later allocation. This fixes McCat/18-imp with llc-beta.
llvm-svn: 30204
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llvm-svn: 30198
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of unallocatable registers, just because an alias is allocatable. We were
picking registers like SIL just because ESI was being used.
llvm-svn: 30197
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llvm-svn: 30191
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llvm-svn: 30190
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llvm-svn: 30189
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llvm-svn: 30188
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fix select.ll
llvm-svn: 30186
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llvm-svn: 30178
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llvm-svn: 30177
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llvm-svn: 30173
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shuffle V1, <undef>, <undef, undef, 4, 5>
- Fix some suspicious logic into LowerVectorShuffle that cause less than
optimal code by failing to identify MOVL (move to lowest element of a
vector).
llvm-svn: 30171
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2. Protect and outline createTargetAsmInfo.
3. Misc. kruft.
llvm-svn: 30169
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llvm-svn: 30168
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reduce amount of stack space used at runtime.
llvm-svn: 30167
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llvm-svn: 30165
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host, it should be affected by the target. Allow the command line option to
override in either case.
llvm-svn: 30164
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llvm-svn: 30162
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llvm-svn: 30161
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For Transforms/TailDup/if-tail-dup.ll, f.e., it produces:
_foo:
movl 8(%esp), %eax
movl 4(%esp), %ecx
testl $1, %ecx
je LBB1_2 #cond_next
LBB1_1: #cond_true
movl $1, (%eax)
LBB1_2: #cond_next
testl $2, %ecx
je LBB1_4 #cond_next10
LBB1_3: #cond_true6
movl $1, 4(%eax)
LBB1_4: #cond_next10
testl $4, %ecx
je LBB1_6 #cond_next18
LBB1_5: #cond_true14
movl $1, 8(%eax)
LBB1_6: #cond_next18
testl $8, %ecx
je LBB1_8 #return
LBB1_7: #cond_true22
movl $1, 12(%eax)
ret
LBB1_8: #return
ret
instead of:
_foo:
movl 4(%esp), %eax
testl $2, %eax
sete %cl
movl 8(%esp), %edx
testl $1, %eax
je LBB1_2 #cond_next
LBB1_1: #cond_true
movl $1, (%edx)
testb %cl, %cl
jne LBB1_4 #cond_next10
jmp LBB1_3 #cond_true6
LBB1_2: #cond_next
testb %cl, %cl
jne LBB1_4 #cond_next10
LBB1_3: #cond_true6
movl $1, 4(%edx)
testl $4, %eax
je LBB1_6 #cond_next18
jmp LBB1_5 #cond_true14
LBB1_4: #cond_next10
testl $4, %eax
je LBB1_6 #cond_next18
LBB1_5: #cond_true14
movl $1, 8(%edx)
testl $8, %eax
je LBB1_8 #return
jmp LBB1_7 #cond_true22
LBB1_6: #cond_next18
testl $8, %eax
je LBB1_8 #return
LBB1_7: #cond_true22
movl $1, 12(%edx)
ret
LBB1_8: #return
ret
llvm-svn: 30158
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using test, which provides nice simplifications like:
- movl %edi, %ecx
- andl $2, %ecx
- cmpl $0, %ecx
+ testl $2, %edi
je LBB1_11 #cond_next90
There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.
llvm-svn: 30156
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llvm-svn: 30155
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llvm-svn: 30152
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llvm-svn: 30151
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llvm-svn: 30149
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llvm-svn: 30146
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too many phi operands when lowering a switch to branches in some cases.
llvm-svn: 30142
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llvm-svn: 30140
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llvm-svn: 30135
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llvm-svn: 30134
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llvm-svn: 30131
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llvm-svn: 30127
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llvm-svn: 30126
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llvm-svn: 30125
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llvm-svn: 30122
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recently
llvm-svn: 30121
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llvm-svn: 30118
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llvm-svn: 30117
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lowerinvoke regtests.
llvm-svn: 30115
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llvm-svn: 30114
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llvm-svn: 30113
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llvm-svn: 30112
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adds assertions that check to make sure every operand gets emitted.
llvm-svn: 30110
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def operand or a use operand.
llvm-svn: 30109
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actually *removes* one of the operands, instead of just assigning both operands
the same register. This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.
Changing this also gets rid of a bunch of hacky code in various places.
This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.
llvm-svn: 30108
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llvm-svn: 30107
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llvm-svn: 30103
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llvm-svn: 30102
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