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* TargetTransformInfo: address calculation parameter for gather/scatherArnold Schwaighofer2013-07-124-8/+64
| | | | | | | | | | | Address calculation for gather/scather in vectorized code can incur a significant cost making vectorization unbeneficial. Add infrastructure to add cost. Tests and cost model for targets will be in follow-up commits. radar://14351991 llvm-svn: 186187
* R600/SI: Add support for f64 kernel argumentsTom Stellard2013-07-121-1/+1
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186182
* R600/SI: Implement select and compares for SITom Stellard2013-07-121-6/+18
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186181
* R600/SI: Add fsqrt pattern for SITom Stellard2013-07-121-2/+6
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186180
* R600/SI: Add double precision fsub pattern for SITom Stellard2013-07-122-3/+29
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186179
* R600/SI: SI support for 64bit ConstantFPTom Stellard2013-07-122-0/+19
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186178
* R600/SI: Add initial double precision support for SITom Stellard2013-07-123-1/+36
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186177
* X86: Shrink certain forms of movsx.Benjamin Kramer2013-07-121-0/+35
| | | | | | | | | | | | In particular: movsbw %al, %ax --> cbtw movswl %ax, %eax --> cwtl movslq %eax, %rax --> cltq According to Intel's manual those have the same performance characteristics but come with a smaller encoding. llvm-svn: 186174
* X86: fold SSE2/AVX2 logical shift by immediate amount into zero vector when ↵Stephen Lin2013-07-121-0/+38
| | | | | | | | possible Patch by Andrea Di Biagio llvm-svn: 186165
* Don't reject an empty archive.Rafael Espindola2013-07-121-4/+6
| | | | llvm-svn: 186159
* Revert "indvars: Improve LFTR by eliminating truncation when comparingChandler Carruth2013-07-121-23/+4
| | | | | | | | | | | | | | | | | | | against a constant." This reverts commit r186107. It didn't handle wrapping arithmetic in the loop correctly and thus caused the following C program to count from 0 to UINT64_MAX instead of from 0 to 255 as intended: #include <stdio.h> int main() { unsigned char first = 0, last = 255; do { printf("%d\n", first); } while (first++ != last); } Full test case and instructions to reproduce with just the -indvars pass sent to the original review thread rather than to r186107's commit. llvm-svn: 186152
* Add support for Mips break and syscall insructions. The corresponding test ↵Vladimir Medic2013-07-122-0/+49
| | | | | | cases are added. llvm-svn: 186151
* [SystemZ] Optimize sign-extends of vector setccsRichard Sandiford2013-07-121-0/+9
| | | | | | | | | | | | | Normal (sext (setcc ...)) sequences are optimised into (select_cc ..., -1, 0) by DAGCombiner::visitSIGN_EXTEND. However, this is deliberately not done for vectors, and after vector type legalization we have (sext_inreg (setcc ...)) instead. I wondered about trying to extend DAGCombiner to handle this case too, but it seemed to be a loss on some other targets I tried, even those for which SETCC isn't "legal" and SELECT_CC is. llvm-svn: 186149
* [SystemZ] Fix parsing of inline asm registersRichard Sandiford2013-07-124-8/+49
| | | | | | | | | | | | GPR and FPR constraints like "{r2}" and "{f2}" weren't handled correctly because the name-to-regno mapping depends on the value type and (because of that) the internal names in RegStrings are not the same as the AsmName. CC constraints like "{cc}" didn't work either because there was no associated register class. llvm-svn: 186148
* [SystemZ] Improve spilling of LGDR and LDGRRichard Sandiford2013-07-121-1/+23
| | | | | | | If the source of these instructions is spilled we should load the destination. If the destination is spilled we should store the source. llvm-svn: 186147
* Stylistic change.Shuxin Yang2013-07-121-2/+2
| | | | | | Thank Nick for figuring out these problems. llvm-svn: 186146
* SLPVectorizer: Sink and enable CSE for ExtractElements.Nadav Rotem2013-07-121-11/+25
| | | | llvm-svn: 186145
* Target/X86: Add explicit Win64 and System V/x86-64 calling conventions.Charles Davis2013-07-128-26/+55
| | | | | | | | | | | | | | | Summary: This patch adds explicit calling convention types for the Win64 and System V/x86-64 ABIs. This allows code to override the default, and use the Win64 convention on a target that wants to use SysV (and vice-versa). This is needed to implement the `ms_abi` and `sysv_abi` GNU attributes. Reviewers: CC: llvm-svn: 186144
* Windows/TimeValue.inc: Mute prefixed '0' on %d to emulate %e.NAKAMURA Takumi2013-07-121-0/+5
| | | | | | It fixes compatibility in llvm/test/Object/archive-toc.test. llvm-svn: 186142
* PEI: refactor replaceFrameIndices(MF) to call replaceFrameIndices(BB).Manman Ren2013-07-122-81/+87
| | | | | | | replaceFrameIndices(MF) will iterate over the BBs and call replaceFrameIndices(BB). No functionality change. llvm-svn: 186141
* SLPVectorize: Replace the code that checks for vectorization candidates in ↵Nadav Rotem2013-07-121-25/+22
| | | | | | | | successor blocks with code that scans PHINodes. Before we could vectorize PHINodes scanning successors was a good way of finding candidates. Now we can vectorize the phinodes which is simpler. llvm-svn: 186139
* Remove an argument that we dont use anymore.Nadav Rotem2013-07-111-15/+12
| | | | llvm-svn: 186116
* PPC: Add some missing V_SET0 patternsHal Finkel2013-07-111-2/+15
| | | | | | | | | | We had patterns to match v4i32 immAllZerosV -> V_SET0, but not patterns for v8i16 (which occurs in the test case) or v16i8. The same was true for V_SETALLONES (so I added the associated patterns for those as well). Another bug found by llvm-stress. llvm-svn: 186108
* indvars: Improve LFTR by eliminating truncation when comparing against a ↵Andrew Trick2013-07-111-4/+23
| | | | | | | | | | | | | | | | | constant. Patch by Michele Scandale! Adds a special handling of the case where, during the loop exit condition rewriting, the exit value is a constant of bitwidth lower than the type of the induction variable: instead of introducing a trunc operation in order to match correctly the operand types, it allows to convert the constant value to an equivalent constant, depending on the initial value of the induction variable and the trip count, in order have an equivalent comparison between the induction variable and the new constant. llvm-svn: 186107
* PPCDAGToDAGISel::isRunOfOnes should return false on zeroHal Finkel2013-07-111-1/+4
| | | | | | | | | | | | This fixes a bug (found by csmith) at -O0 where we attempt to create a RLWIMI with an out-of-range operand. Most uses of the isRunOfOnes function are guarded by a condition that the value is not zero. This was not true in two places, and in both places a zero input would result in an out-of-rage MB value (= 32). To fix this, isRunOfOnes returns false on a zero input (and I've remove one now-redundant guard). llvm-svn: 186101
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-119-23/+23
| | | | | | size. llvm-svn: 186098
* Add back code for supporting old mingw versions. Should bring the bots back.Rafael Espindola2013-07-111-3/+13
| | | | llvm-svn: 186096
* Don't use a potentially expensive shift if all we want is one set bit.Benjamin Kramer2013-07-114-6/+6
| | | | | | No functionality change. llvm-svn: 186095
* Looks like some versions of mingw don't have errno_t. Use int.Rafael Espindola2013-07-111-1/+1
| | | | llvm-svn: 186092
* Use move semantics if possible to construct ConstantRanges.Benjamin Kramer2013-07-111-5/+6
| | | | | | | Arithmetic on ConstantRanges creates a lot of large temporary APInts that benefit from move semantics. llvm-svn: 186091
* Fix a FIXME about the format and add a test.Rafael Espindola2013-07-112-26/+16
| | | | | | | While at it, use strftime on Unix too and use the thread safe versions of localtime. llvm-svn: 186090
* LoopVectorize: Vectorize all accesses in address space zero with unit strideArnold Schwaighofer2013-07-111-8/+16
| | | | | | | | | | | We can vectorize them because in the case where we wrap in the address space the unvectorized code would have had to access a pointer value of zero which is undefined behavior in address space zero according to the LLVM IR semantics. (Thank you Duncan, for pointing this out to me). Fixes PR16592. llvm-svn: 186088
* Reduce the number of indirections in the attributes implementation.Benjamin Kramer2013-07-112-178/+131
| | | | | | | | | | | - Coallocate entires for AttributeSetImpls and Nodes after the class itself. - Remove mutable iterators from immutable classes. - Remove unused context field from AttributeImpl. - Derive Enum/Align/String attribute implementations from AttributeImpl instead of having a whole new inheritance tree for them. - Derive AlignAttributeImpl from EnumAttributeImpl. llvm-svn: 186075
* [SystemZ] Use zeroing form of RISBG for shift-and-AND sequencesRichard Sandiford2013-07-111-5/+66
| | | | | | Extend r186072 to handle shifts and ANDs. llvm-svn: 186073
* [SystemZ] Use zeroing form of RISBG for some AND sequencesRichard Sandiford2013-07-111-1/+118
| | | | | | | | | | | | RISBG can handle some ANDs for which no AND IMMEDIATE exists. It also acts as a three-operand AND for some cases where an AND IMMEDIATE could be used instead. It might be worth adding a pass to replace RISBG with AND IMMEDIATE in cases where the register operands end up being the same and where AND IMMEDIATE is smaller. llvm-svn: 186072
* [SystemZ] Allow 8-bit operands to RISBGRichard Sandiford2013-07-111-2/+1
| | | | | | | | | | | | RISBG has three 8-bit operands (I3, I4 and I5). I'd originally restricted all three to 6 bits, since that's the only range we intended to use at the time. However, the top bit of I4 acts as a "zero" flag for RISBG, while the top bit of I3 acts as a "test" flag for RNSBG & co. This patch therefore allows them to have the full 8-bit range. I've left the fifth operand as a 6-bit value for now since the upper 2 bits have no defined meaning. llvm-svn: 186070
* TryToSimplifyUncondBranchFromEmptyBlock was checking that any commonDuncan Sands2013-07-111-23/+147
| | | | | | | | | | predecessors of the two blocks it is attempting to merge supply the same incoming values to any phi in the successor block. This change allows merging in the case where there is one or more incoming values that are undef. The undef values are rewritten to match the non-undef value that flows from the other edge. Patch by Mark Lacey. llvm-svn: 186069
* Initialize AsmPrinter::MF in the constructorHal Finkel2013-07-111-1/+1
| | | | | | | | | | | MF is normally initialized in AsmPrinter::SetupMachineFunction, but if the file contains only globals (no functions), then we need this to be initialized because, when encountering an error, lowerConstant() references it. This should fix the non-deterministic failures of test/CodeGen/X86/nonconst-static-iv.ll, etc. llvm-svn: 186068
* RegScavenger should not exclude undef usesHal Finkel2013-07-111-1/+1
| | | | | | | | | | | | | | When computing currently-live registers, the register scavenger excludes undef uses. As a result, undef uses are ignored when computing the restore points of registers spilled into the emergency slots. While the register scavenger normally excludes from consideration, when scavenging, registers used by the current instruction, we need to not exclude undef uses. Otherwise, we might end up requiring more emergency spill slots than we have (in the case where the undef use *is* the currently-spilled register). Another bug found by llvm-stress. llvm-svn: 186067
* Fix indentation. No functional change.Craig Topper2013-07-111-8/+8
| | | | llvm-svn: 186065
* Fix a warning.Nadav Rotem2013-07-111-2/+1
| | | | llvm-svn: 186064
* SLPVectorizer: refactor the code that places extracts. Place the code that ↵Nadav Rotem2013-07-111-41/+131
| | | | | | decides where to put extracts in the build-tree phase. This allows us to take the cost of the extracts into account. llvm-svn: 186058
* Teach TailRecursionElimination to handle certain cases of nocapture escaping ↵Michael Gottesman2013-07-111-64/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | allocas. Without the changes introduced into this patch, if TRE saw any allocas at all, TRE would not perform TRE *or* mark callsites with the tail marker. Because TRE runs after mem2reg, this inadequacy is not a death sentence. But given a callsite A without escaping alloca argument, A may not be able to have the tail marker placed on it due to a separate callsite B having a write-back parameter passed in via an argument with the nocapture attribute. Assume that B is the only other callsite besides A and B only has nocapture escaping alloca arguments (*NOTE* B may have other arguments that are not passed allocas). In this case not marking A with the tail marker is unnecessarily conservative since: 1. By assumption A has no escaping alloca arguments itself so it can not access the caller's stack via its arguments. 2. Since all of B's escaping alloca arguments are passed as parameters with the nocapture attribute, we know that B does not stash said escaping allocas in a manner that outlives B itself and thus could be accessed indirectly by A. With the changes introduced by this patch: 1. If we see any escaping allocas passed as a capturing argument, we do nothing and bail early. 2. If we do not see any escaping allocas passed as captured arguments but we do see escaping allocas passed as nocapture arguments: i. We do not perform TRE to avoid PR962 since the code generator produces significantly worse code for the dynamic allocas that would be created by the TRE algorithm. ii. If we do not return twice, mark call sites without escaping allocas with the tail marker. *NOTE* This excludes functions with escaping nocapture allocas. 3. If we do not see any escaping allocas at all (whether captured or not): i. If we do not have usage of setjmp, mark all callsites with the tail marker. ii. If there are no dynamic/variable sized allocas in the function, attempt to perform TRE on all callsites in the function. Based off of a patch by Nick Lewycky. rdar://14324281. llvm-svn: 186057
* Don't assert if we can't constant fold extract/insertvalueHal Finkel2013-07-101-8/+21
| | | | | | | | | | | | | | | A non-constant-foldable static initializer expression containing insertvalue or extractvalue had been causing an assert: Constants.cpp:1971: Assertion `FC && "ExtractValue constant expr couldn't be folded!"' failed. Now we report a more-sensible "Unsupported expression in static initializer" error instead. Fixes PR15417. llvm-svn: 186044
* Find the symbol table on archives created on OS X.Rafael Espindola2013-07-101-3/+14
| | | | llvm-svn: 186041
* Put ELF COMDAT relocations into the relevant COMDAT group.Tim Northover2013-07-101-2/+9
| | | | | | | | Patch from Игорь Пашев (I do hope we support utf-8 commit messages; I also hope he'll forgive me for transliterating it as Igor Pashev in case things go horribly wrong). llvm-svn: 186034
* Remove trailing whitespacStephen Lin2013-07-101-2/+2
| | | | llvm-svn: 186032
* Don't crash in 'llvm -s' when an archive has no symtab.Rafael Espindola2013-07-101-1/+7
| | | | llvm-svn: 186029
* [objc-arc] Changed 'mode: c++' => 'C++' at Nick Lewycky's suggestion. Also ↵Michael Gottesman2013-07-107-7/+7
| | | | | | removed unnecessary mode: c++ lines from .cpp files. llvm-svn: 186026
* MemoryBuffer::getFile handles zero sized files, no need to duplicate the test.Rafael Espindola2013-07-101-21/+2
| | | | llvm-svn: 186018
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