summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* ARM disassembler was erroneously accepting an invalid RSC instruction.Johnny Chen2011-04-051-0/+6
| | | | | | | | Added checks for regs which should not be 15. rdar://problem/9237734 llvm-svn: 128945
* remove postdom frontiers, because it is dead. Forward dom frontiers areChris Lattner2011-04-052-52/+0
| | | | | | still used by RegionInfo :( llvm-svn: 128943
* ARM disassembler was erroneously accepting an invalid LSL instruction.Johnny Chen2011-04-051-0/+4
| | | | | | | | | For register-controlled shifts, we should check that the encoding constraint Inst{7} = 0 and Inst{4} = 1 is satisfied. rdar://problem/9237693 llvm-svn: 128941
* Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as ↵Owen Anderson2011-04-053-80/+76
| | | | | | doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions. llvm-svn: 128940
* Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy.Jakob Stoklund Olesen2011-04-052-0/+14
| | | | llvm-svn: 128935
* Refactor.Devang Patel2011-04-052-15/+21
| | | | llvm-svn: 128929
* Add an assertion instead of crashing when the scavenger goes past the endBob Wilson2011-04-051-1/+2
| | | | | | of a basic block. llvm-svn: 128925
* Fix typos. Adjust some whitespace for style. No functionality change.Nick Lewycky2011-04-052-14/+14
| | | | llvm-svn: 128924
* The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.Johnny Chen2011-04-051-7/+19
| | | | | | | | Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change. rdar://problem/9236873 llvm-svn: 128922
* Add support for detection of Intel SandyBridge.Roman Divacky2011-04-051-0/+2
| | | | llvm-svn: 128920
* When dead code elimination removes all but one use, try to fold the single ↵Jakob Stoklund Olesen2011-04-052-0/+55
| | | | | | | | def into the remaining use. Rematerialization can leave single-use loads behind that we might as well fold whenever possible. llvm-svn: 128918
* Do not emit empty name.Devang Patel2011-04-051-1/+2
| | | | llvm-svn: 128914
* ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.Johnny Chen2011-04-051-2/+10
| | | | llvm-svn: 128913
* Added *hidden* flags -print-options and -print-all-options soAndrew Trick2011-04-051-26/+150
| | | | | | | | | | | | | | | | | | | developers can see if their driver changed any cl::Option's. The current implementation isn't perfect but handles most kinds of options. This is nice to have when decomposing the stages of compilation and moving between different drivers. It's also a good sanity check when comparing results produced by different command line invocations that are expected to produce the comparable results. Note: This is not an attempt to prolong the life of cl::Option. On the contrary, it's a placeholder for a feature that must exist when cl::Option is replaced by a more appropriate framework. A new framework needs: a central option registry, dynamic name lookup, non-global containers of option values (e.g. per-module, per-function), *and* the ability to print options values and their defaults at any point during compilation. llvm-svn: 128910
* An MCDisassembler has the option to not implementShantonu Sen2011-04-051-2/+4
| | | | | | | | | | getEDInfo(), in which case this code would dereference NULL. EDInst can already handle NULL info, so avoid the dereference and pass NULL through. Reviewed by Sean Callanan llvm-svn: 128904
* Make second source operand of LDRD pre/post explicit.Jim Grosbach2011-04-052-8/+28
| | | | | | Finish what r128736 started. llvm-svn: 128903
* Constants with multiple encodings (ARM):Johnny Chen2011-04-051-2/+3
| | | | | | | | | | An alternative syntax is available for a modified immediate constant that permits the programmer to specify the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where: <byte> is the numeric value of abcdefgh, in the range 0-255 <rot> is twice the numeric value of rotation, an even number in the range 0-30. llvm-svn: 128897
* Check for invalid register encodings for UMAAL and friends where:Johnny Chen2011-04-051-2/+49
| | | | | | | | | if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; if dHi == dLo then UNPREDICTABLE; rdar://problem/9230202 llvm-svn: 128895
* Convert ADCS and SBCS instructions into pseudos that are expanded to the ↵Owen Anderson2011-04-052-41/+56
| | | | | | ADC/ABC with the appropriate S-bit input value. llvm-svn: 128892
* Ensure all defs referring to a virtual register are marked dead by ↵Jakob Stoklund Olesen2011-04-051-7/+2
| | | | | | | | | | | | addRegisterDead(). There can be multiple defs for a single virtual register when they are defining sub-registers. The missing <dead> flag was stopping the inline spiller from eliminating dead code after rematerialization. llvm-svn: 128888
* Print visibility info for external variables.Rafael Espindola2011-04-051-10/+12
| | | | llvm-svn: 128887
* Use std::unique instead of a SmallPtrSet to ensure unique instructions in ↵Jakob Stoklund Olesen2011-04-052-54/+26
| | | | | | | | | | | UseSlots. This allows us to always keep the smaller slot for an instruction which is what we want when a register has early clobber defines. Drop the UsingInstrs set and the UsingBlocks map. They are no longer needed. llvm-svn: 128886
* InstCombine optimizes gep(bitcast(x)) even when the bitcasts casts away addressNadav Rotem2011-04-051-8/+11
| | | | | | | space info. We crash with an assert in this case. This change checks that the address space of the bitcasted pointer is the same as the gep ptr. llvm-svn: 128884
* Stop precomputing last split points, query the SplitAnalysis cache on demand.Jakob Stoklund Olesen2011-04-053-21/+17
| | | | llvm-svn: 128875
* Cache the fairly expensive last split point computation and provide a fastJakob Stoklund Olesen2011-04-052-14/+54
| | | | | | | | | inlined path for the common case. Most basic blocks don't contain a call that may throw, so the last split point os simply the first terminator. llvm-svn: 128874
* Revamp the SjLj "dispatch setup" intrinsic.Bill Wendling2011-04-054-13/+10
| | | | | | | | | | | | It needed to be moved closer to the setjmp statement, because the code directly after the setjmp needs to know about values that are on the stack. Also, the 'bitcast' of the function context was causing a dead load. This wouldn't be too horrible, except that at -O0 it wasn't optimized out, and because it wasn't using the correct base pointer (if there is a VLA), it would try to access a value from a garbage address. <rdar://problem/9130540> llvm-svn: 128873
* Just use BL all the time. It's safer that way.Eric Christopher2011-04-051-9/+1
| | | | | | Fixes rdar://9184526 llvm-svn: 128869
* Revert 123704; it broke threaded LLVM.Stuart Hastings2011-04-051-9/+15
| | | | llvm-svn: 128868
* Fix SRS/SRSW encoding bits.Johnny Chen2011-04-051-0/+4
| | | | | | | | | rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with http://llvm.org/viewvc/llvm-project?view=rev&revision=128859. llvm-svn: 128864
* A8.6.105 MULJohnny Chen2011-04-041-1/+3
| | | | | | | | Inst{15-12} should be specified as 0b0000. rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL llvm-svn: 128862
* RFE encoding should also specify the "should be" encoding bits.Johnny Chen2011-04-043-28/+49
| | | | | | | | | rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while doing regression testings. llvm-svn: 128859
* Add missing file from r128851.Jim Grosbach2011-04-041-0/+58
| | | | llvm-svn: 128856
* Layer the memory manager between the JIT and the runtime Dyld.Jim Grosbach2011-04-043-18/+21
| | | | | | | | | | | The JITMemory manager references LLVM IR constructs directly, while the runtime Dyld works at a lower level and can handle objects which may not originate from LLVM IR. Introduce a new layer for the memory manager to handle the interface between them. For the MCJIT, this layer will be almost entirely simply a call-through w/ translation between the IR objects and symbol names. llvm-svn: 128851
* Make OpcodeMask an unsigned long long literal to deal with overflow.Joerg Sonnenberger2011-04-041-1/+1
| | | | llvm-svn: 128847
* Allow coalescing with reserved physregs in certain cases:Jakob Stoklund Olesen2011-04-043-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | | When a virtual register has a single value that is defined as a copy of a reserved register, permit that copy to be joined. These virtual register are usually copies of the stack pointer: %vreg75<def> = COPY %ESP; GR32:%vreg75 MOV32mr %vreg75, 1, %noreg, 0, %noreg, %vreg74<kill> MOV32mi %vreg75, 1, %noreg, 8, %noreg, 0 MOV32mi %vreg75<kill>, 1, %noreg, 4, %noreg, 0 CALLpcrel32 ... Coalescing these virtual registers early decreases register pressure. Previously, they were coalesced by RALinScan::attemptTrivialCoalescing after register allocation was completed. The lower register pressure causes the mcinst-lowering-cmp0.ll test case to fail because it depends on linear scan spilling a particular register. I am deleting 2008-08-05-SpillerBug.ll because it is counting the number of instructions emitted, and its revision history shows the 'correct' count being edited many times. llvm-svn: 128845
* Extract physreg joining policy to a separate method.Jakob Stoklund Olesen2011-04-042-53/+60
| | | | llvm-svn: 128844
* Fix incorrect alignment for NEON VST2b32_UPD.Johnny Chen2011-04-041-7/+132
| | | | | | rdar://problem/9225433 llvm-svn: 128841
* Insert code in the right location when lowering PowerPC atomics.Jakob Stoklund Olesen2011-04-041-2/+4
| | | | | | | This causes defs to dominate uses, no instructions after terminators, and other goodness. llvm-svn: 128836
* - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHTBruno Cardoso Lopes2011-04-047-32/+240
| | | | | | | | | | also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. llvm-svn: 128832
* Move transformation of JmpLink and related nodes done during instruction ↵Akira Hatanaka2011-04-042-59/+27
| | | | | | selection to Legalize phase. llvm-svn: 128830
* PowerPC atomic pseudos clobber CR0, they don't read it.Jakob Stoklund Olesen2011-04-042-2/+2
| | | | llvm-svn: 128829
* Use X0 instead of R0 for the zero register on ppc64.Jakob Stoklund Olesen2011-04-041-10/+13
| | | | | | The 32-bit R0 cannot be used where a 64-bit register is expected. llvm-svn: 128828
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-047-4/+81
| | | | llvm-svn: 128826
* Expand Op0Mask by one bit in preparation for the PadLock prefixes.Joerg Sonnenberger2011-04-043-50/+51
| | | | | | | | Define most shift masks incrementally to reduce the redundant hard-coding. Introduce new shift for the VEX flags to replace the magic constant 32 in various places. llvm-svn: 128822
* Stop caching basic block index ranges now that SlotIndexes can keep up.Jakob Stoklund Olesen2011-04-043-30/+33
| | | | llvm-svn: 128821
* Delete leftover data members.Jakob Stoklund Olesen2011-04-041-4/+0
| | | | llvm-svn: 128820
* Remove some support for ReturnInsts with multiple operands, and forJay Foad2011-04-043-43/+5
| | | | | | | returning a scalar value in a function whose return type is a single- element structure or array. llvm-svn: 128810
* Region: Allow user control the printing style of the print function.Tobias Grosser2011-04-041-16/+16
| | | | | | Contributed by: etherzhhb@gmail.com llvm-svn: 128808
* Attempt to fix breakage from r128782 reported by Francois Pichet onEli Friedman2011-04-041-0/+3
| | | | | | | llvm-commits. (Not sure why it only breaks on Windows; maybe it has something to do with the iterator representation...) llvm-svn: 128802
* Start migrating mach-o dumping facilities to the object file out of aEric Christopher2011-04-031-0/+28
| | | | | | separate executable. llvm-svn: 128801
OpenPOWER on IntegriCloud