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llvm-svn: 122268
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llvm-svn: 122265
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it could only be tested indirectly, via instcombine, gvn or some other
pass that makes use of InstructionSimplify, which means that testcases
had to be carefully contrived to dance around any other transformations
that that pass did.
llvm-svn: 122264
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llvm-svn: 122261
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llvm-svn: 122259
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situation.
llvm-svn: 122258
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the OverDefinedCache.
llvm-svn: 122256
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This is much easier to
verify as being safe thanks its recent de-recursivization.
llvm-svn: 122254
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llvm-svn: 122249
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(icmp ult (X + CA), C1 + 1) if C2 + CA == C1.
InstCombine creates these so now we compile x == 23 || x == 24 || x == 25 to
%x.off = add i32 %x, -23
%1 = icmp ult i32 %x.off, 3
instead of
%x.off = add i32 %x, -23
%1 = icmp ult i32 %x.off, 2
%cmp3 = icmp eq i32 %x, 25
%ret2 = or i1 %1, %cmp3
llvm-svn: 122248
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llvm-svn: 122247
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llvm-svn: 122246
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(they had just been forgotten before). Adding Xor causes "main" in the
existing testcase 2010-11-01-lshr-mask.ll to be hugely more simplified.
llvm-svn: 122245
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llvm-svn: 122243
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llvm-svn: 122242
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llvm-svn: 122238
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llvm-svn: 122237
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to make sure that the reused alloca has sufficient alignment.
llvm-svn: 122236
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llvm-svn: 122235
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argument. The generated alloca has to have at least the alignment of the
byval, if not, the client may be making assumptions that the new alloca won't
satisfy.
llvm-svn: 122234
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out-edges. Fixes PR8824.
llvm-svn: 122228
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begin at DEF slots. Fixes the second half of PR8813.
llvm-svn: 122225
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llvm-svn: 122224
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ARM (and other 32-bit-only) targets support for i8 and i16 overflow
multiplies. The generated code isn't great, but this at least fixes
CodeGen/Generic/overflow.ll when running on ARM hosts.
llvm-svn: 122221
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the same as setcc. Optimize ADDC(0,0,FLAGS) -> SET_CARRY(FLAGS). This is
a step towards finishing off PR5443. In the testcase in that bug we now get:
movq %rdi, %rax
addq %rsi, %rax
sbbq %rcx, %rcx
testb $1, %cl
setne %dl
ret
instead of:
movq %rdi, %rax
addq %rsi, %rax
movl $0, %ecx
adcq $0, %rcx
testq %rcx, %rcx
setne %dl
ret
llvm-svn: 122219
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the register; it may be a dead def instead. Fixes PR8820.
llvm-svn: 122218
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doesn't, match it back to setb.
On a 64-bit version of the testcase before we'd get:
movq %rdi, %rax
addq %rsi, %rax
sbbb %dl, %dl
andb $1, %dl
ret
now we get:
movq %rdi, %rax
addq %rsi, %rax
setb %dl
ret
llvm-svn: 122217
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llvm-svn: 122215
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llvm-svn: 122214
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their carry depenedencies with MVT::Flag operands) and use clean and beautiful
EFLAGS dependences instead.
We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs
(which is what requires the previous scheduler change) and change X86 ISelLowering
to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes.
With the previous series of changes, this causes no changes in the testsuite, woo.
llvm-svn: 122213
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Imagine we see:
EFLAGS = inst1
EFLAGS = inst2 FLAGS
gpr = inst3 EFLAGS
Previously, we would refuse to schedule inst2 because it clobbers
the EFLAGS of the predecessor. However, it also uses the EFLAGS
of the predecessor, so it is safe to emit. SDep edges ensure that
the right order happens already anyway.
This fixes 2 testsuite crashes with the X86 patch I'm going to
commit next.
llvm-svn: 122211
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llvm-svn: 122209
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llvm-svn: 122208
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PR8822.
llvm-svn: 122207
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after legalize types
has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type.
llvm-svn: 122206
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half of PR8813.
llvm-svn: 122205
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llvm-svn: 122204
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ConnectedVNInfoEqClasses::Classify().
llvm-svn: 122202
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consistently by moving it out of lowering into dag combine.
Add some missing patterns for matching away extended versions of setcc_c.
llvm-svn: 122201
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llvm-svn: 122199
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llvm-svn: 122197
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going through the CSE maps to get it.
llvm-svn: 122196
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llvm-svn: 122193
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headers provide symbols outside namespace std and the LLVM coding standards
state that we should prefix all of them.
llvm-svn: 122192
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enough to teach it that ADDE(0,0) is known 0 except the
low bit, for example.
llvm-svn: 122191
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llvm-svn: 122190
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we don't need -disable-mmx anymore.
llvm-svn: 122189
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llvm-svn: 122187
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generate them.
Now we compile:
define zeroext i8 @X(i8 signext %a, i8 signext %b) nounwind ssp {
entry:
%0 = tail call %0 @llvm.sadd.with.overflow.i8(i8 %a, i8 %b)
%cmp = extractvalue %0 %0, 1
br i1 %cmp, label %if.then, label %if.end
into:
_X: ## @X
## BB#0: ## %entry
subl $12, %esp
movb 16(%esp), %al
addb 20(%esp), %al
jo LBB0_2
Before we were generating:
_X: ## @X
## BB#0: ## %entry
pushl %ebp
movl %esp, %ebp
subl $8, %esp
movb 12(%ebp), %al
testb %al, %al
setge %cl
movb 8(%ebp), %dl
testb %dl, %dl
setge %ah
cmpb %cl, %ah
sete %cl
addb %al, %dl
testb %dl, %dl
setge %al
cmpb %al, %ah
setne %al
andb %cl, %al
testb %al, %al
jne LBB0_2
llvm-svn: 122186
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llvm-svn: 122183
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