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* Revert r236912.Quentin Colombet2015-05-091-4/+4
| | | | | | | | | | | | | | Author: dblaikie Date: Fri May 8 17:47:50 2015 New Revision: 236912 URL: http://llvm.org/viewvc/llvm-project?rev=236912&view=rev Log: [opaque pointer type] Cleanup a few references to pointee types using nearby non-pointee types of the same value & cleanup a convoluted return expression while I'm here llvm-svn: 236919
* [Target/ARM] Remove unused 'private' from class.Davide Italiano2015-05-081-2/+0
| | | | | | | Differential Revision: http://reviews.llvm.org/D9611 Reviewed by: rengolin llvm-svn: 236918
* ScheduleDAGInstrs: In functions with tail calls PseudoSourceValues are not ↵Arnold Schwaighofer2015-05-086-3/+19
| | | | | | | | | | | | | | | | | | | | non-aliasing distinct objects The code that builds the dependence graph assumes that two PseudoSourceValues don't alias. In a tail calling function two FixedStackObjects might refer to the same location. Worse 'immutable' fixed stack objects like function arguments are not immutable and will be clobbered. Change this so that a load from a FixedStackObject is not invariant in a tail calling function and don't return a PseudoSourceValue for an instruction in tail calling functions when building the dependence graph so that we handle function arguments conservatively. Fix for PR23459. rdar://20740035 llvm-svn: 236916
* [opaque pointer type] Cleanup a few references to pointee types using nearby ↵David Blaikie2015-05-081-4/+4
| | | | | | | | non-pointee types of the same value & cleanup a convoluted return expression while I'm here llvm-svn: 236912
* [lib/Fuzzer] build tests that work well with dfsan also w/o dfsanKostya Serebryany2015-05-085-10/+12
| | | | llvm-svn: 236909
* [lib/Fuzzer] use -fsanitize-coverage=trace-cmp when building LLVM with ↵Kostya Serebryany2015-05-086-10/+68
| | | | | | LLVM_USE_SANITIZE_COVERAGE; in lib/Fuzzer try to reload the corpus to pick up new units from other processes llvm-svn: 236906
* Switch lowering: cluster adjacent fall-through cases even at -O0Hans Wennborg2015-05-081-3/+5
| | | | | | | It's cheap to do, and codegen is much faster if cases can be merged into clusters. llvm-svn: 236905
* TargetParser: FPU/ARCH/EXT parsing refactory - NFCRenato Golin2015-05-0812-294/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This new class in a global context contain arch-specific knowledge in order to provide LLVM libraries, tools and projects with the ability to understand the architectures. For now, only FPU, ARCH and ARCH extensions on ARM are supported. Current behaviour it to parse from free-text to enum values and back, so that all users can share the same parser and codes. This simplifies a lot both the ASM/Obj streamers in the back-end (where this came from), and the front-end parsers for command line arguments (where this is going to be used next). The previous implementation, using .def/.h includes is deprecated due to its inflexibility to be built without the backend support and for being too cumbersome. As more architectures join this scheme, and as more features of such architectures are added (such as hardware features, type sizes, etc) into a full blown TargetDescription class, having a set of classes is the most sane implementation. The ultimate goal of this refactor both LLVM's and Clang's target description classes into one unique interface, so that we can de-duplicate and standardise the descriptions, as well as make it available for other front-ends, tools, etc. The FPU parsing for command line options in Clang has been converted to use this new library and a number of aliases were added for compatibility: * A bogus neon-vfpv3 alias (neon defaults to vfp3) * armv5/v6 * {fp4/fp5}-{sp/dp}-d16 Next steps: * Port Clang's ARCH/EXT parsing to use this library. * Create a TableGen back-end to generate this information. * Run this TableGen process regardless of which back-ends are built. * Expose more information and rename it to TargetDescription. * Continue re-factoring Clang to use as much of it as possible. llvm-svn: 236900
* [Fast-ISel] Clear kill flags on registers replaced by updateValueMap.Pete Cooper2015-05-081-0/+7
| | | | | | | | | | When selecting an extract instruction, we don't actually generate code but instead work out which register we are reading, and rewrite uses of the extract def to the source register. This is done via updateValueMap,. However, its possible that the source register we are rewriting *to* to also have uses. If those uses are after a kill of the value we are rewriting *from* then we have uses after a kill and the verifier fails. This code checks for the case where the to register is also used, and if so it clears all kill on the from register. This is conservative, but better that always clearing kills on the from register. llvm-svn: 236897
* [Hexagon] Generate more hardware loopsBrendon Cahoon2015-05-081-133/+206
| | | | | | | | | Refactored parts of the hardware loop pass to generate more. Also, added more tests. Differential Revision: http://reviews.llvm.org/D9568 llvm-svn: 236896
* [BasicAA] Fix zext & sext handlingSanjoy Das2015-05-081-60/+199
| | | | | | | | | | | | | | | | | | | | | | | Summary: There are several unhandled edge cases in BasicAA's GetLinearExpression method. This changes fixes outstanding issues, including zext / sext of a constant with the sign bit set, and the refusal to decompose zexts or sexts of wrapping arithmetic. Test Plan: Unit tests added in //q.ext.ll//. Patch by Nick White. Reviewers: hfinkel, sanjoy Reviewed By: hfinkel, sanjoy Subscribers: sanjoy, llvm-commits, hfinkel Differential Revision: http://reviews.llvm.org/D6682 llvm-svn: 236894
* Replace branch-to-unreachable with assertion.David Blaikie2015-05-081-4/+2
| | | | llvm-svn: 236893
* [X86] Fast-ISel was incorrectly always killing the source of a truncate.Pete Cooper2015-05-081-1/+3
| | | | | | | | | | | A trunc from i32 to i1 on x86_64 generates an instruction such as %vreg19<def> = COPY %vreg9:sub_8bit<kill>; GR8:%vreg19 GR32:%vreg9 However, the copy here should only have the kill flag on the 32-bit path, not the 64-bit one. Otherwise, we are killing the source of the truncate which could be used later in the program. llvm-svn: 236890
* Extend the statepoint intrinsic to allow statepoints to be marked as ↵Pat Gavlin2015-05-086-19/+177
| | | | | | | | | | | | | | | | | | | | | | transitions from GC-aware code to code that is not GC-aware. This changes the shape of the statepoint intrinsic from: @llvm.experimental.gc.statepoint(anyptr target, i32 # call args, i32 unused, ...call args, i32 # deopt args, ...deopt args, ...gc args) to: @llvm.experimental.gc.statepoint(anyptr target, i32 # call args, i32 flags, ...call args, i32 # transition args, ...transition args, i32 # deopt args, ...deopt args, ...gc args) This extension offers the backend the opportunity to insert (somewhat) arbitrary code to manage the transition from GC-aware code to code that is not GC-aware and back. In order to support the injection of transition code, this extension wraps the STATEPOINT ISD node generated by the usual lowering lowering with two additional nodes: GC_TRANSITION_START and GC_TRANSITION_END. The transition arguments that were passed passed to the intrinsic (if any) are lowered and provided as operands to these nodes and may be used by the backend during code generation. Eventually, the lowering of the GC_TRANSITION_{START,END} nodes should be informed by the GC strategy in use for the function containing the intrinsic call; for now, these nodes are instead replaced with no-ops. Differential Revision: http://reviews.llvm.org/D9501 llvm-svn: 236888
* Clear kill flags on all used registers when sinking instructions.Pete Cooper2015-05-081-1/+7
| | | | | | | | | | | | | The test here was sinking the AND here to a lower BB: %vreg7<def> = ANDWri %vreg8, 0; GPR32common:%vreg7,%vreg8 TBNZW %vreg8<kill>, 0, <BB#1>; GPR32common:%vreg8 which meant that vreg8 was read after it was killed. This commit changes the code from clearing kill flags on the AND to clearing flags on all registers used by the AND. llvm-svn: 236886
* 80 cols fix since i'm looking at this function anyway. NFCPete Cooper2015-05-081-1/+2
| | | | llvm-svn: 236885
* [Hexagon] Update AnalyzeBranch, etc target hooksBrendon Cahoon2015-05-083-274/+350
| | | | | | | | | | | | | Improved the AnalyzeBranch, InsertBranch, and RemoveBranch functions in order to handle more of our branch instructions. This requires changes to analyzeCompare and PredicateInstructions. Specifically, we've added support for new value compare jumps, improved handling of endloop, added more compare instructions, and improved support for predicate instructions. Differential Revision: http://reviews.llvm.org/D9559 llvm-svn: 236876
* [X86] Teach 'getTargetShuffleMask' how to look through ISD::WrapperRIP when ↵Andrea Di Biagio2015-05-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | decoding a PSHUFB mask. The function 'getTargetShuffleMask' already knows how to deal with PSHUFB nodes where the mask node is a load from constant pool, and the constant pool node is wrapped by a X86ISD::Wrapper node. This patch extends that logic by teaching it how to also look through X86ISD::WrapperRIP. This helps function combineX86ShufflesRecusively to combine more shuffle sequences containing PSHUFB nodes if we are in RIPRel PIC mode. Before this change, llc (with -relocation-model=pic -march=x86-64) was unable to decode a pshufb where the mask was loaded from a constant pool. For example, the no-op shuffle from test 'x86-fold-pshufb.ll' was not folded into its operand, so instead of generating a single 'movaps' the backend always generated a sub-optimal 'movdqa + pshufb' sequence. Added test x86-fold-pshufb.ll. llvm-svn: 236863
* [mips][microMIPSr6] Implement ALUIPC and AUIPC instructionsJozef Kolek2015-05-083-3/+32
| | | | | | | | This patch implements ALUIPC and AUIPC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8441 llvm-svn: 236858
* [mips][microMIPSr6] Implement ADDIUPC and LWPC instructionsJozef Kolek2015-05-083-3/+31
| | | | | | | | This patch implements ADDIUPC and LWPC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8415 llvm-svn: 236852
* Fix alignment checks in MergeConsecutiveStores.James Y Knight2015-05-081-36/+52
| | | | | | | | | | | | | | | 1) check whether the alignment of the memory is sufficient for the *merged* store or load to be efficient. Not doing so can result in some ridiculously poor code generation, if merging creates a vector operation which must be aligned but isn't. 2) DON'T check that the alignment of each load/store is equal. If you're merging 2 4-byte stores, the first *might* have 8-byte alignment, but the second certainly will have 4-byte alignment. We do want to allow those to be merged. llvm-svn: 236850
* Fix coding standart based on post submit comments.Igor Laevsky2015-05-081-4/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D7760 llvm-svn: 236849
* [ARM] Reject invalid -march valuesJohn Brawn2015-05-081-35/+40
| | | | | | | | | | | | | | | Restructure Triple::getARMCPUForArch so that invalid values will return nullptr, while retaining the behaviour that an argument specifying no particular architecture version will give a default CPU. This will be used by clang to give an error on invalid -march values. Also restructure the extraction of the architecture version from the MArch string a little to hopefully make what it's doing clearer. Differential Revision: http://reviews.llvm.org/D9599 llvm-svn: 236845
* Fix gcc warning of different enum and non-enum types in ternaryDenis Protivensky2015-05-081-8/+8
| | | | | | | Make '0' literal explicitly unsigned with '0u'. This appeared after r236775. llvm-svn: 236838
* [mips] Only use FGR_{32,64} in TableGen descriptions. NFC.Toma Tabacu2015-05-082-33/+23
| | | | | | | | | | | | | | Summary: Instead of explicitly adding the IsFP64bit and NotFP64bit predicates through AdditionalRequires. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9566 llvm-svn: 236835
* This change is refactoring only. It moves basic block normalization for ↵Igor Laevsky2015-05-081-39/+36
| | | | | | invokes to happen before replacement of a call with safepoint in "ReplaceWithStatepoint". Previously it was partly done before replacement of calls with safepoint and partly after call replacement but before RAUW's for gc_relocates, which was confusing. llvm-svn: 236829
* [mips] Emit the .insn directive for empty basic blocks.Vasileios Kalintiris2015-05-082-0/+7
| | | | | | | | | | | | | | | | | | | Summary: In microMIPS, labels need to know whether they are on code or data. This is indicated with STO_MIPS_MICROMIPS and can be inferred by being followed by instructions. For empty basic blocks, we can ensure this by emitting the .insn directive after the label. Also, this fixes some failures in our out-of-tree microMIPS buildbots, for the exception handling regression tests under: SingleSource/Regression/C++/EH Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9530 llvm-svn: 236815
* [llvm-readobj/obj2yaml/yaml2obj] Support MIPS machine ELF header flagsSimon Atanasyan2015-05-081-0/+18
| | | | llvm-svn: 236807
* [opaque pointer type] Explicit pointee type for GEPOperator/GEPConstantExpr.David Blaikie2015-05-086-23/+59
| | | | | | | Also a couple of other changes to avoid use of PointerType::getElementType here & there too. llvm-svn: 236799
* Update CMake flags, LibFuzzer comments and docs for new -fsanitize-coverage= ↵Alexey Samsonov2015-05-072-3/+2
| | | | | | flags. llvm-svn: 236797
* InMips16HardFloat was only being set conditional on whether orEric Christopher2015-05-071-1/+1
| | | | | | | not IsSoftFloat was set so remove it from here simplifying the accessor. llvm-svn: 236795
* Rename the MIPS routine abiUsesSoftFloat -> useSoftFloat to matchEric Christopher2015-05-078-15/+13
| | | | | | some incoming changes and the general scheme used by features (use/has). llvm-svn: 236794
* Delete unused createSanitizerCoverageModulePass overload.Alexey Samsonov2015-05-071-3/+0
| | | | llvm-svn: 236791
* Revert "SanitizerCoverage: Use `createSanitizerCtor` to create ctor and call ↵Ismail Pazarbasi2015-05-071-11/+16
| | | | | | | | init" Will fix tomorrow. Unbreak build bots now. llvm-svn: 236786
* Fix typo.Matthias Braun2015-05-071-1/+1
| | | | llvm-svn: 236785
* Clear kill flags in tail duplication.Pete Cooper2015-05-071-0/+3
| | | | | | | | | | | | | | If we duplicate an instruction then we must also clear kill flags on any uses we rewrite. Otherwise we might be killing a register which was used in other BBs. For example, here the entry BB ended up with these instructions, the ADD having been tail duplicated. %vreg24<def> = t2ADDri %vreg10<kill>, 1, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg24 rGPR:%vreg10 %vreg22<def> = COPY %vreg10; GPR:%vreg22 rGPR:%vreg10 The copy here is inserted after the add and so needs vreg10 to be live. llvm-svn: 236782
* SanitizerCoverage: Use `createSanitizerCtor` to create ctor and call initIsmail Pazarbasi2015-05-071-16/+11
| | | | | | | | | | Reviewers: kcc, samsonov Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8780 llvm-svn: 236780
* MSan: Use `createSanitizerCtor` to create ctor, and call `__msan_init`Ismail Pazarbasi2015-05-071-3/+12
| | | | | | | | | | Reviewers: kcc, eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8781 llvm-svn: 236779
* TSan: Use `createSanitizerCtor` to create ctor, and call `__tsan_init`Ismail Pazarbasi2015-05-071-6/+13
| | | | | | | | | | Reviewers: kcc, dvyukov Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8779 llvm-svn: 236778
* ASan: Use `createSanitizerCtor` to create ctor, and call `__asan_init`Ismail Pazarbasi2015-05-071-10/+4
| | | | | | | | | | Reviewers: kcc, samsonov Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8778 llvm-svn: 236777
* Change getTargetNodeName() to produce compiler warnings for missing cases, ↵Matthias Braun2015-05-0726-41/+125
| | | | | | fix them llvm-svn: 236775
* [lib/Fuzzer] change the way we use taint information for fuzzing. Now, we ↵Kostya Serebryany2015-05-074-49/+84
| | | | | | run a single unit and collect suggested mutations based on tracing+taint data, then apply the suggested mutations one by one. The previous scheme was slower and more complex. llvm-svn: 236772
* Use auto instead of the long type name. NFC.Steven Wu2015-05-071-2/+1
| | | | llvm-svn: 236768
* [AArch64] Fix sext/zext folding in address arithmetic.Pete Cooper2015-05-071-29/+32
| | | | | | | | We were accidentally folding a sign/zero extend in to address arithmetic in a different BB when the extend wasn't available there. Cross BB fast-isel isn't safe, so restrict this to only when the extend is in the same BB as the use. llvm-svn: 236764
* [lib/Fuzzer] minor refactoring/simplification, NFCKostya Serebryany2015-05-073-31/+41
| | | | llvm-svn: 236757
* Add VSX Scalar loads and stores to the PPC back endNemanja Ivanovic2015-05-078-8/+150
| | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D9440 It adds a new register class to the PPC back end to contain single precision values in VSX registers. Additionally, it adds scalar loads and stores for VSX registers. llvm-svn: 236755
* YAML: Enable the YAMLParser tests. Alex Lorenz2015-05-071-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | | This commit enables the tests located in test/YAMLParser directory. Those tests were never actually enabled, as llvm-lit didn't pick up the files with the 'data' extension. The commit renames those test files to files with the 'test' extension so that llvm-lit would find them. This commit also modifies yaml-bench so that it returns an error status if an error occurred during parsing. It also adds the '-use-color' command line option to yaml-bench (to make sure that file check matches the error messages in the output stream). This commit modifies some of the renamed tests so that they wouldn't fail. It gets rid of XFAILs and uses the 'not' command instead for some of the tests that have to fail during parsing. This commit also adds some 'FIXME' comments to a couple of tests that are supposed to fail but currently pass because of various bugs in the implementation of the yaml parser. Reviewers: Justin Bogner Differential Revision: http://reviews.llvm.org/D9448 llvm-svn: 236754
* Recommit r236670: [opaque pointer type] Pass explicit pointer type through ↵David Blaikie2015-05-074-16/+36
| | | | | | | | | | GEP constant folding"" Clang regressions were caused by more stringent assertion checking introduced by this change. Small fix needed to clang has been committed in r236751. llvm-svn: 236752
* Fix information loss in branch probability computation.Diego Novillo2015-05-071-12/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This addresses PR 22718. When branch weights are too large, they were being clamped to the range [1, MaxWeightForBB]. But this clamping is only applied to edges that go outside the range, so it distorts the relative branch probabilities. This patch changes the weight calculation to scale every branch so the relative probabilities are preserved. The scaling is done differently now. First, all the branch weights are added up, and if the sum exceeds 32 bits, it computes an integer scale to bring all the weights within the range. The patch fixes an existing test that had slightly wrong branch probabilities due to the previous clamping. It now gets branch weights scaled accordingly. Reviewers: dexonsmith Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9442 llvm-svn: 236750
* [mips][microMIPSr6] Implement JIALC and JIC instructionsJozef Kolek2015-05-072-3/+30
| | | | | | | | This patch implements JIALC and JIC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8389 llvm-svn: 236748
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