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* [X86] Add isel patterns for selecting masked SUBV_BROADCAST with bitcasts. ↵Craig Topper2018-02-053-55/+108
| | | | | | | | Remove combineBitcastForMaskedOp. Add test cases for the merge masked versions to make sure we have all those covered. llvm-svn: 324210
* [SimplifyCFG] Relax restriction for folding unconditional branchesSerguei Katkov2018-02-051-1/+4
| | | | | | | | | | | | | | | | | | The commit rL308422 introduces a restriction for folding unconditional branches. Specifically if empty block with unconditional branch leads to header of the loop then elimination of this basic block is prohibited. However it seems this condition is redundantly strict. If elimination of this basic block does not introduce more back edges then we can eliminate this block. The patch implements this relax of restriction. Reviewers: efriedma, mcrosier, pacxx, hsung, davidxl Reviewed By: pacxx Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42691 llvm-svn: 324208
* [X86] Remove unused lambda. NFCCraig Topper2018-02-051-11/+0
| | | | llvm-svn: 324206
* [X86] Remove X86ISD::SHUF128 from combineBitcastForMaskedOp. Use isel ↵Craig Topper2018-02-052-20/+46
| | | | | | | | | | patterns instead. We always created X86ISD::SHUF128 with a 64-bit element type so we can use isel patterns to detect a bitconvert to 32-bit to handle masking. The test changes are because we also match the bitconvert even if there is no masking. This leads to unnecessary isel pattern, but it requires more multiclass hackery in tablegen to get rid of it. llvm-svn: 324205
* Re-apply [SCEV] Fix isLoopEntryGuardedByCond usageSerguei Katkov2018-02-052-11/+23
| | | | | | | | | | | | | | | | | ScalarEvolution::isKnownPredicate invokes isLoopEntryGuardedByCond without check that SCEV is available at entry point of the loop. It is incorrect and fixed by patch. To bugs additionally fixed: assert is moved after the check whether loop is not a nullptr. Usage of isLoopEntryGuardedByCond in ScalarEvolution::isImpliedCondOperandsViaNoOverflow is guarded by isAvailableAtLoopEntry. Reviewers: sanjoy, mkazantsev, anna, dorit, reames Reviewed By: mkazantsev Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42417 llvm-svn: 324204
* [InlineFunction] Set arg attrs even if there only are VarArg attrs.Florian Hahn2018-02-041-1/+1
| | | | | | | | | | | | When using the partial inliner, we might have attributes for forwarded varargs, but the CodeExtractor does not create an empty argument attribute set for regular arguments in that case, because it does not know of the additional arguments. So in case we have attributes for VarArgs, we also have to make sure we create (empty) attributes for all regular arguments. This fixes PR36210. llvm-svn: 324197
* [LV] Use Demanded Bits and ValueTracking for reduction type-shrinkingChad Rosier2018-02-042-76/+158
| | | | | | | | | | | | | | | The type-shrinking logic in reduction detection, although narrow in scope, is also rather ad-hoc, which has led to bugs (e.g., PR35734). This patch modifies the approach to rely on the demanded bits and value tracking analyses, if available. We currently perform type-shrinking separately for reductions and other instructions in the loop. Long-term, we should probably think about computing minimal bit widths in a more complete way for the loops we want to vectorize. PR35734 Differential Revision: https://reviews.llvm.org/D42309 llvm-svn: 324195
* [X86] Add DAG combine to turn (bitcast (and/or/xor (bitcast X), Y)) -> ↵Craig Topper2018-02-041-0/+53
| | | | | | | | | | (and/or/xor X, (bitcast Y)) when casting between GPRs and mask operations. This reduces the number of transitions between k-registers and GPRs, reducing the number of instructions. There's still some room for improvement to remove more transitions, but this is a good start. llvm-svn: 324184
* [X86] Remove unused function argument. NFCCraig Topper2018-02-041-4/+3
| | | | llvm-svn: 324183
* [DAGCombiner] When folding fold (sext/zext (and/or/xor (sextload/zextload ↵Craig Topper2018-02-031-4/+6
| | | | | | | | | | | | | | | | | | | x), cst)) -> (and/or/xor (sextload/zextload x), (sext/zext cst)) make sure we check the legality of the full extended load. Summary: If the load is already an extended load we should be using the memory VT for the legality check, not just the VT of the current extension. I don't have a test case, just noticed it while investigating some load extension improvements. Reviewers: RKSimon, spatel, niravd Reviewed By: niravd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42783 llvm-svn: 324181
* [SelectionDAG] Don't use simple VT in generic shuffle codeSimon Pilgrim2018-02-031-1/+1
| | | | | | | | Better to assume that any value type may be commuted, not just MVTs. No test case right now, but discovered while investigating possible shuffle combines. llvm-svn: 324179
* [X86] Remove and autoupgrade kand/kandn/kor/kxor/kxnor/knot intrinsics.Craig Topper2018-02-033-30/+37
| | | | | | | | Clang already stopped using these a couple months ago. The test cases aren't great as there is nothing forcing the operations to stay in k-registers so some of them moved back to scalar ops due to the bitcasts being moved around. llvm-svn: 324177
* [ORC] Rename NullResolver to NullLegacyResolver.Lang Hames2018-02-031-2/+3
| | | | | | | | | This resolver conforms to the LegacyJITSymbolResolver interface, and will be replaced with a null-returning resolver conforming to the newer orc::SymbolResolver interface in the near future. This patch renames the class to avoid a clash. llvm-svn: 324175
* [InstCombine] Allow common type conversions to i8/i16/i32David Green2018-02-031-1/+9
| | | | | | | | | | | This, in instcombine, allows conversions to i8/i16/i32 (very common cases) even if the resulting type is not legal according to the data layout. This can often open up extra combine opportunities. Differential Revision: https://reviews.llvm.org/D42424 llvm-svn: 324174
* Fix MSVC signed/unsigned comparison warning. NFCI.Simon Pilgrim2018-02-031-1/+1
| | | | llvm-svn: 324171
* [InstCombine] Use getDestAlignment in SimplifyMemSet (NFC)Daniel Neilson2018-02-021-2/+2
| | | | | | | | Summary: Small NFC change to change the name of the function used getting and setting the alignment of a memset. llvm-svn: 324148
* [X86] Prefer to create a ISD::SETCC over X86ISD::PCMPEQ in ↵Craig Topper2018-02-021-3/+3
| | | | | | | | combineVectorSizedSetCCEquality. This is running pre-legalize, we should try to use target independent nodes. This will give the best opportunity for target independent optimizations. llvm-svn: 324147
* [X86] Pass SDLoc by const reference in a few more places in ↵Craig Topper2018-02-021-6/+8
| | | | | | X86ISelLowering.cpp. NFC llvm-svn: 324135
* [GISel][NFC]: Move RegisterBankInfo::getSizeInBits into TargetRegisterInfo.Aditya Nandakumar2018-02-022-13/+27
| | | | llvm-svn: 324125
* [InstCombine] simplify logic for swapMayExposeCSEOpportunities; NFCISanjay Patel2018-02-021-23/+9
| | | | llvm-svn: 324122
* [InstCombine] fix typos, formatting; NFCSanjay Patel2018-02-021-7/+6
| | | | llvm-svn: 324118
* [AArch64][GlobalISel] Use getRegClassForTypeOnBank() in selectCopy.Amara Emerson2018-02-021-23/+15
| | | | | | Differential Revision: https://reviews.llvm.org/D42832 llvm-svn: 324110
* [X86] Remove checks for FeatureAVX512 from the X86 assembly parser. Remove ↵Craig Topper2018-02-021-83/+73
| | | | | | | | | | | | | | | | | | | | | mcpu/mattr from assembly test command lines. Summary: We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode. I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features. Fixes PR36202 Reviewers: RKSimon, echristo, bkramer Reviewed By: echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42824 llvm-svn: 324106
* [AMDGPU] Switch to the new addr space mapping by defaultYaxun Liu2018-02-022-20/+3
| | | | | | | | This requires corresponding clang change. Differential Revision: https://reviews.llvm.org/D40955 llvm-svn: 324101
* Fix type sizes that were causing incorrect string formattingJames Henderson2018-02-021-2/+2
| | | | llvm-svn: 324096
* [ThinLTO] - Add comment. NFC.George Rimar2018-02-021-0/+2
| | | | | | Was requested during review of D42798. llvm-svn: 324095
* [Analysis] Support aggregate access types in TBAAIvan A. Kosarev2018-02-021-96/+217
| | | | | | | | | This patch implements analysis for new-format TBAA access tags with aggregate types as their final access types. Differential Revision: https://reviews.llvm.org/D41501 llvm-svn: 324092
* Add missing new files from r324077James Henderson2018-02-022-0/+218
| | | | | | Differential Revision: https://reviews.llvm.org/D42481 llvm-svn: 324078
* [DWARF v5] Add limited support for dumping .debug_rnglistsJames Henderson2018-02-023-12/+29
| | | | | | | | | | | | | | | | | | | | | This change adds support to llvm-dwarfdump for dumping DWARF5 .debug_rnglists sections in regular ELF files. It is not complete, in that several DW_RLE_* encodings are currently not supported, but does dump the headert and the basic ranges for DW_RLE_start_length and DW_RLE_start_end encodings. Obvious next steps are to add verbose dumping that dumps the raw encodings, rather than the interpreted contents, to add -verify support of the section (e.g. to show that the correct number of offsets are specified), add dumping of .debug_rnglists.dwo, and to add support for other encodings. Reviewed by: dblaikie, JDevlieghere Differential Revision: https://reviews.llvm.org/D42481 llvm-svn: 324077
* [LTO] - Simplify. NFC.George Rimar2018-02-021-3/+2
| | | | llvm-svn: 324076
* [ThinLTO] - Fix for "ThinLTO inlines variables that should be discarded".George Rimar2018-02-021-6/+12
| | | | | | | | | | | This fixes PR36187. Patch teaches ThinLTO to drop non-prevailing variables, just like we recently did for functions (in r323633). Differential revision: https://reviews.llvm.org/D42798 llvm-svn: 324075
* [GlobalOpt] Include padding in debug fragmentsMikael Holmen2018-02-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When creating the debug fragments for a SRA'd variable, use the types' allocation sizes. This fixes issues where the pass would emit too small fragments, placed at the wrong offset, for padded types. An example of this is long double on x86. The type is represented using x86_fp80, which is 10 bytes, but the value is aligned to 12/16 bytes. The padding is included in the type's DW_AT_byte_size attribute; therefore, the fragments should also include that. Newer GCC releases (I tested 7.2.0) emit 12/16-byte pieces for long double. Earlier releases, e.g. GCC 5.5.0, behaved as LLVM did, i.e. by emitting a 10-byte piece, followed by an empty 2/6-byte piece for the padding. Failing to cover all `DW_AT_byte_size' bytes of a value with non-empty pieces results in the value being printed as <optimized out> by GDB. Patch by: David Stenberg Reviewers: aprantl, JDevlieghere Reviewed By: aprantl, JDevlieghere Subscribers: llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D42807 llvm-svn: 324066
* [SelectionDAG] Consider endianness in scalarizeVectorStore().Jonas Paulsson2018-02-021-2/+5
| | | | | | | | | | | | When handling vectors with non byte-sized elements, reverse the order of the elements in the built integer if the target is Big-Endian. SystemZ tests updated. Review: Eli Friedman, Ulrich Weigand. https://reviews.llvm.org/D42786 llvm-svn: 324063
* [SelectionDAG] Add an assert in getNode() for EXTRACT_VECTOR_ELT.Jonas Paulsson2018-02-021-0/+4
| | | | | | | | When getNode() is called to create an EXTRACT_VECTOR_ELT, assert that the result VT is at least as wide as the vector element type. Review: Eli Friedman llvm-svn: 324061
* [RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-objdump could get ↵Shiva Chen2018-02-021-0/+13
| | | | | | | | | | | RISCV target feature llvm-objdump could get C feature by ELF::EF_RISCV_RVC e_flag, so then we don't have to add -mattr=+c on the command line. Differential Revision: https://reviews.llvm.org/D42629 llvm-svn: 324058
* [X86] Legalize (v64i1 (bitcast (i64 X))) on 32-bit targets by extracting ↵Craig Topper2018-02-021-0/+16
| | | | | | | | 32-bit halves from i32, bitcasting each to v32i1, and concatenating. This prevents the scalarization that would otherwise occur. llvm-svn: 324057
* [X86] Legalize (i64 (bitcast (v64i1 X))) on 32-bit targets by extracting to ↵Craig Topper2018-02-021-0/+17
| | | | | | | | v32i1 and bitcasting to i32. This saves a trip through memory and seems to open up other combining opportunities. llvm-svn: 324056
* [RISCV] Fix c.addi and c.addi16sp immediate constraints which should be non-zeroShiva Chen2018-02-022-9/+34
| | | | | | Differential Revision: https://reviews.llvm.org/D42782 llvm-svn: 324055
* [RISCV] Define getSetCCResultType for setting vector setCC typeShiva Chen2018-02-022-0/+10
| | | | | | | | To avoid trigger "No default SetCC type for vectors!" Assertion Differential Revision: https://reviews.llvm.org/D42675 llvm-svn: 324054
* Fix debug spelling in ResetMachineFunction pass.Amara Emerson2018-02-021-2/+2
| | | | llvm-svn: 324048
* [GlobalISel] Constrain the dest reg of IMPLICT_DEF.Amara Emerson2018-02-021-0/+6
| | | | | | | | | | This fixes a crash where the user is a COPY, which deliberately does not constrain its source operands, resulting in a vreg without a reg class escaping selection. Differential Revision: https://reviews.llvm.org/D42697 llvm-svn: 324047
* Remove non-modular header containing static utility functionsDavid Blaikie2018-02-022-203/+178
| | | | | | | | | | The one place that uses these functions isn't particularly long/complicated, so it's easier to just have these inline at that location than trying to split it out into a true header. (in part also because of the use of the DEBUG macros, which make this not really a standalone header even if the static functions were made inline instead) llvm-svn: 324044
* Add missing includesDavid Blaikie2018-02-021-0/+3
| | | | llvm-svn: 324040
* SplitKit: Fix liveness recomputation in some remat cases.Matthias Braun2018-02-022-11/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Example situation: ``` BB0: %0 = ... use %0 ; ... condjump BB1 jmp BB2 BB1: %0 = ... ; rematerialized def from above (from earlier split step) jmp BB2 BB2: ; ... use %0 ``` %0 will have a live interval with 3 value numbers (for the BB0, BB1 and BB2 parts). Now SplitKit tries and succeeds in rematerializing the value number in BB2 (This only works because it is a secondary split so SplitKit is can trace this back to a single original def). We need to recompute all live ranges affected by a value number that we rematerialize. The case that we missed before is that when the value that is rematerialized is at a join (Phi VNI) then we also have to recompute liveness for the predecessor VNIs. rdar://35699130 Differential Revision: https://reviews.llvm.org/D42667 llvm-svn: 324039
* [X86] Separate the call to LowerVectorAllZeroTest from EmitTest. NFCICraig Topper2018-02-011-17/+21
| | | | | | | | | | Every instruction that has the word TEST in its name seems to have been buried into EmitTest. But that code is largely concerned with trying to reuse the flags from instructions that update flags in a pretty normal way. PTEST/TESTP/KTEST do not update flags in a normal way. They only update Z and C and the C flag update is non-standard. Rather than try to bend EmitTest's already complex logic to accomodate this, just move the call up to LowerSETCC and replicate the few pre-checks that are needed. While there add a FIXME for using the C flag for checking for all 1s which we definitely couldn't do from EmitTEST. llvm-svn: 324029
* [GlobalISel][Legalizer] Relax a legalization loop detecting assert.Amara Emerson2018-02-011-1/+3
| | | | | | | Legalizing vectors may keep the element type the same but change the number of elements, the assert didn't take this into account. llvm-svn: 324028
* [InstCombine] allow multi-use values in canEvaluate* if all uses are in 1 instSanjay Patel2018-02-011-5/+13
| | | | | | | | | | | | | | | | This is the enhancement suggested in D42536 to fix a shortcoming in regular InstCombine's canEvaluate* functionality. When we have multiple uses of a value, but they're all in one instruction, we can allow that expression to be narrowed or widened for the same cost as a single-use value. AFAICT, this can only matter for multiply: sub/and/or/xor/select would be simplified away if the operands are the same value; add becomes shl; shifts with a variable shift amount aren't handled. Differential Revision: https://reviews.llvm.org/D42739 llvm-svn: 324014
* [PowerPC] Tell VSX swap removal that scalar conversions are lane-sensitiveNemanja Ivanovic2018-02-011-0/+2
| | | | | | | | This is a rather non-controversial change. We were missing these instructions from the list of instructions that are lane-sensitive. These two put the result into lane 0 (BE) or 3 (LE) regardless of the input. This patch fixes PR36068. llvm-svn: 324005
* [DAGCombiner] When folding (insert_subvector undef, (bitcast ↵Craig Topper2018-02-011-1/+3
| | | | | | | | | | | | (extract_subvector N1, Idx)), Idx) -> (bitcast N1) make sure that N1 has the same total size as the original output We were only checking the element count, but not the total width. This could cause illegal bitcasts to be created if for example the output was 512-bits, but N1 is 256 bits, and the extraction size was 128-bits. Fixes PR36199 Differential Revision: https://reviews.llvm.org/D42809 llvm-svn: 324002
* [GlobalISel] Fix assert failure when legalizing non-power-2 loads.Amara Emerson2018-02-011-3/+6
| | | | | | | Until we support extending loads properly we're going to fall back for these. We already handle stores in the same way, so this is just being consistent. llvm-svn: 324001
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