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* Add OpSize16 flags to 32-bit CRC32 instructions so they can be encoded ↵Craig Topper2014-01-171-2/+2
| | | | | | correctly in 16-bit mode. llvm-svn: 199478
* Teach x86 asm parser to handle 'opaque ptr' in Intel syntax.Craig Topper2014-01-171-0/+1
| | | | llvm-svn: 199477
* Teach X86 asm parser to understand 'ZMMWORD PTR' in Intel syntax.Craig Topper2014-01-171-0/+1
| | | | llvm-svn: 199476
* Fix intel syntax for 64-bit version of FXSAVE/FXRSTOR to use '64' suffix ↵Craig Topper2014-01-171-2/+2
| | | | | | instead of 'q' llvm-svn: 199474
* VEX_PREFIX_66 doesn't need to set the hasOpSize flag since VEX instructions ↵Craig Topper2014-01-171-11/+0
| | | | | | don't use the size fields it controls. llvm-svn: 199470
* Replace duplicated code with a existing helper function.Craig Topper2014-01-171-16/+1
| | | | llvm-svn: 199468
* [AArch64]Fix the problem can't select f16_to_f32 and f32_to_f16.Hao Liu2014-01-172-0/+16
| | | | | | | Also add copy support for FPR16. Also add a missing test case file belongs to commit r197361. llvm-svn: 199463
* [AArch64 NEON] Custom lower conversion between vector integer and vector ↵Kevin Qin2014-01-171-0/+94
| | | | | | floating point if element bit-width doesn't match. llvm-svn: 199462
* [AArch64]Fix the problem can't select concat_vectors of two v1i32 types.Hao Liu2014-01-172-12/+10
| | | | | | Also fix the problem can't select scalar_to_vector from f32 to v2f32/v4f32. llvm-svn: 199461
* Change inalloca rules to make it only apply to the last parameterReid Kleckner2014-01-161-24/+9
| | | | | | | | | | | This makes things a lot easier, because we can now talk about the "argument allocation", which allocates all the memory for the call in one shot. The only functional change is to the verifier for a feature that hasn't shipped yet. llvm-svn: 199434
* [opt][PassInfo] Allow opt to run passes that need target machine.Quentin Colombet2014-01-162-5/+15
| | | | | | | | | | | | | | | | | | When registering a pass, a pass can now specify a second construct that takes as argument a pointer to TargetMachine. The PassInfo class has been updated to reflect that possibility. If such a constructor exists opt will use it instead of the default constructor when instantiating the pass. Since such IR passes are supposed to be rare, no specific support has been added to this commit to allow an easy registration of such a pass. In other words, for such pass, the initialization function has to be hand-written (see CodeGenPrepare for instance). Now, codegenprepare can be tested using opt: opt -codegenprepare -mtriple=mytriple input.ll llvm-svn: 199430
* Fix two cases where we could lose fast math flags when optimizing FADD ↵Owen Anderson2014-01-161-4/+10
| | | | | | expressions. llvm-svn: 199427
* Fix an instance where we would drop fast math flags when performing an fdiv ↵Owen Anderson2014-01-161-1/+3
| | | | | | to reciprocal multiply transformation. llvm-svn: 199425
* Fix a bug in InstCombine where we failed to preserve fast math flags when ↵Owen Anderson2014-01-161-2/+5
| | | | | | optimizing an FMUL expression. llvm-svn: 199424
* llvm-objdump/COFF: Print DLL name in the export table header.Rui Ueyama2014-01-161-1/+11
| | | | llvm-svn: 199422
* Teach InstCombine that (fmul X, -1.0) can be simplified to (fneg X), which ↵Owen Anderson2014-01-161-0/+10
| | | | | | LLVM expresses as (fsub -0.0, X). llvm-svn: 199420
* Use static instead of anonymous namespace.Rui Ueyama2014-01-161-8/+4
| | | | llvm-svn: 199419
* Reduce nesting.Rui Ueyama2014-01-161-13/+11
| | | | llvm-svn: 199418
* Use the current local variable naming style.Rui Ueyama2014-01-161-244/+242
| | | | llvm-svn: 199417
* Tweak the MCExternalSymbolizer to print references to C string literalsKevin Enderby2014-01-161-2/+5
| | | | | | | | | | | | | | | with raw_ostream's write_escaped() method. For example darwin's otool(1) program that uses the llvm disassembler now produces disassembly like this: leaq 0x7b(%rip), %rdi ## literal pool for: "%f\ntoto\n" and not print the new lines which messes up the output. rdar://15145300 llvm-svn: 199407
* [mips][sched] Removed IIXfer. No instructions use it.Daniel Sanders2014-01-161-2/+0
| | | | llvm-svn: 199403
* [mips][sched] Put AND, OR, XOR, MOVT_I, and MOVF_I in the same itinerary ↵Daniel Sanders2014-01-161-5/+5
| | | | | | | | class as their non-microMIPS counterparts. No functional change since both classes have the same InstrItinData definition. llvm-svn: 199402
* Add an emitRawComment function and use it to simplify some uses of EmitRawText.Rafael Espindola2014-01-165-22/+22
| | | | llvm-svn: 199397
* [mips][sched] Split IIseb into II_SEB and II_SEHDaniel Sanders2014-01-164-9/+11
| | | | | | No functional change since there are no InstrItinData's. llvm-svn: 199396
* [mips][sched] Split IILogic into II_AND, II_OR, II_XOR, II_ANDI, II_ORI, II_XORIDaniel Sanders2014-01-163-14/+14
| | | | | | | | This is necessary because the classes are shared between all implementations. No functional change since the InstrItinData's have been duplicated. llvm-svn: 199394
* [mips][sched] Split IIArith in preparation for the first scheduler targeting ↵Daniel Sanders2014-01-165-69/+154
| | | | | | | | | | | | | | | | | | | | | | | a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
* [mips] Correct itin class for MULT_MM and MULTu_MM to IIImult.Daniel Sanders2014-01-161-2/+2
| | | | | | | This matches the itin class used by the non-microMIPS equivalents of these instructions. llvm-svn: 199389
* [mips] IIImult should have an InstrItinData in the generic scheduler. Used ↵Daniel Sanders2014-01-161-0/+1
| | | | | | | | | | | | | the same one as for IIImul. Affects: DMULT, DMULTu, MADD, MADD_MM, MADDU, MADDU_MM, MSUB, MSUB_MM, MSUBU, MSUBU_MM, MULT, MULTu Does not affect MULT_MM, MULTu_MM since they are currently miscategorised as IIImul. llvm-svn: 199381
* ReMat: fix overly cavalier attitude to sub-register indicesTim Northover2014-01-161-24/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two attempted optimisations in reMaterializeTrivialDef, trying to avoid promoting the size of a register too much when rematerializing. Unfortunately, both appear to be flawed. First, we see if the original register would have worked, but this is inadequate. Consider: v1 = SOMETHING (v1 is QQ) v2:Q0 = COPY v1:Q1 (v1, v2 are QQ) ... uses of v2 In this case even though v2 *could* be used directly as the output of SOMETHING, this would set the wrong bits of the QQ register involved. The correct rematerialization must be: v2:Q0_Q1 = SOMETHING (v2 promoted to QQQ) ... uses of v2:Q1_Q2 For the second optimisation, if the correct remat is "v2:idx = SOMETHING" then we can't necessarily expect v2 itself to be valid for SOMETHING, but we do try to hunt for a class between v1 and v2 that works. Unfortunately, this is also wrong: v1 = SOMETHING (v1 is QQ) v2:Q0_Q1 = COPY v1 (v1 is QQ, v2 is QQQ) ... uses of v2 as a QQQ The canonical rematerialization here is "v2:Q0_Q1 = SOMETHING". However current logic would decide that v2 could be a QQ (no interest is taken in later uses). This patch, therefore, always accepts the widened register class without trying to be clever. Generally there is no penalty to this (e.g. in the common GR32 < GR64 case, expanding the width doesn't matter because it's not like you were going to do anything else with the high bits of a GR32 register). It can increase register pressure in cases like the ARM VFP regs though (multiple non-overlapping but equivalent subregisters). This situation can be spotted by the fact that both source and destination in the not-quite-coalesced pair have a sub-register index and rematerialisation is skipped in that situation. Unfortunately, no in-tree targets actually expose this as far as I can tell (there are so few isAsCheapAsAMove instructions for it to trigger on) so I've been unable to produce a test. It was exposed in our ARM64 SPEC tests though, and I will be adding a test there that we should be able to contribute soon(TM). rdar://problem/15775279 llvm-svn: 199376
* [asan] Remove -fsanitize-address-zero-base-shadow command lineEvgeniy Stepanov2014-01-161-22/+14
| | | | | | | | | | | | | | | | flag from clang, and disable zero-base shadow support on all platforms where it is not the default behavior. - It is completely unused, as far as we know. - It is ABI-incompatible with non-zero-base shadow, which means all objects in a process must be built with the same setting. Failing to do so results in a segmentation fault at runtime. - It introduces a backward dependency of compiler-rt on user code, which is uncommon and complicates testing. This is the LLVM part of a larger change. llvm-svn: 199371
* For ARM, fix assertuib failures for some ld/st 3/4 instruction with wirteback.Jiangning Liu2014-01-164-11/+78
| | | | llvm-svn: 199369
* AVX-512: fixed a compare patternElena Demikhovsky2014-01-161-6/+10
| | | | llvm-svn: 199366
* Copy segment register when optimizing to MOV8ao8/MOV16ao16/MOV32ao32.Craig Topper2014-01-161-1/+2
| | | | llvm-svn: 199365
* Allow x86 mov instructions to/from memory with absolute address to be ↵Craig Topper2014-01-168-54/+92
| | | | | | encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
* Use a slightly smaller hack.Rafael Espindola2014-01-161-2/+1
| | | | llvm-svn: 199363
* llmv-objdump/COFF: Print export table contents.Rui Ueyama2014-01-161-3/+95
| | | | | | | | | | | | | | | | This patch adds the capability to dump export table contents. An example output is this: Export Table: Ordinal RVA Name 5 0x2008 exportfn1 6 0x2010 exportfn2 By adding this feature to llvm-objdump, we will be able to use it to check export table contents in LLD's tests. Currently we are doing binary comparison in the tests, which is fragile and not readable to humans. llvm-svn: 199358
* CommentColumn is always 40. Simplify.Rafael Espindola2014-01-162-2/+0
| | | | llvm-svn: 199357
* Reapply r194218 with fix:Bill Wendling2014-01-161-4/+4
| | | | | | | | | | | | Move copying of global initializers below the cloning of functions. The BlockAddress doesn't have access to the correct basic blocks until the functions have been cloned. This causes the BlockAddress to point to the old values. Just wait until the functions have been cloned before copying the initializers. PR13163 llvm-svn: 199354
* Remove use of OpSize for populating VEX_PP field. A prefix encoding is now ↵Craig Topper2014-01-162-20/+8
| | | | | | used instead. Simplify some other code. No functional changes intended. llvm-svn: 199353
* Attempt to fix the MSVC build.Rafael Espindola2014-01-161-0/+2
| | | | llvm-svn: 199352
* BasicAA: We need to check both access sizes when comparing a gep and anArnold Schwaighofer2014-01-161-1/+9
| | | | | | | | underlying object of unknown size. Fixes PR18460. llvm-svn: 199351
* Prevent calls to __jit_debug_register_code from being optimized out.Rafael Espindola2014-01-161-1/+5
| | | | | | Patch by Andrew MacPherson. I just tweaked the comment. llvm-svn: 199350
* Don't use DataRefImpl to implement ImportDirectoryEntryRef.Rui Ueyama2014-01-161-37/+17
| | | | | | | | | DataRefImpl (a union of two integers and a pointer) is not the ideal data type to represent a reference to an import directory entity. We should just use the pointer to the import table and an offset instead to simplify. No functionality change. llvm-svn: 199349
* Report a warning when dropping outdated debug info metadata.Manman Ren2014-01-163-2/+20
| | | | | | Use DiagnosticInfo to emit the warning. llvm-svn: 199346
* Adjust offsets for max load instruction offsets. This is more pessimisticReed Kotler2014-01-162-2/+4
| | | | | | | | | than it needs to be by 1 bit but I need to finish some other things so that all the boundary cases will work in that situation. constpool.c in test-suite will fail to assemble under our new internal test-suite sync without this change. llvm-svn: 199343
* Fix parsing of .symver directive on ARMDavid Peixotto2014-01-151-0/+7
| | | | | | | | | | | | | | | ARM assembly syntax uses @ for a comment, execpt for the second parameter of the .symver directive which requires @ as part of the symbol name. This commit fixes the parsing of this directive by adding a special case for ARM for this one argumnet. To make the change we had to move the AllowAtInIdentifier variable to the MCAsmLexer interface (from AsmLexer) and expose a setter for the value. The ELFAsmParser then toggles this value when parsing the second argument to the .symver directive for a target that uses @ as a comment symbol llvm-svn: 199339
* [LTO] Add a hook to map LLVM diagnostics into the clients of LTO.Quentin Colombet2014-01-151-1/+49
| | | | | | | | | | | | | | | | | | | Add a hook in the C API of LTO so that clients of the code generator can set their own handler for the LLVM diagnostics. The handler is defined like this: typedef void (*lto_diagnostic_handler_t)(lto_codegen_diagnostic_severity_t severity, const char *diag, void *ctxt) - severity says how bad this is. - diag is a string that contains the diagnostic message. - ctxt is the registered context for this handler. This hook is more general than the lto_get_error_message, since this function keeps only the latest message and can only be queried when something went wrong (no warning for instance). <rdar://problem/15517596> llvm-svn: 199338
* Remove support for armv7f slice. <rdar://problem/12478440>Bob Wilson2014-01-151-1/+0
| | | | | | This was never used for anything so we should just get rid of it. llvm-svn: 199337
* [DAGCombiner] Fix a wrong check in method SimplifyVBinOp.Andrea Di Biagio2014-01-151-2/+2
| | | | | | | | | | | | | | | | | | | This fixes a regression intruced by r199135. Revision 199135 tried to simplify part of the logic in method DAGCombiner::SimplifyVBinOp introducing calls to method BuildVectorSDNode::isConstant(). However, that revision wrongly changed the check performed by method SimplifyVBinOp to identify dag nodes that can be folded. Before revision 199135, that method only tried to simplify vector binary operations if both operands were build_vector of Constant/ConstantFP/Undef only. After revision 199135, method SimplifyVBinop tried to simplify also vector binary operations with only one constant operand. This fixes the problem restoring the old behavior of SimplifyVBinOp. llvm-svn: 199328
* Return an ErrorOr<Binary *> from createBinary.Rafael Espindola2014-01-152-34/+29
| | | | | | | | I did write a version returning ErrorOr<OwningPtr<Binary> >, but it is too cumbersome to use without std::move. I will keep the patch locally and submit when we switch to c++11. llvm-svn: 199326
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