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* Fix a performance bug in the Linker.Rafael Espindola2013-05-041-11/+22
| | | | | | | | | | | | | Now that we hava a convinient place to keep it, remeber the set of identified structs as we merge modules. This speeds up the linking of all the bitcode files in clang with the gold plugin and -plugin-opt=emit-llvm (i.e., link only, no codegen) from 5:25 minutes to 13.6 seconds! Patch by Xiaofei Wan! llvm-svn: 181104
* Implement Linker::LinkModules with Linker::linkInModule.Rafael Espindola2013-05-041-8/+9
| | | | | | Flipping which one is the implementation will let us optimize linkInModule. llvm-svn: 181102
* Now that Linker.cpp is almost empty, merge it into LinkModules.cpp.Rafael Espindola2013-05-043-37/+9
| | | | | | Also remove unused includes. llvm-svn: 181100
* Last batch of cleanups to Linker.h.Rafael Espindola2013-05-041-0/+4
| | | | | | | | Update comments, fix * placement, fix method names that are not used in clang, add a linkInModule that takes a Mode and put it in Linker.cpp. llvm-svn: 181099
* Don't construct or delete a module on the Linker.Rafael Espindola2013-05-041-5/+0
| | | | | | | The linker is now responsible only for actually linking the modules, it is up to the clients to create and destroy them. llvm-svn: 181098
* Don't store the context in the Linker.Rafael Espindola2013-05-041-2/+0
| | | | llvm-svn: 181097
* Remove unused members and constructor arguments.Rafael Espindola2013-05-041-11/+5
| | | | llvm-svn: 181096
* Delete dead code from the linker.Rafael Espindola2013-05-041-31/+0
| | | | llvm-svn: 181094
* Use consistent function names.Krzysztof Parzyszek2013-05-043-3/+3
| | | | llvm-svn: 181090
* Tabs to spaces. No functionality change.Nick Lewycky2013-05-041-3/+3
| | | | llvm-svn: 181082
* Revert r181009.Amara Emerson2013-05-032-8/+139
| | | | llvm-svn: 181079
* Remove some uneeded pseudos in the presence of the naked function attribute.Reed Kotler2013-05-031-2/+8
| | | | llvm-svn: 181072
* [PowerPC] Avoid using '$' in generated assembler codeUlrich Weigand2013-05-031-2/+2
| | | | | | | | | | | | PowerPC assemblers are supposed to support a stand-alone '$' symbol as an alternative of '.' to refer to the current PC. This does not work in the LLVM assembler parser yet. To avoid bootstrap failures when using the LLVM assembler as system assembler, this patch modifies the assembler source code generated by LLVM to avoid using '$' (and simply use '.' instead). llvm-svn: 181054
* [PowerPC] Parse platform-specifc variant kinds in AsmParserUlrich Weigand2013-05-031-0/+34
| | | | | | | | | This patch adds support for PowerPC platform-specific variant kinds in MCSymbolRefExpr::getVariantKindForName, and also adds a test case to verify they are translated to the appropriate fixup type. llvm-svn: 181053
* [PowerPC] Add some Book II instructions to AsmParserUlrich Weigand2013-05-032-0/+17
| | | | | | | | | | | | | This patch adds a couple of Book II instructions (isync, icbi) to the PowerPC assembler parser. These are needed when bootstrapping clang with the integrated assembler forced on, because they are used in inline asm statements in the code base. The test case adds the full list of Book II storage control instructions, including associated extended mnemonics. Again, those that are not yet supported as marked as FIXME. llvm-svn: 181052
* [PowerPC] Support extended mnemonics in AsmParserUlrich Weigand2013-05-032-0/+142
| | | | | | | | | | | | This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
* [PowerPC] Add assembler parserUlrich Weigand2013-05-0310-16/+853
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds assembler parser support to the PowerPC back end. The parser will run for any powerpc-*-* and powerpc64-*-* triples, but was tested only on 64-bit Linux. The supported syntax is intended to be compatible with the GNU assembler. The parser does not yet support all PowerPC instructions, but it does support anything that is generated by LLVM itself. There is no support for testing restricted instruction sets yet, i.e. the parser will always accept any instructions it knows, no matter what feature flags are given. Instruction operands will be checked for validity and errors generated. (Error handling in general could still be improved.) The patch adds a number of test cases to verify instruction and operand encodings. The tests currently cover all instructions from the following PowerPC ISA v2.06 Book I facilities: Branch, Fixed-point, Floating-Point, and Vector. Note that a number of these instructions are not yet supported by the back end; they are marked with FIXME. A number of follow-on check-ins will add extra features. When they are all included, LLVM passes all tests (including bootstrap) when using clang -cc1as as the system assembler. llvm-svn: 181050
* Decompose GVN::processNonLocalLoad() (about 400 LOC) into smaller helper ↵Shuxin Yang2013-05-031-169/+194
| | | | | | | | | | | | | | functions. No function change. This function consists of following steps: 1. Collect dependent memory accesses. 2. Analyze availability. 3. Perform fully redundancy elimination, or 4. Perform PRE, depending on the availability Step 2, 3 and 4 are now moved to three helper routines. llvm-svn: 181047
* [mips] Split the DSP control register and define one register for each field ofAkira Hatanaka2013-05-035-191/+258
| | | | | | | | | | | its fields. This removes false dependencies between DSP instructions which access different fields of the the control register. Implicit register operands are added to instructions RDDSP and WRDSP after instruction selection, depending on the value of the mask operand. llvm-svn: 181041
* LoopVectorizer: Add support for if-conversion of PHINodes with 3+ incoming ↵Nadav Rotem2013-05-031-20/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | values. By supporting the vectorization of PHINodes with more than two incoming values we can increase the complexity of nested if statements. We can now vectorize this loop: int foo(int *A, int *B, int n) { for (int i=0; i < n; i++) { int x = 9; if (A[i] > B[i]) { if (A[i] > 19) { x = 3; } else if (B[i] < 4 ) { x = 4; } else { x = 5; } } A[i] = x; } } llvm-svn: 181037
* R600: Expand vector or, shl, srl, and xor nodesTom Stellard2013-05-031-0/+8
| | | | llvm-svn: 181035
* R600: BFI_INT is a vector-only instructionTom Stellard2013-05-031-1/+1
| | | | llvm-svn: 181034
* R600: Add pattern for SHA-256 Ma functionTom Stellard2013-05-033-0/+17
| | | | | | This can be optimized using the BFI_INT instruction. llvm-svn: 181033
* R600: Clean up comments in Processors.tdTom Stellard2013-05-031-5/+1
| | | | llvm-svn: 181032
* RegionInfo: Do not crash if unreachable block is foundTobias Grosser2013-05-031-1/+2
| | | | llvm-svn: 181025
* [SystemZ] Add MCJIT supportRichard Sandiford2013-05-034-0/+113
| | | | | | | | Another step towards reinstating the SystemZ backend. I'll commit the configure changes separately (TARGET_HAS_JIT etc.), then commit a patch to enable the MCJIT tests on SystemZ. llvm-svn: 181015
* [SystemZ] Support System Z as host architectureUlrich Weigand2013-05-031-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The llvm::sys::AddSignalHandler function (as well as related routines) in lib/Support/Unix/Signals.inc currently registers a signal handler routine via "sigaction". When this handler is called due to a SIGSEGV, SIGILL or similar signal, it will show a stack backtrace, deactivate the handler, and then simply return to the operating system. The intent is that the OS will now retry execution at the same location as before, which ought to again trigger the same error condition and cause the same signal to be delivered again. Since the hander is now deactivated, the OS will take its default action (usually, terminate the program and possibly create a core dump). However, this method doesn't work reliably on System Z: With certain signals (namely SIGILL, SIGFPE, and SIGTRAP), the program counter stored by the kernel on the signal stack frame (which is the location where execution will resume) is not the instruction that triggered the fault, but then instruction *after it*. When the LLVM signal handler simply returns to the kernel, execution will then resume at *that* address, which will not trigger the problem again, but simply go on and execute potentially unrelated code leading to random errors afterwards. To fix this, the patch simply goes and re-raises the signal in question directly from the handler instead of returning from it. This is done only on System Z and only for those signals that have this particular problem. llvm-svn: 181010
* Add support for reading ARM ELF build attributes.Amara Emerson2013-05-032-139/+8
| | | | | | | | | | | Build attribute sections can now be read if they exist via ELFObjectFile, and the llvm-readobj tool has been extended with an option to dump this information if requested. Regression tests are also included which exercise these features. Also update the docs with a fixed ARM ABI link and a new link to the Addenda which provides the build attributes specification. llvm-svn: 181009
* [SystemZ] Add llvm::Triple::systemzRichard Sandiford2013-05-031-0/+8
| | | | | | | First step towards reinstating the SystemZ backend. Tests will be included in the main backend patch. llvm-svn: 181007
* X86: Add target description for btver2; make autodetection logic aware of AVX.Benjamin Kramer2013-05-032-4/+14
| | | | llvm-svn: 181005
* Unbreaking the non-x86 build bots by protecting the AVX test code properly.Aaron Ballman2013-05-031-0/+4
| | | | llvm-svn: 180992
* Correctly testing for AVX support in x86 based off code from Hosts.cpp.Aaron Ballman2013-05-031-1/+18
| | | | llvm-svn: 180991
* Fix missing include in Hexagon code for Release+AssertsReid Kleckner2013-05-031-0/+1
| | | | llvm-svn: 180983
* In MC asm parsing, account for the possibility of whitespace withinJohn McCall2013-05-031-18/+22
| | | | | | | | | | | | | | the "identifier" parsed by the frontend callback by skipping forward until we've consumed a token that ends at the point dictated by the callback. In addition, inform the callback when it's parsing an unevaluated operand (e.g. mov eax, LENGTH A::x) as opposed to an evaluated one (e.g. mov eax, [A::x]). This commit depends on a clang commit. llvm-svn: 180978
* [mips] Handle reading, writing or copying of ccond field of DSP controlAkira Hatanaka2013-05-023-1/+60
| | | | | | | | | | | | register. - Define pseudo instructions which store or load ccond field of the DSP control register. - Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack. - Expand the pseudos before callee-scan save. - Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. llvm-svn: 180969
* reverting r180953Jyotsna Verma2013-05-025-305/+404
| | | | llvm-svn: 180964
* R600: Signed literals are 64bits wideVincent Lejeune2013-05-021-3/+3
| | | | llvm-svn: 180960
* R600: If previous bundle is dot4, PV valid chan is always XVincent Lejeune2013-05-021-38/+51
| | | | llvm-svn: 180959
* R600: Improve asmPrint of ALU clauseVincent Lejeune2013-05-023-4/+20
| | | | llvm-svn: 180957
* R600: Prettier asmPrint of AluVincent Lejeune2013-05-024-13/+45
| | | | llvm-svn: 180956
* Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.Jyotsna Verma2013-05-025-404/+305
| | | | llvm-svn: 180953
* [GV] Remove dead code which is really difficult to decipher.Shuxin Yang2013-05-021-26/+2
| | | | | | | | | | | Actually it took me couple of hours trying to make sense of them and only to find they are dead code. I guess the original author used "allSingleSucc" to indicate if there are any critial edge emanating from some blocks, and tried to perform code motion (actually speculation) in the presence of these critical edges; but later on he/she changed mind and decided to perform edge-splitting first. llvm-svn: 180951
* Hexagon - Add peephole optimizations for zero extends.Pranav Bhandarkar2013-05-022-0/+40
| | | | | | | | | | | | * lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a sequence of a pair of i32->i64 extensions followed by a "bitwise or" into COMBINE_rr. * lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg. * test/CodeGen/Hexagon/union-1.ll: New test. * test/CodeGen/Hexagon/combine_ir.ll: Fix test. llvm-svn: 180946
* [mips] Fix the head Mips16RegisterInfo.cpp commentRichard Sandiford2013-05-021-2/+1
| | | | | | ...aka a test commit. llvm-svn: 180936
* Hexagon: Honor __builtin_expect by using branch probabilities.Jyotsna Verma2013-05-024-37/+122
| | | | | | | | | | | | | * lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp): Given a jump opcode return the right pred.new jump opcode with a taken vs not-taken hint based on branch probabilities provided by the target independent module. * lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function. * lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode): Enhance existing function use branch probabilities like HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps. llvm-svn: 180923
* R600: Use new tablegen syntax for patternsTom Stellard2013-05-023-447/+381
| | | | | | | | All but two patterns have been converted to the new syntax. The remaining two patterns will require COPY_TO_REGCLASS instructions, which the VLIW DAG Scheduler cannot handle. llvm-svn: 180922
* R600/SI: remove nonsense select patternTom Stellard2013-05-021-8/+1
| | | | | | | | Fortunately this pattern never matched, otherwise we would have generated incorrect code. Signed-off-by: Christian K??nig <christian.koenig@amd.com> llvm-svn: 180921
* 80-col fixup.Michael Liao2013-05-021-2/+3
| | | | llvm-svn: 180915
* Avoid duplicating logic on frame register selecting when lowering eh_returnMichael Liao2013-05-021-9/+11
| | | | | | No functionality change llvm-svn: 180914
* Avoid duplicating logic on frame register selecting when lowering frameaddrMichael Liao2013-05-021-1/+3
| | | | | | No functionality change llvm-svn: 180912
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