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* [COFF] Improve correctness of def parsing for GNU featuresMartin Storsjo2018-05-093-12/+20
| | | | | | | | | | | | | | | | | | | | | | | | The operator == used for exporting a function with a different name in the DLL compared to the name in the import library (which is useful for adding linker level aliases for function in the import library) is a feature distinct and different from the operator = used for exporting a function with a different name (both in import library and DLL) than in the implementation producing the DLL. When creating an import library using dlltool, from a def file that contains forwards (Func = OtherDll.Func), this shouldn't affect the produced import library, which should still behave just as if it was a normal exported function. This clears a lot of confusion and subtle misunderstandings, and avoids a parameter that was used to avoid creating weak aliases when invoked from lld. (This parameter was added previously due to the existing conflation of the two features.) Differential Revision: https://reviews.llvm.org/D46245 llvm-svn: 331859
* [MergedLoadStoreMotion] Fix a debug invariant bug in mergeStoresBjorn Pettersson2018-05-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Summary: MergedLoadStoreMotion::mergeStores is using some heuristics to limit the amount of stores that it tries to sink (see MagicCompileTimeControl in MergedLoadStoreMotion.cpp). The heuristic involves counting the number of instructions in one of the basic blocks that is part of the transformation. We now ignore dbg intrinsics when counting instruction for the MagicCompileTimeControl heuristic. This to make sure that the amount of stores that are sunk doesn't depend on the amount of debug information (if -g is used or not). Reviewers: Gerolf, davide, majnemer Reviewed By: davide Subscribers: dberlin, bjope, aprantl, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D46600 llvm-svn: 331852
* [InstCombine] snprintf optimizationsDavid Bolvansky2018-05-091-0/+90
| | | | | | | | | | | | Reviewers: spatel, efriedma, majnemer, rja Reviewed By: rja Subscribers: rja, llvm-commits Differential Revision: https://reviews.llvm.org/D46285 llvm-svn: 331849
* [X86] Combine (vXi1 (bitcast (-1)))) and (vXi1 (bitcast (0))) to all ones or ↵Craig Topper2018-05-091-0/+10
| | | | | | all zeros vXi1 vector. llvm-svn: 331847
* Revert r331816 and r331820 - [globalisel] Add a combiner helpers for ↵Daniel Sanders2018-05-095-146/+1
| | | | | | | | | | extending loads and use them in a pre-legalize combiner for AArch64 Reverting this to see if the clang-cmake-aarch64-global-isel and clang-cmake-aarch64-quick bots are failing because of this commit. We know it wasn't r331819. llvm-svn: 331846
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-09103-212/+225
| | | | | | | | | | | | | | | | | | Because we create a new kind of debug instruction, DBG_LABEL, we need to check all passes which use isDebugValue() to check MachineInstr is debug instruction or not. When expelling debug instructions, we should expel both DBG_VALUE and DBG_LABEL. So, I create a new function, isDebugInstr(), in MachineInstr to check whether the MachineInstr is debug instruction or not. This patch has no new test case. I have run regression test and there is no difference in regression test. Differential Revision: https://reviews.llvm.org/D45342 Patch by Hsiangkai Wang. llvm-svn: 331844
* [DebugInfo] Convert intrinsic llvm.dbg.label to MachineInstr.Shiva Chen2018-05-099-0/+141
| | | | | | | | | | | | | | | | | | | | | In order to convert LLVM IR to MachineInstr, we need a new TargetOpcode, DBG_LABEL, to ‘lower’ intrinsic llvm.dbg.label. The patch creates this new TargetOpcode and convert intrinsic llvm.dbg.label to MachineInstr through SelectionDAG. In SelectionDAG, debug information is stored in SDDbgInfo. We create a new data member of SDDbgInfo for labels and use the new data member, SDDbgLabel, to create DBG_LABEL MachineInstr. The new DBG_LABEL MachineInstr uses label metadata from LLVM IR as its parameter. So, the backend could get metadata information of labels from DBG_LABEL MachineInstr. Differential Revision: https://reviews.llvm.org/D45341 Patch by Hsiangkai Wang. llvm-svn: 331842
* [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.Shiva Chen2018-05-0915-40/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to set breakpoints on labels and list source code around labels, we need collect debug information for labels, i.e., label name, the function label belong, line number in the file, and the address label located. In order to keep these information in LLVM IR and to allow backend to generate debug information correctly. We create a new kind of metadata for labels, DILabel. The format of DILabel is !DILabel(scope: !1, name: "foo", file: !2, line: 3) We hope to keep debug information as much as possible even the code is optimized. So, we create a new kind of intrinsic for label metadata to avoid the metadata is eliminated with basic block. The intrinsic will keep existing if we keep it from optimized out. The format of the intrinsic is llvm.dbg.label(metadata !1) It has only one argument, that is the DILabel metadata. The intrinsic will follow the label immediately. Backend could get the label metadata through the intrinsic's parameter. We also create DIBuilder API for labels to be used by Frontend. Frontend could use createLabel() to allocate DILabel objects, and use insertLabel() to insert llvm.dbg.label intrinsic in LLVM IR. Differential Revision: https://reviews.llvm.org/D45024 Patch by Hsiangkai Wang. llvm-svn: 331841
* Revert r331819 [GlobalISel][Legalizer] More concise and faster widenScalar, NFCRoman Tereshin2018-05-092-144/+236
| | | | | | | Reverting this to see if the clang-cmake-aarch64-global-isel and clang-cmake-aarch64-quick bots are failing because of this commit llvm-svn: 331839
* [RuntimeDyld][MachO] Properly handle thumb to thumb calls within a section.Lang Hames2018-05-091-1/+19
| | | | | | | | | | | Previously thumb bits were only checked for external relocations (thumb to arm code and vice-versa). This patch adds detection for thumb callees in the same section asthe (also thumb) caller. The MachO/Thumb test case is updated to cover this, and redundant checks (handled by the MachO/ARM test) are removed. llvm-svn: 331838
* Support a funclet operand bundle in LowerInvokeHeejin Ahn2018-05-091-2/+4
| | | | | | | | | | | | | | | | | Summary: The current LowerInvoke pass cannot handle invoke instructions with a funclet bundle operand. The order of operands for an invoke instruction is {call arguments, callee, funclet operand (if any), normal dest, unwind dest}. The current code assumes there is no funclet operand and incorrectly includes a funclet operand into call arguments. Reviewers: rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46242 llvm-svn: 331832
* [SimplifyCFG] Fix a crash when folding PHIs.Davide Italiano2018-05-081-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | We enter MergeBlockIntoPredecessor with a block looking like this: for.inc.us-lcssa: ; preds = %cond.end %k.1.lcssa.ph = phi i32 [ %conv15, %cond.end ] %t.3.lcssa.ph = phi i32 [ %k.1.lcssa.ph, %cond.end ] br label %for.inc, !dbg !66 [note the first arg of the PHI being a PHI]. FoldSingleEntryPHINodes gets rid of both PHIs (calling, eraseFromParent). But right before we call the function, we push into IncomingValues the only argument of the PHIs, and shortly after we try to iterate over something which has been invalidated before :( The fix its not trying to remove PHIs which have an incoming value coming from the same BB we're looking at. Fixes PR37300 and rdar://problem/39910460 Differential Revision: https://reviews.llvm.org/D46568 llvm-svn: 331824
* MC: Remove dead code. NFCI.Peter Collingbourne2018-05-081-1/+0
| | | | | | We should never emit an SHT_DYNSYM into an object file. llvm-svn: 331821
* [globalisel] Correct r331816 to check the opcode before calling getOperand().Daniel Sanders2018-05-081-4/+4
| | | | | | | | | Fix a silly mistake in my pre-commit changes for r331816. It should check what opcode the insn is before extracting the operands. NFC at the moment since the caller already checked the opcode. llvm-svn: 331820
* [GlobalISel][Legalizer] More concise and faster widenScalar, NFCRoman Tereshin2018-05-082-236/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactoring LegalizerHelper::widenScalar member function reducing its size by approximately a factor of 2 and (hopefuly) making it more straightforward and regular by introducing widenScalarSrc and widenScalarDst helper methods. The new widenScalar* methods mutate the instructions in place instead of recreating them from scratch and removing the originals. The compile time implications of this were measured on sqlite3 amalgamation, targeting AArch64 in -O0: LegalizerHelper::widenScalar: > 25% faster Legalizer::runOnMachineFunction: ~ 4.0 - 4.5% faster Also adding MachineOperand::setCImm and refactoring out MachineIRBuilder::recordInsertion methods to make the change possible. Reviewers: aditya_nandakumar, bogner, javed.absar, t.p.northover, ab, dsanders, arsenm Reviewed By: aditya_nandakumar Subscribers: wdng, rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46414 llvm-svn: 331819
* [globalisel] Add a combiner helpers for extending loads and use them in a ↵Daniel Sanders2018-05-085-1/+146
| | | | | | | | | | | | | | | | pre-legalize combiner for AArch64 Summary: Depends on D45541 Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar, aemerson Reviewed By: aemerson Subscribers: aemerson, rengolin, mgorny, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45543 llvm-svn: 331816
* Revert "[X86][CET] Shadow stack fix for setjmp/longjmp"Jessica Paquette2018-05-082-251/+5
| | | | | | | | | | | | This reverts commit 30962eca38ef02666ebcdded72a94f2cd0292d68. This commit has been causing test asan failures on a build bot. http://green.lab.llvm.org/green/job/clang-stage1-configure-RA/45108/ Original commit: https://reviews.llvm.org/D46181 llvm-svn: 331813
* [AsmPrinter] Allow emitting codeview for any windows targetMartin Storsjo2018-05-081-2/+1
| | | | | | | | | | | | | | | | Before SVN r244158, codeview debug info was emitted always emitted for msvc if debug info was enabled, but that commit added a module flag. Since it's still restricted by the flag, we can allow it for any target if the user requests it, not only msvc (and windows-itanium, added in SVN r287567). Add a test for emitting it for a mingw target. Differential Revision: https://reviews.llvm.org/D46303 llvm-svn: 331809
* [Coverage] Take filenames into account when loading function records.Max Moroz2018-05-081-2/+4
| | | | | | | | | | | | | | | | | | | | Summary: Don't skip functions with the same name but from different files. That change makes it possible to generate code coverage reports from different binaries compiled from different sources even if there are functions with non-unique names. Without that change, code coverage for such functions is missing except of the first function processed. Reviewers: vsk, morehouse Reviewed By: vsk Subscribers: llvm-commits, kcc Differential Revision: https://reviews.llvm.org/D46478 llvm-svn: 331801
* [LV] Fix for PR37248, Broadcast codegen incorrectly assumed vector loop body ↵Hideki Saito2018-05-081-5/+7
| | | | | | | | | | | | | | | | | | | is single basic block Summary: Broadcast code generation emitted instructions in pre-header, while the instruction they are dependent on in the vector loop body. This resulted in an IL verification error ---- value used before defined. Reviewers: rengolin, fhahn, hfinkel Reviewed By: rengolin, fhahn Subscribers: dcaballe, Ka-Ka, llvm-commits Differential Revision: https://reviews.llvm.org/D46302 llvm-svn: 331799
* [AMDGPU] Provide machine -> name mappingTim Renouf2018-05-082-51/+70
| | | | | | | | | | | | | | | Summary: AMDGPU stores a numerical code for the particular GPU variant in EFlags in the ELF file. This commit provides a mapping from that number into the machine name for use by objdump-type tools. Change-Id: Id37fc0bebad443bd89c0080985ce298c4e7e9319 Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D46587 llvm-svn: 331798
* [Power9]Legalize and emit code for truncate and convert QP to HW and ByteLei Huang2018-05-081-2/+14
| | | | | | | | | Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
* AMDGPU: Fix broken dynamic vector indexing for packed typesMatt Arsenault2018-05-081-4/+4
| | | | | | The intention of this was to multiply by 16, not shift by 16. llvm-svn: 331793
* DAG: Use correct shift width typeMatt Arsenault2018-05-081-1/+1
| | | | llvm-svn: 331792
* [Power9]Legalize and emit code for truncate and convert Quad-Precision to WordLei Huang2018-05-081-0/+10
| | | | | | | | | | | Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
* AMDGPU: Use eraseFromParent to delete am instruction when it is no longer ↵Changpeng Fang2018-05-081-3/+6
| | | | | | | | | | | needed. Reviewer: Nicolai Differential Revision: https://reviews.llvm.org/D46438 llvm-svn: 331788
* [Power9]Legalize and emit code for truncate and convert QP to DWLei Huang2018-05-082-2/+27
| | | | | | | | | | | Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
* [CodeGenPrepare] Move Extension Instructions Through Logical And Shift ↵Guozhi Wei2018-05-081-0/+41
| | | | | | | | | | Instructions CodeGenPrepare pass move extension instructions close to load instructions in different BB, so they can be combined later. But the extension instructions can't move through logical and shift instructions in current implementation. This patch enables this enhancement, so we can eliminate more extension instructions. Differential Revision: https://reviews.llvm.org/D45537 llvm-svn: 331783
* [PowerPC] Unify handling for conversion of FP_TO_INT feeding a storeLei Huang2018-05-084-56/+149
| | | | | | | | | | | | Existing DAG combine only handles conversions for FP_TO_SINT: "{f32, f64} x { i32, i16 }" This patch simplifies the code to handle: "{ FP_TO_SINT, FP_TO_UINT } x { f64, f32 } x { i64, i32, i16, i8 }" Differential Revision: https://reviews.llvm.org/D46102 llvm-svn: 331778
* [AMDGPU] Added checks for dpp_ctrl valueStanislav Mekhanoshin2018-05-084-36/+99
| | | | | | | | | | | | - Report error for invalid dpp_ctrl values. - Changed the way it is reported, now the error will be emitted into asm and will work with release build as well. - Added dpp_ctrl value verifier for codegen. - Added symbolic constants for dpp_ctrl. Differential Revision: https://reviews.llvm.org/D46565 llvm-svn: 331775
* [X86] Tag PCONFIG instruction with WriteSystem scheduler classSimon Pilgrim2018-05-081-0/+2
| | | | llvm-svn: 331773
* [mips][msa] Pattern match the splat.d instructionStefan Maksimovic2018-05-082-11/+32
| | | | | | | | | | | Introduced a new pattern for matching splat.d explicitly. Both splat.d and splati.d can now be generated from the @llvm.mips.splat.d intrinsic depending on whether an immediate value has been passed. Differential Revision: https://reviews.llvm.org/D45683 llvm-svn: 331771
* [X86] Split off WriteIMul64 from WriteIMul schedule class (PR36931)Simon Pilgrim2018-05-0811-105/+84
| | | | | | | This fixes a couple of BtVer2 missing instructions that weren't been handled in the override. NOTE: There are still a lot of overrides that still need cleaning up! llvm-svn: 331770
* [X86] Split WriteIDiv into div/idiv 8/16/32/64 implementations (PR36930)Simon Pilgrim2018-05-0811-130/+113
| | | | | | | I've created the necessary classes but there are still a lot of overrides that need cleaning up. NOTE: The Znver1 model was missing some div/idiv variants in the instregex patterns and wasn't setting the resource cycles at all in the overrides. llvm-svn: 331767
* [X86] Add vector masked load/store scheduler classes (PR32857)Simon Pilgrim2018-05-0811-247/+163
| | | | | | Split off from existing vector load/store classes to remove InstRW overrides. llvm-svn: 331760
* [AArch64][SVE] Asm: Support for LD1R load-and-replicate scalar instructions.Sander de Smalen2018-05-084-1/+93
| | | | | | | | | | Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46251 llvm-svn: 331758
* [X86] Add SchedWriteFTest/SchedWriteVecTest TEST scheduler classesSimon Pilgrim2018-05-0811-195/+75
| | | | | | Split off from SchedWriteVecLogic to remove InstRW overrides. llvm-svn: 331757
* [mips] Mark various memory instructions as being in microMIPS (NFC)Simon Dardis2018-05-081-10/+9
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46388 llvm-svn: 331756
* [AArch64] Disallow vector operand if FPR128 Q register is required.Sander de Smalen2018-05-083-206/+225
| | | | | | | | | | | | | | | | | | | | | | | | | Patch https://reviews.llvm.org/D41445 changed the behaviour of 'isReg()' to also return 'true' if the parsed register operand is a vector register. Code in the AsmMatcher checks if a register is a subclass of the expected register class. However, even though both parsed registers map to the same physical register, the 'v' register is of kind 'NeonVector', where 'q' is of type Scalar, where isSubclass() does not distinguish between the two cases. The solution is to use an AsmOperand instead of the register directly, and use the PredicateMethod to distinguish the two operands. This fixes for example: ldr v0, [x0] // 'v0' is an invalid operand for this instruction ldr q0, [x0] // valid Reviewers: aemerson, Gerolf, SjoerdMeijer, javed.absar Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D46310 llvm-svn: 331755
* [mips] Correct clo/clz predicatesSimon Dardis2018-05-082-22/+19
| | | | | | | | Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46125 llvm-svn: 331754
* [X86] Mark all byval parameters as aliasedJeremy Morse2018-05-081-1/+5
| | | | | | | | | | | | | | | This is a fix for PR30290: by marking all byval stack slots as being aliased, the instruction scheduler is more conservative about rescheduling memory accesses to such stack slots as an LLVM Value* might alias it. This fixes errors such as in the patched test case, where reads and writes to a data structure are illegally mixed. This could be fixed better in the future with better analysis for the instruction scheduler to know what Values alias what stack slots. Differential Revision: https://reviews.llvm.org/D45022 llvm-svn: 331749
* [X86][CET] Shadow stack fix for setjmp/longjmpAlexander Ivchenko2018-05-082-5/+251
| | | | | | | | | | | | This patch adds a shadow stack fix when compiling setjmp/longjmp with the shadow stack enabled. This allows setjmp/longjmp to work correctly with CET. Patch by mike.dvoretsky Differential Revision: https://reviews.llvm.org/D46181 llvm-svn: 331748
* Object: Find terminator correctly when reading long filenames in GNU ↵Hans Wennborg2018-05-081-4/+8
| | | | | | | | | | | | archives (PR37244) The code was previously relying on there being a null terminator somewhere in (or after) the string table, something made less likely by r330786. Differential Revision: https://reviews.llvm.org/D46527 llvm-svn: 331746
* [x86] Introduce the enclv instructionGabor Buella2018-05-083-1/+7
| | | | | | | | | | | | | | Summary: and use the -msgx flag as a requirement for the SGX instructions. Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46436 llvm-svn: 331742
* [LCSSA] Do not remove used PHI nodes in formLCSSAForInstructionsBjorn Pettersson2018-05-081-5/+10
| | | | | | | | | | | | | | | | | | | | | | | Summary: In formLCSSAForInstructions we speculatively add new PHI nodes, that sometimes ends up without having any uses. It has been discovered that sometimes an added PHI node can appear as being unused in one iteration of the Worklist, although it can end up being used by a PHI node added in a later iteration. We now check, a second time, that the PHI node still is unused before we remove it. This avoids an assert about "Trying to remove a phi with uses." for the added test case. Reviewers: davide, mzolotukhin, mattd, dberlin Reviewed By: mzolotukhin, dberlin Subscribers: dberlin, mzolotukhin, davide, bjope, uabelho, llvm-commits Differential Revision: https://reviews.llvm.org/D46422 llvm-svn: 331741
* [x86] Introduce the pconfig instructionGabor Buella2018-05-086-0/+38
| | | | | | | | | | Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46430 llvm-svn: 331739
* [DebugInfo] Accept `S` in augmentation strings in CIE.Fangrui Song2018-05-081-0/+3
| | | | | | glibc libc.a(sigaction.o) compiled from sysdeps/unix/sysv/linux/x86_64/sigaction.c uses "zRS". llvm-svn: 331738
* [MachineVerifier][GlobalISel] Verifying generic extends and truncatesRoman Tereshin2018-05-081-0/+52
| | | | | | | | | | | | | | | | | Making sure we don't truncate / extend pointers, don't try to change vector topology or bitcast vectors to scalars or back, and most importantly, don't extend to a smaller type or truncate to a large one. Reviewers: qcolombet t.p.northover aditya_nandakumar Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46490 llvm-svn: 331718
* [MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)Roman Tereshin2018-05-081-13/+20
| | | | | | | | | | | | | | MIParser wasn't able to parse LLTs like `<4 x p0>`, fixing that. Reviewers: qcolombet t.p.northover aditya_nandakumar Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46490 llvm-svn: 331712
* [NewPM] Emit inliner NoDefinition missed optimization remarkTeresa Johnson2018-05-081-1/+18
| | | | | | | | | | | | Summary: Makes this consistent with the old PM. Reviewers: eraman Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D46526 llvm-svn: 331709
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