| Commit message (Collapse) | Author | Age | Files | Lines |
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This is not supposed to happen, but I have seen the x86 rematter getting
confused when rematerializing partial redefs.
llvm-svn: 127857
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and early clobbers.
Assert when trying to find an undefined value.
llvm-svn: 127856
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llvm-svn: 127853
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comparisons on x86. Essentially, the way this works is that SUB+SBB sets
the relevant flags the same way a double-width CMP would.
This is a substantial improvement over the generic lowering in LLVM. The output
is also shorter than the gcc-generated output; I haven't done any detailed
benchmarking, though.
llvm-svn: 127852
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be used to release resources during a crash.
llvm-svn: 127849
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Remove the offending logic and update the test cases.
llvm-svn: 127843
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sneak in my last checkin.
llvm-svn: 127842
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llvm-svn: 127840
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SCEV may generate expressions composed of multiple pointers, which can
lead to invalid GEP expansion. Until we can teach SCEV to follow strict
pointer rules, make sure no bad GEPs creep into IR.
Fixes rdar://problem/9038671.
llvm-svn: 127839
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llvm-svn: 127837
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instead of copying.
llvm-svn: 127835
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This is done by lowering dbg.declare intrinsic into dbg.value intrinsic.
Radar 9143931.
llvm-svn: 127834
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o A8.6.195 STR (register) -- Encoding T1
o A8.6.193 STR (immediate, Thumb) -- Encoding T1
It has been changed so that now they use different addressing modes
and thus different MC representation (Operand Infos). Modify the
disassembler to reflect the change, and add relevant tests.
llvm-svn: 127833
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llvm-svn: 127832
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multiplied value by introducing an early shift.
This allows us to compile "unsigned foo(unsigned x) { return x/28; }" into
shrl $2, %edi
imulq $613566757, %rdi, %rax
shrq $32, %rax
ret
instead of
movl %edi, %eax
imulq $613566757, %rax, %rcx
shrq $32, %rcx
subl %ecx, %eax
shrl %eax
addl %ecx, %eax
shrl $4, %eax
on x86_64
llvm-svn: 127829
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bits that are known zero in the divided number.
This will come in handy soon.
llvm-svn: 127828
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components.
I have convinced myself that it can only happen when a phi value dies. When it
happens, allocate new virtual registers for the components.
llvm-svn: 127827
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llvm-svn: 127821
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been removed.
llvm-svn: 127812
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llvm-svn: 127809
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llvm-svn: 127807
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llvm-svn: 127801
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llvm-svn: 127788
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llvm-svn: 127786
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While here, add VK_ARM_TPOFF and VK_ARM_GOTTPOFF, too.
llvm-svn: 127780
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llvm-svn: 127779
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The register allocator needs to adjust its live interval unions when that happens.
llvm-svn: 127774
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llvm-svn: 127773
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register number.
The live range of a virtual register may change which invalidates the cached
interference information.
llvm-svn: 127772
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llvm-svn: 127771
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rather than an int. Thankfully, this only causes LLVM to miss optimizations, not
generate incorrect code.
This just fixes the zext at the return. We still insert an i32 ZextAssert when
reading a function's arguments, but it is followed by a truncate and another i8
ZextAssert so it is not optimized.
llvm-svn: 127766
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llvm-svn: 127764
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plus the test where it used to break.", which broke Clang self-host of a
Debug+Asserts compiler, on OS X.
llvm-svn: 127763
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llvm-svn: 127761
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where it used to break.
llvm-svn: 127757
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can event.
llvm-svn: 127741
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llvm-svn: 127728
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called at dtor context.
report_fatal_error() invokes exit(). We know report_fatal_error() might not write messages to stderr when any errors were detected on FD == 2.
llvm-svn: 127726
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FIXME: It is a temporal hack. We should detect as many "special file name" as possible.
llvm-svn: 127724
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for workaround.
FIXME: We should use sys::fs::unique_file() in future.
llvm-svn: 127723
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llvm-svn: 127721
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llvm-svn: 127720
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chose is having a non-memcpy/memset use and being larger than any native integer
type. Originally I chose having an access of a size smaller than the total size
of the alloca, but this caused some minor issues on the spirit benchmark where
SRoA runs again after some inlining.
This fixes <rdar://problem/8613163>.
llvm-svn: 127718
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llvm-svn: 127716
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llvm-svn: 127715
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1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
Modify the ARMDisassemblerCore.cpp file to accomodate the change.
2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:
imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
// Encoding A1
It has no business doing such. Removed the offending logic.
Add test cases to arm-tests.txt.
llvm-svn: 127707
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llvm-svn: 127705
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accept. If a value in the mask is out of range, it uses the value 0, for VTBL,
or leaves the value unchanged, for VTBX.
llvm-svn: 127700
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defs.
After live range splitting, an original value may be available in multiple
registers. Tracing back through the registers containing the same value, find
the best place to insert a spill, determine if the value has already been
spilled, or discover a reaching def that may be rematerialized.
This is only the analysis part. The information is not used for anything yet.
llvm-svn: 127698
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llvm-svn: 127697
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