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* COFF: Implement sectionContainsSymbol for relocatable files only.Michael J. Spencer2011-10-131-2/+8
| | | | llvm-svn: 141884
* Fix memory corruption I introduced a few checkins ago.Andrew Trick2011-10-131-5/+6
| | | | | | Self-review easily caught this obvious bug. llvm-svn: 141880
* SETEND is not allowed in an IT block.Owen Anderson2011-10-131-0/+1
| | | | llvm-svn: 141874
* Revert r141870. The test case crashes on linux with data corruption. A ↵Andrew Trick2011-10-131-14/+2
| | | | | | deeper issue was exposed. llvm-svn: 141873
* LSR: Reuse the post-inc expansion of expressions.Andrew Trick2011-10-131-2/+14
| | | | | | | | This avoids unnecessary expansion of expressions and allows the SCEV expander to work on expression DAGs, not just trees. Fixes PR11090. llvm-svn: 141870
* SCEV: Rewrite TrandformForPostIncUse to handle expression DAGs, notAndrew Trick2011-10-131-30/+70
| | | | | | | | just expression trees. Partially fixes PR11090. Test case will be with the full fix. llvm-svn: 141868
* Slightly more useful tracing.Andrew Trick2011-10-131-1/+2
| | | | llvm-svn: 141867
* Mark 'branch indirect' instruction as an indirect branch.Kalle Raiskila2011-10-131-2/+4
| | | | | | Not having it confused assembly printing of jumptables. llvm-svn: 141862
* More closely follow libgcc, which has code after the `ret' instruction toBill Wendling2011-10-131-5/+24
| | | | | | | release the stack segment and reset the stack pointer. Place the code in its own MBB to make the verifier happy. llvm-svn: 141859
* Revert r141854 because it was causing failures:Bill Wendling2011-10-134-52/+5
| | | | | | | | | | | | | | | http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101 --- Reverse-merging r141854 into '.': U test/MC/Disassembler/X86/x86-32.txt U test/MC/Disassembler/X86/simple-tests.txt D test/CodeGen/X86/bmi.ll U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86.td U lib/Target/X86/X86Subtarget.h llvm-svn: 141857
* Should not add instructions to a BB after a return instruction. The machine ↵Bill Wendling2011-10-131-1/+2
| | | | | | instruction verifier doesn't like this, nor do I. llvm-svn: 141856
* Use an existing method.Cameron Zwarich2011-10-131-1/+1
| | | | llvm-svn: 141855
* Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper2011-10-134-5/+52
| | | | | | processor which is gcc's name for Haswell. llvm-svn: 141854
* Add 'implicit EFLAGS' to patterns for popcnt and lzcntCraig Topper2011-10-132-12/+23
| | | | llvm-svn: 141853
* Elf_Word is not POD! Stop using it in a DenseMap.Nick Lewycky2011-10-131-7/+4
| | | | llvm-svn: 141851
* If MI is deleted then remove it from the set. If a new MI is created, it couldNick Lewycky2011-10-131-0/+2
| | | | | | | have the same address as the one we deleted, and we don't want that in the set yet. Noticed by inspection. llvm-svn: 141849
* Tabs to spaces.Nick Lewycky2011-10-131-2/+2
| | | | llvm-svn: 141844
* Add missing braces to pacify GCC's -Wparentheses.Nick Lewycky2011-10-131-1/+2
| | | | llvm-svn: 141842
* Also inflate register classes around inline asm.Jakob Stoklund Olesen2011-10-121-4/+1
| | | | | | | | | | Now that MI->getRegClassConstraint() can also handle inline assembly, don't bail when recomputing the register class of a virtual register used by inline asm. This fixes PR11078. llvm-svn: 141836
* Add MachineInstr::getRegClassConstraint().Jakob Stoklund Olesen2011-10-121-0/+33
| | | | | | | | | Most instructions have some requirements for their register operands. Usually, this is expressed as register class constraints in the MCInstrDesc, but for inline assembly the constraints are encoded in the flag words. llvm-svn: 141835
* Extract a method for finding the inline asm flag operand.Jakob Stoklund Olesen2011-10-121-30/+38
| | | | llvm-svn: 141834
* Encode register class constreaints in inline asm instructions.Jakob Stoklund Olesen2011-10-122-8/+29
| | | | | | | | | | | | | The inline asm operand constraint is initially encoded in the virtual register for the operand, but that register class may change during coalescing, and the original constraint is lost. Encode the original register class as part of the flag word for each inline asm operand. This makes it possible to recover the actual constraint required by inline asm, just like we can for normal instructions. llvm-svn: 141833
* We need to verify that the machine instruction we're using as a replacement forBill Wendling2011-10-121-0/+11
| | | | | | | | | | our current machine instruction defines a register with the same register class as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it would ICE because a tail call was expecting one register class but was given another. (The machine instruction verifier catches this situation.) <rdar://problem/10270968> llvm-svn: 141830
* Use a utility from MathExtras to clarify a check and avoid undefined ↵Eli Friedman2011-10-121-1/+1
| | | | | | behavior. Based on patch by Ahmed Charles. llvm-svn: 141829
* The VMAs stored in the symbol table of a MachO file are absolute addresses, ↵Owen Anderson2011-10-121-9/+9
| | | | | | not offsets from the section. llvm-svn: 141828
* Don't label a STAB debugging symbol as a function symbol.Owen Anderson2011-10-121-0/+5
| | | | llvm-svn: 141824
* sectionContainsSymbol needs to be based on VMA's rather than section indices ↵Owen Anderson2011-10-121-2/+17
| | | | | | to properly account for files with segment load commands that contain no sections. llvm-svn: 141822
* Fix a couple hash functions so that they do not depend on undefined shifts. ↵Eli Friedman2011-10-121-2/+2
| | | | | | Based on patch by Ahmed Charles. llvm-svn: 141820
* ARM addrmode5 represents the 'U' bit of the encoding backwards.Jim Grosbach2011-10-121-14/+17
| | | | | | | The disassembler needs to use the AM5 factory methods instead of just building up the immediate directly. llvm-svn: 141819
* Fix APFloat::getSmallestNormalized so the shift doesn't depend on undefined ↵Eli Friedman2011-10-121-1/+1
| | | | | | behavior. Patch from Ahmed Charles. llvm-svn: 141818
* Fix APFloat::getLargest so that it actually returns the correct value. ↵Eli Friedman2011-10-121-2/+3
| | | | | | Found by accident while reviewing a patch to nearby code. llvm-svn: 141816
* Section indices in MachO symbol tables begin at 1, not 0.Owen Anderson2011-10-121-1/+1
| | | | llvm-svn: 141815
* Finish supporting cpp #file/line comments in assembler for error messages. SoKevin Enderby2011-10-121-5/+64
| | | | | | | | for cpp pre-processed assembly we give correct filename and line numbers when reporting errors in assembly files when using clang and -integrated-as on .s files. rdar://8998895 llvm-svn: 141814
* Disable machine LICM speculation check (for profitability) until I have time ↵Evan Cheng2011-10-121-6/+15
| | | | | | to investigate the regressions. llvm-svn: 141813
* To find the exiting VN of a LiveInterval from a block, use the previous slotCameron Zwarich2011-10-121-1/+1
| | | | | | | | | | | rather than the previous index. If a block has a single instruction, the previous index may be in a different basic block. I have no clue how this used to work on all of test-suite, because now this failure is seen quite often when trying to compile code with -strong-phi-elim. This fixes PR10252. llvm-svn: 141812
* Thumb2 assembly parsing and encoding for LDC/STC.Jim Grosbach2011-10-123-99/+116
| | | | llvm-svn: 141811
* Hoist vector.size() computation out of the loop. No functionality change.Nick Lewycky2011-10-121-1/+2
| | | | llvm-svn: 141807
* addrmode2 is gone from these, so no need for the reg0 operand.Jim Grosbach2011-10-121-24/+0
| | | | llvm-svn: 141794
* ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach2011-10-124-9/+84
| | | | llvm-svn: 141786
* 80 columns.Jim Grosbach2011-10-121-2/+1
| | | | llvm-svn: 141781
* Tidy up. Formatting.Jim Grosbach2011-10-121-2/+2
| | | | llvm-svn: 141780
* Fix a thinko that Nick noticed. The previous code actually worked asDan Gohman2011-10-121-1/+1
| | | | | | intended, but only by accident. llvm-svn: 141779
* lib/Object/ELFObjectFile.cpp: Fix undefined behavior for ↵NAKAMURA Takumi2011-10-121-1/+4
| | | | | | | | MC/ELF/many-section.s not to fail (on msvc). DenseMap::lookup(k) would return "default constructor value" when k was not met. It would be useless when value type were POD. llvm-svn: 141774
* Expand the check for a landing pad so that it looks at the basic block'sBill Wendling2011-10-121-5/+11
| | | | | | | containing loop's header to see if that's a landing pad. If it is, then we don't want to hoist instructions out of the loop and above the header. llvm-svn: 141767
* Use an existing function.Jakob Stoklund Olesen2011-10-121-10/+2
| | | | llvm-svn: 141763
* Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it.Akira Hatanaka2011-10-122-13/+5
| | | | llvm-svn: 141761
* Fix encoding of 32-bit integer instructions. Change names of operands and nodes.Akira Hatanaka2011-10-121-87/+108
| | | | | | Remove unused classes. llvm-svn: 141757
* Add missing space.Nick Lewycky2011-10-121-1/+1
| | | | llvm-svn: 141750
* Fix indent in comment.Nick Lewycky2011-10-121-1/+1
| | | | llvm-svn: 141749
* Fix r141744.Evan Cheng2011-10-121-1/+19
| | | | | | | | | 1. The speculation check may not have been performed if the BB hasn't had a load LICM candidate. 2. If the candidate would be CSE'ed, then go ahead and speculatively LICM the instruction even if it's in high register pressure situation. llvm-svn: 141747
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